void tls_timer_clear_irq(void)
{
int value;
value = tls_reg_read32(HR_TIMER1_CSR);
value |= TLS_TIMER_INT_CLR;
tls_reg_write32(HR_TIMER1_CSR, value);
}
void tls_irq_init(void)
{
int i;
for (i=0; i<INTR_CNT; i++) {
intr_handler_vect[i].handler = tls_irq_handler_dummy;
intr_handler_vect[i].data = NULL;
intr_handler_vect[i].name = "intr_dummy";
intr_handler_vect[i].counter = 0;
}
intr_counter = 0;
/* initailize VIC */
tls_reg_write32(HR_VIC_INT_SELECT, 0);
tls_reg_write32(HR_VIC_VECT_ENABLE, 0); /* disable vector interrupt */
tls_reg_write32(HR_VIC_INT_EN_CLR, 0xFFFFFFFF);
}
void tls_set_rtc(struct tm *tblock)
{
int ctrl1 = 0;
int ctrl2 = 0;
ctrl2 = tls_reg_read32(HR_PMU_RTC_CTRL2); //disable
ctrl2 &= ~(1<<16);
tls_reg_write32(HR_PMU_RTC_CTRL2, ctrl2);
ctrl1 |= tblock->tm_sec;
ctrl1 |= tblock->tm_min<<8;
ctrl1 |= tblock->tm_hour<<16;
ctrl1 |= tblock->tm_mday<<24;
tls_reg_write32(HR_PMU_RTC_CTRL1, ctrl1);
ctrl2 = 0;
ctrl2 |= tblock->tm_mon + 1;
ctrl2 |= (tblock->tm_year - 100)<<8;
tls_reg_write32(HR_PMU_RTC_CTRL2, ctrl2);
ctrl2 = tls_reg_read32(HR_PMU_RTC_CTRL2); //enable
ctrl2 |= (1<<16);
tls_reg_write32(HR_PMU_RTC_CTRL2, ctrl2);
}
int spi_demo(char *buf)
{
// int time;
tls_spi_slave_sel(SPI_SLAVE_CARD);
tls_spi_trans_type(2);
tls_spi_setup(TLS_SPI_MODE_0, TLS_SPI_CS_LOW, 100000);
#if CS_CTRL_SOFT
tls_reg_write32(HR_IOCTL_GP_SPI, 2); //cs 作为gpio18使用
tls_gpio_cfg(18, TLS_GPIO_DIR_OUTPUT, TLS_GPIO_ATTR_PULLLOW);
#endif
TestSPIReceiveData();
#if 1
// while(1)
{
TestSPITransferCMD();
TestSPIReceiveData();
OSTimeDly(10);
}
#endif
#if 0
time = OSTimeGet();
printf("\ntime1 = %d\n",time);
for(i = 0;i < 1000;i ++)
#endif
{
//TestSPITransferData();
}
#if 0
time = OSTimeGet();
printf("\ntime1 = %d\n",time);
#endif
return WM_SUCCESS;
}
void UartRegInit(int uart_no)
{
int ioctl;
/* baud rate register value = apb_clk/(16*115200) */
/* 如果APB时钟是40MHz， */
/* 波特率寄存器的值设置为 115200 : 21 */
/* 9600bps : 260 */
if(TLS_UART_0 == uart_no)
{
tls_reg_write32(HR_UART0_BAUD_RATE_CTRL, 21);
/* Line control register : Normal,No parity,1 stop,8 bits, only use tx */
tls_reg_write32(HR_UART0_LINE_CTRL, ULCON_WL8|ULCON_TX_EN);
/* disable auto flow control */
tls_reg_write32(HR_UART0_FLOW_CTRL, 0);
/* disable dma */
tls_reg_write32(HR_UART0_DMA_CTRL, 0);
/* one byte tx */
tls_reg_write32(HR_UART0_FIFO_CTRL, 0);
/* disable interrupt */
tls_reg_write32(HR_UART0_INT_MASK, 0xFF);
//uart0
ioctl = tls_reg_read32(HR_IOCTL_GP_JTAG);
ioctl &= 0xFFFF00FF;
ioctl |= 0x00005500;
tls_reg_write32(HR_IOCTL_GP_JTAG, ioctl);
}
if(TLS_UART_1 == uart_no)
{
/* 4 byte tx, 8 bytes rx */
tls_reg_write32(HR_UART1_FIFO_CTRL, (0x01<<2)|(0x02<<4));
/* enable rx timeout, disable rx dma, disable tx dma */
tls_reg_write32(HR_UART1_DMA_CTRL, (8<<3)|(1<<2));
/* enable rx/timeout interrupt */
tls_reg_write32(HR_UART1_INT_MASK, ~(3<<2));
//uart1
ioctl = tls_reg_read32(HR_IOCTL_GP_SDIO_I2C);
ioctl &= 0xFFFF00FF;
ioctl |= 0x00005500;
tls_reg_write32(HR_IOCTL_GP_SDIO_I2C, ioctl);
}
}
void freeRtos_irq_isr_handler(void)
#endif
{
u32 irq_status = tls_reg_read32(HR_VIC_IRQ_STATUS);
intr_counter++;
if (irq_status & (1UL<<SDIO_DOWN_DATA_INT)) {
intr_handler_vect[SDIO_DOWN_DATA_INT].handler(
(void *)intr_handler_vect[SDIO_DOWN_DATA_INT].data);
intr_handler_vect[SDIO_DOWN_DATA_INT].counter++;
}
if (irq_status & (1UL<<SDIO_DOWN_CMD_INT)) {
intr_handler_vect[SDIO_DOWN_CMD_INT].handler(
(void *)intr_handler_vect[SDIO_DOWN_CMD_INT].data);
intr_handler_vect[SDIO_DOWN_CMD_INT].counter++;
}
if (irq_status & (1UL<<SDIO_UP_DATA_INT)) {
intr_handler_vect[SDIO_UP_DATA_INT].handler(
(void *)intr_handler_vect[SDIO_UP_DATA_INT].data);
intr_handler_vect[SDIO_UP_DATA_INT].counter++;
}
if (irq_status & (1UL<<TIMER0_INT)) {
intr_handler_vect[TIMER0_INT].handler(
(void *)intr_handler_vect[TIMER0_INT].data);
intr_handler_vect[TIMER0_INT].counter++;
}
if (irq_status & (1UL<<TIMER1_INT)) {
intr_handler_vect[TIMER1_INT].handler(
(void *)intr_handler_vect[TIMER1_INT].data);
intr_handler_vect[TIMER1_INT].counter++;
}
if (irq_status & (1UL<<TIMER2_INT)) {
intr_handler_vect[TIMER2_INT].handler(
(void *)intr_handler_vect[TIMER2_INT].data);
intr_handler_vect[TIMER2_INT].counter++;
}
if(irq_status & (1UL<<MAC_INT)) {
intr_handler_vect[MAC_INT].handler(
(void *)intr_handler_vect[MAC_INT].data);
intr_handler_vect[MAC_INT].counter++;
}
if (irq_status & (1UL<<TX_MGMT_COMPLETE_INT)) {
intr_handler_vect[TX_MGMT_COMPLETE_INT].handler(
(void *)intr_handler_vect[TX_MGMT_COMPLETE_INT].data);
intr_handler_vect[TX_MGMT_COMPLETE_INT].counter++;
}
if (irq_status & (1UL<<TX_DATA_COMPLETE_INT)) {
intr_handler_vect[TX_DATA_COMPLETE_INT].handler(
(void *)intr_handler_vect[TX_DATA_COMPLETE_INT].data);
intr_handler_vect[TX_DATA_COMPLETE_INT].counter++;
}
if (irq_status & (1UL<<RX_INT)) {
intr_handler_vect[RX_INT].handler((void *)intr_handler_vect[RX_INT].data);
intr_handler_vect[RX_INT].counter++;
}
if (irq_status & (1UL<<UART0_INT)) {
intr_handler_vect[UART0_INT].handler((void *)intr_handler_vect[UART0_INT].data);
intr_handler_vect[UART0_INT].counter++;
}
if (irq_status & (1UL<<UART1_INT)) {
intr_handler_vect[UART1_INT].handler((void *)intr_handler_vect[UART1_INT].data);
intr_handler_vect[UART1_INT].counter++;
}
if (irq_status & (1UL<<SPI0_INT)) {
intr_handler_vect[SPI0_INT].handler((void *)intr_handler_vect[SPI0_INT].data);
intr_handler_vect[SPI0_INT].counter++;
}
if (irq_status & (1UL<<PM_RTC_INT)) {
intr_handler_vect[PM_RTC_INT].handler((void *)intr_handler_vect[PM_RTC_INT].data);
intr_handler_vect[PM_RTC_INT].counter++;
}
if (irq_status & (1UL<<PM_SLEEP_PERIOD_TIMER_INT)) {
intr_handler_vect[PM_SLEEP_PERIOD_TIMER_INT].handler((void *)intr_handler_vect[PM_SLEEP_PERIOD_TIMER_INT].data);
intr_handler_vect[PM_SLEEP_PERIOD_TIMER_INT].counter++;
}
if (irq_status & (1UL<<GPIO_WAKEUP_INT)) {
intr_handler_vect[GPIO_WAKEUP_INT].handler((void *)intr_handler_vect[GPIO_WAKEUP_INT].data);
intr_handler_vect[GPIO_WAKEUP_INT].counter++;
}
if (irq_status & (1UL<<GPIO_INT)) {
intr_handler_vect[GPIO_INT].handler((void *)intr_handler_vect[GPIO_INT].data);
intr_handler_vect[GPIO_INT].counter++;
}
if (irq_status & (1UL<<DMA0_INT)) {
intr_handler_vect[DMA0_INT].handler((void *)intr_handler_vect[DMA0_INT].data);
intr_handler_vect[DMA0_INT].counter++;
}
if (irq_status & (1UL<<DMA1_INT)) {
intr_handler_vect[DMA1_INT].handler((void *)intr_handler_vect[DMA1_INT].data);
intr_handler_vect[DMA1_INT].counter++;
}
if (irq_status & (1UL<<DMA2_INT)) {
intr_handler_vect[DMA2_INT].handler((void *)intr_handler_vect[DMA2_INT].data);
intr_handler_vect[DMA2_INT].counter++;
}
if (irq_status & (1UL<<DMA3_INT)) {
intr_handler_vect[DMA3_INT].handler((void *)intr_handler_vect[DMA3_INT].data);
intr_handler_vect[DMA3_INT].counter++;
}
if (irq_status & (1UL<<DMA4_INT)) {
intr_handler_vect[DMA4_INT].handler((void *)intr_handler_vect[DMA4_INT].data);
intr_handler_vect[DMA4_INT].counter++;
}
if (irq_status & (1UL<<ADC_INT)) {
intr_handler_vect[ADC_INT].handler((void *)intr_handler_vect[ADC_INT].data);
intr_handler_vect[ADC_INT].counter++;
}
intr_counter --;
/* clear interrupt */
tls_reg_write32(HR_VIC_VECT_ADDR, 0);
}
void tls_irq_disable(u8 vec_no)
{
tls_reg_write32(HR_VIC_INT_ENABLE,
tls_reg_read32(HR_VIC_INT_ENABLE) & ~(1UL<<vec_no));
}