static int armada_drm_bind(struct device *dev)
{
return drm_platform_init(&armada_drm_driver, to_platform_device(dev));
}
static int s3cfb_ioctl(struct fb_info *fb, unsigned int cmd, unsigned long arg)
{
struct s3cfb_global *fbdev =
platform_get_drvdata(to_platform_device(fb->device));
struct fb_var_screeninfo *var = &fb->var;
struct s3cfb_window *win = fb->par;
struct s3cfb_lcd *lcd = fbdev->lcd;
struct fb_fix_screeninfo *fix = &fb->fix;
struct s3cfb_next_info next_fb_info;
int ret = 0;
union {
struct s3cfb_user_window user_window;
struct s3cfb_user_plane_alpha user_alpha;
struct s3cfb_user_chroma user_chroma;
int vsync;
} p;
switch (cmd) {
case FBIO_WAITFORVSYNC:
s3cfb_wait_for_vsync(fbdev);
break;
// Custom IOCTL added to return the VSYNC timestamp
case S3CFB_WAIT_FOR_VSYNC:
ret = s3cfb_wait_for_vsync(fbdev);
if(ret > 0) {
u64 nsecs = ktime_to_ns(fbdev->vsync_timestamp);
copy_to_user((void*)arg, &nsecs, sizeof(u64));
}
break;
case S3CFB_WIN_POSITION:
if (copy_from_user(&p.user_window,
(struct s3cfb_user_window __user *)arg,
sizeof(p.user_window)))
ret = -EFAULT;
else {
if (p.user_window.x < 0)
p.user_window.x = 0;
if (p.user_window.y < 0)
p.user_window.y = 0;
if (p.user_window.x + var->xres > lcd->width)
win->x = lcd->width - var->xres;
else
win->x = p.user_window.x;
if (p.user_window.y + var->yres > lcd->height)
win->y = lcd->height - var->yres;
else
win->y = p.user_window.y;
s3cfb_set_window_position(fbdev, win->id);
}
break;
case S3CFB_WIN_SET_PLANE_ALPHA:
if (copy_from_user(&p.user_alpha,
(struct s3cfb_user_plane_alpha __user *)arg,
sizeof(p.user_alpha)))
ret = -EFAULT;
else {
win->alpha.mode = PLANE_BLENDING;
win->alpha.channel = p.user_alpha.channel;
win->alpha.value =
S3CFB_AVALUE(p.user_alpha.red,
p.user_alpha.green, p.user_alpha.blue);
s3cfb_set_alpha_blending(fbdev, win->id);
}
break;
case S3CFB_WIN_SET_CHROMA:
if (copy_from_user(&p.user_chroma,
(struct s3cfb_user_chroma __user *)arg,
sizeof(p.user_chroma)))
ret = -EFAULT;
else {
win->chroma.enabled = p.user_chroma.enabled;
win->chroma.key = S3CFB_CHROMA(p.user_chroma.red,
p.user_chroma.green,
p.user_chroma.blue);
s3cfb_set_chroma_key(fbdev, win->id);
}
break;
case S3CFB_SET_VSYNC_INT:
if (get_user(p.vsync, (int __user *)arg))
ret = -EFAULT;
else {
if (p.vsync)
s3cfb_set_global_interrupt(fbdev, 1);
s3cfb_set_vsync_interrupt(fbdev, p.vsync);
}
break;
case S3CFB_GET_CURR_FB_INFO:
next_fb_info.phy_start_addr = fix->smem_start;
next_fb_info.xres = var->xres;
next_fb_info.yres = var->yres;
next_fb_info.xres_virtual = var->xres_virtual;
next_fb_info.yres_virtual = var->yres_virtual;
next_fb_info.xoffset = var->xoffset;
next_fb_info.yoffset = var->yoffset;
next_fb_info.lcd_offset_x = 0;
next_fb_info.lcd_offset_y = 0;
if (copy_to_user((void *)arg,
(struct s3cfb_next_info *) &next_fb_info,
sizeof(struct s3cfb_next_info)))
return -EFAULT;
break;
}
return ret;
}
static int s5p_ehci_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct s5p_ehci_platdata *pdata = pdev->dev.platform_data;
struct s5p_ehci_hcd *s5p_ehci = platform_get_drvdata(pdev);
struct usb_hcd *hcd = s5p_ehci->hcd;
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
unsigned long flags;
int rc = 0;
#ifdef CONFIG_MDM_HSIC_PM
/*
* check suspend returns 1 if it is possible to suspend
* otherwise, it returns 0 impossible or returns some error
*/
rc = check_udev_suspend_allowed(hsic_pm_dev);
if (rc > 0) {
set_host_stat(hsic_pm_dev, POWER_OFF);
if (wait_dev_pwr_stat(hsic_pm_dev, POWER_OFF) < 0) {
set_host_stat(hsic_pm_dev, POWER_ON);
pm_runtime_resume(&pdev->dev);
return -EBUSY;
}
} else if (rc == -ENODEV) {
/* no hsic pm driver loaded, proceed suspend */
pr_debug("%s: suspend without hsic pm\n", __func__);
} else {
pm_runtime_resume(&pdev->dev);
return -EBUSY;
}
rc = 0;
#endif
if (time_before(jiffies, ehci->next_statechange))
msleep(10);
/* Root hub was already suspended. Disable irq emission and
* mark HW unaccessible, bail out if RH has been resumed. Use
* the spinlock to properly synchronize with possible pending
* RH suspend or resume activity.
*
* This is still racy as hcd->state is manipulated outside of
* any locks =P But that will be a different fix.
*/
spin_lock_irqsave(&ehci->lock, flags);
if (hcd->state != HC_STATE_SUSPENDED && hcd->state != HC_STATE_HALT) {
spin_unlock_irqrestore(&ehci->lock, flags);
return -EINVAL;
}
ehci_writel(ehci, 0, &ehci->regs->intr_enable);
(void)ehci_readl(ehci, &ehci->regs->intr_enable);
clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
spin_unlock_irqrestore(&ehci->lock, flags);
if (pdata && pdata->phy_exit)
pdata->phy_exit(pdev, S5P_USB_PHY_HOST);
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
if (pdata && pdata->noti_host_states)
pdata->noti_host_states(pdev, S5P_HOST_OFF);
#endif
clk_disable(s5p_ehci->clk);
return rc;
}
/**
* ds1685_rtc_proc - procfs access function.
* @dev: pointer to device structure.
* @seq: pointer to seq_file structure.
*/
static int
ds1685_rtc_proc(struct device *dev, struct seq_file *seq)
{
struct platform_device *pdev = to_platform_device(dev);
struct ds1685_priv *rtc = platform_get_drvdata(pdev);
u8 ctrla, ctrlb, ctrlc, ctrld, ctrl4a, ctrl4b, ssn[8];
char *model;
#ifdef CONFIG_RTC_DS1685_PROC_REGS
char bits[NUM_REGS][(NUM_BITS * NUM_SPACES) + NUM_BITS + 1];
#endif
/* Read all the relevant data from the control registers. */
ds1685_rtc_switch_to_bank1(rtc);
ds1685_rtc_get_ssn(rtc, ssn);
ctrla = rtc->read(rtc, RTC_CTRL_A);
ctrlb = rtc->read(rtc, RTC_CTRL_B);
ctrlc = rtc->read(rtc, RTC_CTRL_C);
ctrld = rtc->read(rtc, RTC_CTRL_D);
ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
ds1685_rtc_switch_to_bank0(rtc);
/* Determine the RTC model. */
switch (ssn[0]) {
case RTC_MODEL_DS1685:
model = "DS1685/DS1687\0";
break;
case RTC_MODEL_DS1689:
model = "DS1689/DS1693\0";
break;
case RTC_MODEL_DS17285:
model = "DS17285/DS17287\0";
break;
case RTC_MODEL_DS17485:
model = "DS17485/DS17487\0";
break;
case RTC_MODEL_DS17885:
model = "DS17885/DS17887\0";
break;
default:
model = "Unknown\0";
break;
}
/* Print out the information. */
seq_printf(seq,
"Model\t\t: %s\n"
"Oscillator\t: %s\n"
"12/24hr\t\t: %s\n"
"DST\t\t: %s\n"
"Data mode\t: %s\n"
"Battery\t\t: %s\n"
"Aux batt\t: %s\n"
"Update IRQ\t: %s\n"
"Periodic IRQ\t: %s\n"
"Periodic Rate\t: %s\n"
"SQW Freq\t: %s\n"
#ifdef CONFIG_RTC_DS1685_PROC_REGS
"Serial #\t: %8phC\n"
"Register Status\t:\n"
" Ctrl A\t: UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0\n"
"\t\t: %s\n"
" Ctrl B\t: SET PIE AIE UIE SQWE DM 2412 DSE\n"
"\t\t: %s\n"
" Ctrl C\t: IRQF PF AF UF --- --- --- ---\n"
"\t\t: %s\n"
" Ctrl D\t: VRT --- --- --- --- --- --- ---\n"
"\t\t: %s\n"
#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689)
" Ctrl 4A\t: VRT2 INCR BME --- PAB RF WF KF\n"
#else
" Ctrl 4A\t: VRT2 INCR --- --- PAB RF WF KF\n"
#endif
"\t\t: %s\n"
" Ctrl 4B\t: ABE E32k CS RCE PRS RIE WIE KSE\n"
"\t\t: %s\n",
#else
"Serial #\t: %8phC\n",
#endif
model,
((ctrla & RTC_CTRL_A_DV1) ? "enabled" : "disabled"),
((ctrlb & RTC_CTRL_B_2412) ? "24-hour" : "12-hour"),
((ctrlb & RTC_CTRL_B_DSE) ? "enabled" : "disabled"),
((ctrlb & RTC_CTRL_B_DM) ? "binary" : "BCD"),
((ctrld & RTC_CTRL_D_VRT) ? "ok" : "exhausted or n/a"),
((ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "exhausted or n/a"),
((ctrlb & RTC_CTRL_B_UIE) ? "yes" : "no"),
((ctrlb & RTC_CTRL_B_PIE) ? "yes" : "no"),
(!(ctrl4b & RTC_CTRL_4B_E32K) ?
ds1685_rtc_pirq_rate[(ctrla & RTC_CTRL_A_RS_MASK)] : "none"),
(!((ctrl4b & RTC_CTRL_4B_E32K)) ?
ds1685_rtc_sqw_freq[(ctrla & RTC_CTRL_A_RS_MASK)] : "32768Hz"),
#ifdef CONFIG_RTC_DS1685_PROC_REGS
ssn,
ds1685_rtc_print_regs(ctrla, bits[0]),
ds1685_rtc_print_regs(ctrlb, bits[1]),
ds1685_rtc_print_regs(ctrlc, bits[2]),
ds1685_rtc_print_regs(ctrld, bits[3]),
ds1685_rtc_print_regs(ctrl4a, bits[4]),
ds1685_rtc_print_regs(ctrl4b, bits[5]));
#else
ssn);
#endif
return 0;
}
void s3cfb_late_resume(struct early_suspend *h)
{
struct s3cfb_global *fbdev =
container_of(h, struct s3cfb_global, early_suspend);
struct s3c_platform_fb *pdata = to_fb_plat(fbdev->dev);
struct platform_device *pdev = to_platform_device(fbdev->dev);
struct fb_info *fb;
struct s3cfb_window *win;
int i, j, ret;
pr_info("s3cfb_late_resume is called\n");
ret = regulator_enable(fbdev->regulator);
if (ret < 0)
dev_err(fbdev->dev, "failed to enable regulator\n");
ret = regulator_enable(fbdev->vcc_lcd);
if (ret < 0)
dev_err(fbdev->dev, "failed to enable vcc_lcd\n");
ret = regulator_enable(fbdev->vlcd);
if (ret < 0)
dev_err(fbdev->dev, "failed to enable vlcd\n");
#if defined(CONFIG_FB_S3C_TL2796)
lcd_cfg_gpio_late_resume();
#endif
dev_dbg(fbdev->dev, "wake up from suspend\n");
if (pdata->cfg_gpio)
pdata->cfg_gpio(pdev);
clk_enable(fbdev->clock);
#ifdef CONFIG_FB_S3C_MDNIE
writel(0x1, S5P_MDNIE_SEL);
writel(3,fbdev->regs + 0x27c);
#endif
s3cfb_init_global(fbdev);
s3cfb_set_clock(fbdev);
#ifdef CONFIG_FB_S3C_MDNIE
s3c_mdnie_init_global(fbdev);
s3c_mdnie_start(fbdev);
#endif
s3cfb_set_alpha_value_width(fbdev, pdata->default_win);
s3cfb_display_on(fbdev);
for (i = pdata->default_win;
i < pdata->nr_wins + pdata->default_win; i++) {
j = i % pdata->nr_wins;
fb = fbdev->fb[j];
win = fb->par;
if ((win->path == DATA_PATH_DMA) && (win->enabled)) {
s3cfb_set_par(fb);
s3cfb_set_window(fbdev, win->id, 1);
}
}
s3cfb_set_vsync_interrupt(fbdev, 1);
s3cfb_set_global_interrupt(fbdev, 1);
if (pdata->backlight_on)
pdata->backlight_on(pdev);
if (pdata->reset_lcd)
pdata->reset_lcd(pdev);
pr_info("s3cfb_late_resume is complete\n");
return ;
}
/**
* ds1685_rtc_set_time - sets the time registers.
* @dev: pointer to device structure.
* @tm: pointer to rtc_time structure.
*/
static int
ds1685_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct platform_device *pdev = to_platform_device(dev);
struct ds1685_priv *rtc = platform_get_drvdata(pdev);
u8 ctrlb, seconds, minutes, hours, wday, mday, month, years, century;
/* Fetch the time info from rtc_time. */
seconds = ds1685_rtc_bin2bcd(rtc, tm->tm_sec, RTC_SECS_BIN_MASK,
RTC_SECS_BCD_MASK);
minutes = ds1685_rtc_bin2bcd(rtc, tm->tm_min, RTC_MINS_BIN_MASK,
RTC_MINS_BCD_MASK);
hours = ds1685_rtc_bin2bcd(rtc, tm->tm_hour, RTC_HRS_24_BIN_MASK,
RTC_HRS_24_BCD_MASK);
wday = ds1685_rtc_bin2bcd(rtc, (tm->tm_wday + 1), RTC_WDAY_MASK,
RTC_WDAY_MASK);
mday = ds1685_rtc_bin2bcd(rtc, tm->tm_mday, RTC_MDAY_BIN_MASK,
RTC_MDAY_BCD_MASK);
month = ds1685_rtc_bin2bcd(rtc, (tm->tm_mon + 1), RTC_MONTH_BIN_MASK,
RTC_MONTH_BCD_MASK);
years = ds1685_rtc_bin2bcd(rtc, (tm->tm_year % 100),
RTC_YEAR_BIN_MASK, RTC_YEAR_BCD_MASK);
century = ds1685_rtc_bin2bcd(rtc, ((tm->tm_year + 1900) / 100),
RTC_CENTURY_MASK, RTC_CENTURY_MASK);
/*
* Perform Sanity Checks:
* - Months: !> 12, Month Day != 0.
* - Month Day !> Max days in current month.
* - Hours !>= 24, Mins !>= 60, Secs !>= 60, & Weekday !> 7.
*/
if ((tm->tm_mon > 11) || (mday == 0))
return -EDOM;
if (tm->tm_mday > rtc_month_days(tm->tm_mon, tm->tm_year))
return -EDOM;
if ((tm->tm_hour >= 24) || (tm->tm_min >= 60) ||
(tm->tm_sec >= 60) || (wday > 7))
return -EDOM;
/*
* Set the data mode to use and store the time values in the
* RTC registers.
*/
ds1685_rtc_begin_data_access(rtc);
ctrlb = rtc->read(rtc, RTC_CTRL_B);
if (rtc->bcd_mode)
ctrlb &= ~(RTC_CTRL_B_DM);
else
ctrlb |= RTC_CTRL_B_DM;
rtc->write(rtc, RTC_CTRL_B, ctrlb);
rtc->write(rtc, RTC_SECS, seconds);
rtc->write(rtc, RTC_MINS, minutes);
rtc->write(rtc, RTC_HRS, hours);
rtc->write(rtc, RTC_WDAY, wday);
rtc->write(rtc, RTC_MDAY, mday);
rtc->write(rtc, RTC_MONTH, month);
rtc->write(rtc, RTC_YEAR, years);
rtc->write(rtc, RTC_CENTURY, century);
ds1685_rtc_end_data_access(rtc);
return 0;
}
/**
* ds1685_rtc_set_alarm - sets the alarm in registers.
* @dev: pointer to device structure.
* @alrm: pointer to rtc_wkalrm structure.
*/
static int
ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct platform_device *pdev = to_platform_device(dev);
struct ds1685_priv *rtc = platform_get_drvdata(pdev);
u8 ctrlb, seconds, minutes, hours, mday;
/* Fetch the alarm info and convert to BCD. */
seconds = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_sec,
RTC_SECS_BIN_MASK,
RTC_SECS_BCD_MASK);
minutes = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_min,
RTC_MINS_BIN_MASK,
RTC_MINS_BCD_MASK);
hours = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_hour,
RTC_HRS_24_BIN_MASK,
RTC_HRS_24_BCD_MASK);
mday = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_mday,
RTC_MDAY_BIN_MASK,
RTC_MDAY_BCD_MASK);
/* Check the month date for validity. */
if (!(mday >= 1) && (mday <= 31))
return -EDOM;
/*
* Check the three alarm bytes.
*
* The Linux RTC system doesn't support the "don't care" capability
* of this RTC chip because rtc_valid_tm tries to validate every
* field, and we only support four fields. We put the support
* here anyways for the future.
*/
if (unlikely(seconds >= 0xc0))
seconds = 0xff;
if (unlikely(minutes >= 0xc0))
minutes = 0xff;
if (unlikely(hours >= 0xc0))
hours = 0xff;
alrm->time.tm_mon = -1;
alrm->time.tm_year = -1;
alrm->time.tm_wday = -1;
alrm->time.tm_yday = -1;
alrm->time.tm_isdst = -1;
/* Disable the alarm interrupt first. */
ds1685_rtc_begin_data_access(rtc);
ctrlb = rtc->read(rtc, RTC_CTRL_B);
rtc->write(rtc, RTC_CTRL_B, (ctrlb & ~(RTC_CTRL_B_AIE)));
/* Read ctrlc to clear RTC_CTRL_C_AF. */
rtc->read(rtc, RTC_CTRL_C);
/*
* Set the data mode to use and store the time values in the
* RTC registers.
*/
ctrlb = rtc->read(rtc, RTC_CTRL_B);
if (rtc->bcd_mode)
ctrlb &= ~(RTC_CTRL_B_DM);
else
ctrlb |= RTC_CTRL_B_DM;
rtc->write(rtc, RTC_CTRL_B, ctrlb);
rtc->write(rtc, RTC_SECS_ALARM, seconds);
rtc->write(rtc, RTC_MINS_ALARM, minutes);
rtc->write(rtc, RTC_HRS_ALARM, hours);
rtc->write(rtc, RTC_MDAY_ALARM, mday);
/* Re-enable the alarm if needed. */
if (alrm->enabled) {
ctrlb = rtc->read(rtc, RTC_CTRL_B);
ctrlb |= RTC_CTRL_B_AIE;
rtc->write(rtc, RTC_CTRL_B, ctrlb);
}
/* Done! */
ds1685_rtc_end_data_access(rtc);
return 0;
}
static int pxa2xx_ac97_remove(struct snd_soc_dai *dai)
{
pxa2xx_ac97_hw_remove(to_platform_device(dai->dev));
return 0;
}
static int dsps_musb_init(struct musb *musb)
{
struct device *dev = musb->controller;
struct dsps_glue *glue = dev_get_drvdata(dev->parent);
struct platform_device *parent = to_platform_device(dev->parent);
const struct dsps_musb_wrapper *wrp = glue->wrp;
void __iomem *reg_base;
struct resource *r;
u32 rev, val;
int ret;
r = platform_get_resource_byname(parent, IORESOURCE_MEM, "control");
reg_base = devm_ioremap_resource(dev, r);
if (IS_ERR(reg_base))
return PTR_ERR(reg_base);
musb->ctrl_base = reg_base;
/* NOP driver needs change if supporting dual instance */
musb->xceiv = devm_usb_get_phy_by_phandle(dev->parent, "phys", 0);
if (IS_ERR(musb->xceiv))
return PTR_ERR(musb->xceiv);
musb->phy = devm_phy_get(dev->parent, "usb2-phy");
/* Returns zero if e.g. not clocked */
rev = dsps_readl(reg_base, wrp->revision);
if (!rev)
return -ENODEV;
usb_phy_init(musb->xceiv);
if (IS_ERR(musb->phy)) {
musb->phy = NULL;
} else {
ret = phy_init(musb->phy);
if (ret < 0)
return ret;
ret = phy_power_on(musb->phy);
if (ret) {
phy_exit(musb->phy);
return ret;
}
}
setup_timer(&glue->timer, otg_timer, (unsigned long) musb);
/* Reset the musb */
dsps_writel(reg_base, wrp->control, (1 << wrp->reset));
musb->isr = dsps_interrupt;
/* reset the otgdisable bit, needed for host mode to work */
val = dsps_readl(reg_base, wrp->phy_utmi);
val &= ~(1 << wrp->otg_disable);
dsps_writel(musb->ctrl_base, wrp->phy_utmi, val);
/*
* Check whether the dsps version has babble control enabled.
* In latest silicon revision the babble control logic is enabled.
* If MUSB_BABBLE_CTL returns 0x4 then we have the babble control
* logic enabled.
*/
val = dsps_readb(musb->mregs, MUSB_BABBLE_CTL);
if (val & MUSB_BABBLE_RCV_DISABLE) {
glue->sw_babble_enabled = true;
val |= MUSB_BABBLE_SW_SESSION_CTRL;
dsps_writeb(musb->mregs, MUSB_BABBLE_CTL, val);
}
return dsps_musb_dbg_init(musb, glue);
}
static void sbus_esp_reset_dma(struct esp *esp)
{
int can_do_burst16, can_do_burst32, can_do_burst64;
int can_do_sbus64, lim;
struct platform_device *op = to_platform_device(esp->dev);
u32 val;
can_do_burst16 = (esp->bursts & DMA_BURST16) != 0;
can_do_burst32 = (esp->bursts & DMA_BURST32) != 0;
can_do_burst64 = 0;
can_do_sbus64 = 0;
if (sbus_can_dma_64bit())
can_do_sbus64 = 1;
if (sbus_can_burst64())
can_do_burst64 = (esp->bursts & DMA_BURST64) != 0;
/* Put the DVMA into a known state. */
if (esp->dmarev != dvmahme) {
val = dma_read32(DMA_CSR);
dma_write32(val | DMA_RST_SCSI, DMA_CSR);
dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
}
switch (esp->dmarev) {
case dvmahme:
dma_write32(DMA_RESET_FAS366, DMA_CSR);
dma_write32(DMA_RST_SCSI, DMA_CSR);
esp->prev_hme_dmacsr = (DMA_PARITY_OFF | DMA_2CLKS |
DMA_SCSI_DISAB | DMA_INT_ENAB);
esp->prev_hme_dmacsr &= ~(DMA_ENABLE | DMA_ST_WRITE |
DMA_BRST_SZ);
if (can_do_burst64)
esp->prev_hme_dmacsr |= DMA_BRST64;
else if (can_do_burst32)
esp->prev_hme_dmacsr |= DMA_BRST32;
if (can_do_sbus64) {
esp->prev_hme_dmacsr |= DMA_SCSI_SBUS64;
sbus_set_sbus64(&op->dev, esp->bursts);
}
lim = 1000;
while (dma_read32(DMA_CSR) & DMA_PEND_READ) {
if (--lim == 0) {
printk(KERN_ALERT PFX "esp%d: DMA_PEND_READ "
"will not clear!\n",
esp->host->unique_id);
break;
}
udelay(1);
}
dma_write32(0, DMA_CSR);
dma_write32(esp->prev_hme_dmacsr, DMA_CSR);
dma_write32(0, DMA_ADDR);
break;
case dvmarev2:
if (esp->rev != ESP100) {
val = dma_read32(DMA_CSR);
dma_write32(val | DMA_3CLKS, DMA_CSR);
}
break;
case dvmarev3:
val = dma_read32(DMA_CSR);
val &= ~DMA_3CLKS;
val |= DMA_2CLKS;
if (can_do_burst32) {
val &= ~DMA_BRST_SZ;
val |= DMA_BRST32;
}
dma_write32(val, DMA_CSR);
break;
case dvmaesc1:
val = dma_read32(DMA_CSR);
val |= DMA_ADD_ENABLE;
val &= ~DMA_BCNT_ENAB;
if (!can_do_burst32 && can_do_burst16) {
val |= DMA_ESC_BURST;
} else {
val &= ~(DMA_ESC_BURST);
}
dma_write32(val, DMA_CSR);
break;
default:
break;
}
/* Enable interrupts. */
val = dma_read32(DMA_CSR);
dma_write32(val | DMA_INT_ENAB, DMA_CSR);
}
static int pxa2xx_ac97_probe(struct snd_soc_dai *dai)
{
return pxa2xx_ac97_hw_probe(to_platform_device(dai->dev));
}
int s5p_dp_psr_exit(struct s5p_dp_device *dp)
{
struct platform_device *pdev;
struct s5p_dp_platdata *pdata;
int timeout_loop = 0;
u8 data;
u32 reg;
int ret = 0;
pdev = to_platform_device(dp->dev);
pdata = pdev->dev.platform_data;
mutex_lock(&dp->lock);
dev_dbg(dp->dev, "%s +\n", __func__);
if (dp->psr_enter_state == PSR_NONE) {
dev_info(dp->dev, "%s: Already edP PSR_EXIT state\n", __func__);
dp->psr_exit_state = PSR_NONE;
mutex_unlock(&dp->lock);
return 0;
}
clk_enable(dp->clock);
s5p_dp_exit_psr(dp);
s5p_dp_set_fifo_reset(dp);
s5p_dp_reset_macro_onoff(dp, 1);
s5p_dp_set_analog_power_down(dp, ANALOG_TOTAL, 0);
if (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
timeout_loop++;
if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
dev_err(dp->dev, "failed to get pll lock status\n");
ret = -ETIMEDOUT;
goto err_exit;
}
udelay(10);
}
}
ndelay(600);
s5p_dp_clear_fifo_reset(dp);
s5p_dp_reset_macro_onoff(dp, 0);
s5p_dp_reset_serdes_fifo(dp);
/* Set sink to D0 (Normal operation) mode. */
s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE,
DPCD_SET_POWER_STATE_D0);
s5p_dp_set_link_train_for_psr(dp, dp->video_info->lane_count,
dp->video_info->link_rate);
s5p_dp_set_idle_en(dp);
timeout_loop = 0;
for (;;) {
timeout_loop++;
if (s5p_dp_get_psr_status(dp) == PSR_STATUS_INACTIVE)
break;
if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
dev_err(dp->dev, "DP: Timeout of PSR inactive\n");
ret = -ETIMEDOUT;
goto err_exit;
}
usleep_range(100, 110);
}
s5p_dp_set_force_stream_valid(dp);
timeout_loop = 0;
for (;;) {
timeout_loop++;
if (s5p_dp_is_video_stream_on(dp) == 0)
break;
if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
dev_err(dp->dev, "Timeout of video streamclk ok\n");
ret = -ETIMEDOUT;
goto err_exit;
}
usleep_range(1000, 1100);
}
timeout_loop = 0;
for (;;) {
timeout_loop++;
s5p_dp_read_byte_from_dpcd(dp,
DPCD_ADDR_SINK_PSR_STATUS,
&data);
if (data == SINK_PSR_INACTIVE_STATE || data == 4) {
break;
}
if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
dev_err(dp->dev, "LCD: Timeout of Sink PSR inactive\n");
ret = -ETIMEDOUT;
goto err_exit;
}
usleep_range(100, 110);
}
dp->psr_enter_state = PSR_NONE;
dp->psr_exit_state = PSR_EXIT_DONE;
dev_dbg(dp->dev, "%s -\n", __func__);
mutex_unlock(&dp->lock);
return ret;
err_exit:
dp->psr_exit_state = PSR_NONE;
dev_dbg(dp->dev, "%s -\n", __func__);
mutex_unlock(&dp->lock);
return ret;
}
static int s5p_dp_psr_enter(struct s5p_dp_device *dp)
{
struct platform_device *pdev;
struct s5p_dp_platdata *pdata;
int timeout_loop = 0;
struct fb_event event;
int ret = 0;
u8 data;
pdev = to_platform_device(dp->dev);
pdata = pdev->dev.platform_data;
mutex_lock(&dp->lock);
dev_dbg(dp->dev, "%s +\n", __func__);
if (dp->psr_enter_state == PSR_ENTER_DONE) {
dev_info(dp->dev, "%s: Already edP PSR_ENTER state\n", __func__);
goto err_exit;
}
if (dp->psr_exit_state == PSR_PRE_EXIT) {
dev_info(dp->dev, "%s: edP does not need to PSR_ENTER\n", __func__);
goto err_exit;
}
dp->psr_enter_state = PSR_PRE_ENTER;
s5p_dp_enable_psr(dp);
for (;;) {
timeout_loop++;
if (s5p_dp_get_psr_status(dp) == PSR_STATUS_ACTIVE)
break;
if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
dev_err(dp->dev, "DP: Timeout of PSR active\n");
ret = -ETIMEDOUT;
dp->psr_enter_state = PSR_NONE;
dp->psr_error_count++;
goto err_exit;
}
mdelay(1);
}
mdelay(2);
dev_dbg(dp->dev, "PSR ENTER DP timeout_loop: %d\n", timeout_loop);
s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_SINK_PSR_STATUS, &data);
if (data == 0)
dev_info(dp->dev, "%s: SINK_PSR_STATUS = 0x%02X\n",
__func__, data);
s5p_dp_set_analog_power_down(dp, ANALOG_TOTAL, 1);
clk_disable(dp->clock);
fb_notifier_call_chain(FB_EVENT_PSR_DONE, &event);
dp->psr_enter_state = PSR_ENTER_DONE;
err_exit:
dev_dbg(dp->dev, "%s -\n", __func__);
mutex_unlock(&dp->lock);
return ret;
}
static int broadcast_tdmb_fc8080_probe(struct spi_device *spi)
{
int rc;
if(spi == NULL)
{
printk("broadcast_fc8080_probe spi is NULL, so spi can not be set\n");
return -1;
}
fc8080_ctrl_info.TdmbPowerOnState = FALSE;
fc8080_ctrl_info.spi_ptr = spi;
fc8080_ctrl_info.spi_ptr->mode = SPI_MODE_0;
fc8080_ctrl_info.spi_ptr->bits_per_word = 8;
fc8080_ctrl_info.spi_ptr->max_speed_hz = (15000*1000);
#ifdef FEATURE_DMB_USE_BUS_SCALE
fc8080_ctrl_info.pdev = to_platform_device(&spi->dev);
fc8080_ctrl_info.bus_scale_pdata = msm_bus_cl_get_pdata(fc8080_ctrl_info.pdev);
fc8080_ctrl_info.bus_scale_client_id = msm_bus_scale_register_client(fc8080_ctrl_info.bus_scale_pdata);
#endif
// Once I have a spi_device structure I can do a transfer anytime
rc = spi_setup(spi);
printk("broadcast_tdmb_fc8080_probe spi_setup=%d\n", rc);
bbm_com_hostif_select(NULL, 1);
#ifdef FEATURE_DMB_USE_XO
fc8080_ctrl_info.clk = clk_get(&fc8080_ctrl_info.spi_ptr->dev, "xo");
if (IS_ERR(fc8080_ctrl_info.clk)) {
rc = PTR_ERR(fc8080_ctrl_info.clk);
dev_err(&fc8080_ctrl_info.spi_ptr->dev, "could not get clock\n");
return rc;
}
/* We enable/disable the clock only to assure it works */
rc = clk_prepare_enable(fc8080_ctrl_info.clk);
if (rc) {
dev_err(&fc8080_ctrl_info.spi_ptr->dev, "could not enable clock\n");
return rc;
}
clk_disable_unprepare(fc8080_ctrl_info.clk);
#endif
#ifdef FEATURE_DMB_USE_WORKQUEUE
INIT_WORK(&fc8080_ctrl_info.spi_work, broacast_tdmb_spi_work);
fc8080_ctrl_info.spi_wq = create_singlethread_workqueue("tdmb_spi_wq");
if(fc8080_ctrl_info.spi_wq == NULL){
printk("Failed to setup tdmb spi workqueue \n");
return -ENOMEM;
}
#endif
tdmb_configure_gpios();
#ifdef FEATURE_DMB_USE_WORKQUEUE
rc = request_irq(spi->irq, broadcast_tdmb_spi_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING,
spi->dev.driver->name, &fc8080_ctrl_info);
#else
rc = request_threaded_irq(spi->irq, NULL, broadcast_tdmb_spi_event_handler, IRQF_ONESHOT | IRQF_DISABLED | IRQF_TRIGGER_FALLING,
spi->dev.driver->name, &fc8080_ctrl_info);
#endif
printk("broadcast_tdmb_fc8080_probe request_irq=%d\n", rc);
tdmb_fc8080_interrupt_lock();
mutex_init(&fc8080_ctrl_info.mutex);
wake_lock_init(&fc8080_ctrl_info.wake_lock, WAKE_LOCK_SUSPEND, dev_name(&spi->dev));
spin_lock_init(&fc8080_ctrl_info.spin_lock);
#ifdef FEATURE_DMB_USE_PM_QOS
pm_qos_add_request(&fc8080_ctrl_info.pm_req_list, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
#endif
printk("broadcast_fc8080_probe End\n");
return rc;
}
/**
* dwc3_otg_init - Initializes otg related registers
* @dwc: Pointer to out controller context structure
*
* Returns 0 on success otherwise negative errno.
*/
int dwc3_otg_init(struct dwc3 *dwc)
{
u32 reg;
int ret = 0;
struct dwc3_otg *dotg;
dev_dbg(dwc->dev, "dwc3_otg_init\n");
/*
* GHWPARAMS6[10] bit is SRPSupport.
* This bit also reflects DWC_USB3_EN_OTG
*/
reg = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
if (!(reg & DWC3_GHWPARAMS6_SRP_SUPPORT)) {
/*
* No OTG support in the HW core.
* We return 0 to indicate no error, since this is acceptable
* situation, just continue probe the dwc3 driver without otg.
*/
dev_dbg(dwc->dev, "dwc3_otg address space is not supported\n");
return 0;
}
/* Allocate and init otg instance */
dotg = kzalloc(sizeof(struct dwc3_otg), GFP_KERNEL);
if (!dotg) {
dev_err(dwc->dev, "unable to allocate dwc3_otg\n");
return -ENOMEM;
}
/* DWC3 has separate IRQ line for OTG events (ID/BSV etc.) */
dotg->irq = platform_get_irq_byname(to_platform_device(dwc->dev),
"otg_irq");
if (dotg->irq < 0) {
dev_err(dwc->dev, "%s: missing OTG IRQ\n", __func__);
ret = -ENODEV;
goto err1;
}
dotg->regs = dwc->regs;
dotg->otg.set_peripheral = dwc3_otg_set_peripheral;
dotg->otg.set_host = dwc3_otg_set_host;
/* This reference is used by dwc3 modules for checking otg existance */
dwc->dotg = dotg;
dotg->otg.phy = kzalloc(sizeof(struct usb_phy), GFP_KERNEL);
if (!dotg->otg.phy) {
dev_err(dwc->dev, "unable to allocate dwc3_otg.phy\n");
ret = -ENOMEM;
goto err1;
}
dotg->dwc = dwc;
dotg->otg.phy->otg = &dotg->otg;
dotg->otg.phy->dev = dwc->dev;
dotg->otg.phy->set_power = dwc3_otg_set_power;
dotg->otg.phy->set_suspend = dwc3_otg_set_suspend;
ret = usb_set_transceiver(dotg->otg.phy);
if (ret) {
dev_err(dotg->otg.phy->dev,
"%s: failed to set transceiver, already exists\n",
__func__);
goto err2;
}
dotg->otg.phy->state = OTG_STATE_UNDEFINED;
init_completion(&dotg->dwc3_xcvr_vbus_init);
INIT_DELAYED_WORK(&dotg->sm_work, dwc3_otg_sm_work);
ret = request_irq(dotg->irq, dwc3_otg_interrupt, IRQF_SHARED,
"dwc3_otg", dotg);
if (ret) {
dev_err(dotg->otg.phy->dev, "failed to request irq #%d --> %d\n",
dotg->irq, ret);
goto err3;
}
pm_runtime_get(dwc->dev);
return 0;
err3:
cancel_delayed_work_sync(&dotg->sm_work);
usb_set_transceiver(NULL);
err2:
kfree(dotg->otg.phy);
err1:
dwc->dotg = NULL;
kfree(dotg);
return ret;
}
static int usbhs_omap_remove_child(struct device *dev, void *data)
{
dev_info(dev, "unregistering\n");
platform_device_unregister(to_platform_device(dev));
return 0;
}
/* subdevs */
static int pcap_remove_subdev(struct device *dev, void *unused)
{
platform_device_unregister(to_platform_device(dev));
return 0;
}
int gfar_mdio_probe(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct gianfar_mdio_data *pdata;
struct gfar_mii __iomem *regs;
struct mii_bus *new_bus;
struct resource *r;
int err = 0;
if (NULL == dev)
return -EINVAL;
new_bus = kzalloc(sizeof(struct mii_bus), GFP_KERNEL);
if (NULL == new_bus)
return -ENOMEM;
new_bus->name = "Gianfar MII Bus",
new_bus->read = &gfar_mdio_read,
new_bus->write = &gfar_mdio_write,
new_bus->reset = &gfar_mdio_reset,
new_bus->id = pdev->id;
pdata = (struct gianfar_mdio_data *)pdev->dev.platform_data;
if (NULL == pdata) {
printk(KERN_ERR "gfar mdio %d: Missing platform data!\n", pdev->id);
return -ENODEV;
}
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
/* Set the PHY base address */
regs = ioremap(r->start, sizeof (struct gfar_mii));
if (NULL == regs) {
err = -ENOMEM;
goto reg_map_fail;
}
new_bus->priv = (void __force *)regs;
new_bus->irq = pdata->irq;
new_bus->dev = dev;
dev_set_drvdata(dev, new_bus);
err = mdiobus_register(new_bus);
if (0 != err) {
printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
new_bus->name);
goto bus_register_fail;
}
return 0;
bus_register_fail:
iounmap(regs);
reg_map_fail:
kfree(new_bus);
return err;
}
/**
* ds1685_rtc_read_alarm - reads the alarm registers.
* @dev: pointer to device structure.
* @alrm: pointer to rtc_wkalrm structure.
*
* There are three primary alarm registers: seconds, minutes, and hours.
* A fourth alarm register for the month date is also available in bank1 for
* kickstart/wakeup features. The DS1685/DS1687 manual states that a
* "don't care" value ranging from 0xc0 to 0xff may be written into one or
* more of the three alarm bytes to act as a wildcard value. The fourth
* byte doesn't support a "don't care" value.
*/
static int
ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct platform_device *pdev = to_platform_device(dev);
struct ds1685_priv *rtc = platform_get_drvdata(pdev);
u8 seconds, minutes, hours, mday, ctrlb, ctrlc;
/* Fetch the alarm info from the RTC alarm registers. */
ds1685_rtc_begin_data_access(rtc);
seconds = rtc->read(rtc, RTC_SECS_ALARM);
minutes = rtc->read(rtc, RTC_MINS_ALARM);
hours = rtc->read(rtc, RTC_HRS_ALARM);
mday = rtc->read(rtc, RTC_MDAY_ALARM);
ctrlb = rtc->read(rtc, RTC_CTRL_B);
ctrlc = rtc->read(rtc, RTC_CTRL_C);
ds1685_rtc_end_data_access(rtc);
/* Check month date. */
if (!(mday >= 1) && (mday <= 31))
return -EDOM;
/*
* Check the three alarm bytes.
*
* The Linux RTC system doesn't support the "don't care" capability
* of this RTC chip. We check for it anyways in case support is
* added in the future.
*/
if (unlikely(seconds >= 0xc0))
alrm->time.tm_sec = -1;
else
alrm->time.tm_sec = ds1685_rtc_bcd2bin(rtc, seconds,
RTC_SECS_BCD_MASK,
RTC_SECS_BIN_MASK);
if (unlikely(minutes >= 0xc0))
alrm->time.tm_min = -1;
else
alrm->time.tm_min = ds1685_rtc_bcd2bin(rtc, minutes,
RTC_MINS_BCD_MASK,
RTC_MINS_BIN_MASK);
if (unlikely(hours >= 0xc0))
alrm->time.tm_hour = -1;
else
alrm->time.tm_hour = ds1685_rtc_bcd2bin(rtc, hours,
RTC_HRS_24_BCD_MASK,
RTC_HRS_24_BIN_MASK);
/* Write the data to rtc_wkalrm. */
alrm->time.tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
RTC_MDAY_BIN_MASK);
alrm->time.tm_mon = -1;
alrm->time.tm_year = -1;
alrm->time.tm_wday = -1;
alrm->time.tm_yday = -1;
alrm->time.tm_isdst = -1;
alrm->enabled = !!(ctrlb & RTC_CTRL_B_AIE);
alrm->pending = !!(ctrlc & RTC_CTRL_C_AF);
return 0;
}
static inline char *s3c24xx_serial_portname(struct uart_port *port)
{
return to_platform_device(port->dev)->name;
}
/**
* ds1685_rtc_work_queue - work queue handler.
* @work: work_struct containing data to work on in task context.
*/
static void
ds1685_rtc_work_queue(struct work_struct *work)
{
struct ds1685_priv *rtc = container_of(work,
struct ds1685_priv, work);
struct platform_device *pdev = to_platform_device(&rtc->dev->dev);
struct mutex *rtc_mutex = &rtc->dev->ops_lock;
u8 ctrl4a, ctrl4b;
mutex_lock(rtc_mutex);
ds1685_rtc_switch_to_bank1(rtc);
ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
/*
* Check for a kickstart interrupt. With Vcc applied, this
* typically means that the power button was pressed, so we
* begin the shutdown sequence.
*/
if ((ctrl4b & RTC_CTRL_4B_KSE) && (ctrl4a & RTC_CTRL_4A_KF)) {
/* Briefly disable kickstarts to debounce button presses. */
rtc->write(rtc, RTC_EXT_CTRL_4B,
(rtc->read(rtc, RTC_EXT_CTRL_4B) &
~(RTC_CTRL_4B_KSE)));
/* Clear the kickstart flag. */
rtc->write(rtc, RTC_EXT_CTRL_4A,
(ctrl4a & ~(RTC_CTRL_4A_KF)));
/*
* Sleep 500ms before re-enabling kickstarts. This allows
* adequate time to avoid reading signal jitter as additional
* button presses.
*/
msleep(500);
rtc->write(rtc, RTC_EXT_CTRL_4B,
(rtc->read(rtc, RTC_EXT_CTRL_4B) |
RTC_CTRL_4B_KSE));
/* Call the platform pre-poweroff function. Else, shutdown. */
if (rtc->prepare_poweroff != NULL)
rtc->prepare_poweroff();
else
ds1685_rtc_poweroff(pdev);
}
/*
* Check for a wake-up interrupt. With Vcc applied, this is
* essentially a second alarm interrupt, except it takes into
* account the 'date' register in bank1 in addition to the
* standard three alarm registers.
*/
if ((ctrl4b & RTC_CTRL_4B_WIE) && (ctrl4a & RTC_CTRL_4A_WF)) {
rtc->write(rtc, RTC_EXT_CTRL_4A,
(ctrl4a & ~(RTC_CTRL_4A_WF)));
/* Call the platform wake_alarm function if defined. */
if (rtc->wake_alarm != NULL)
rtc->wake_alarm();
else
dev_warn(&pdev->dev,
"Wake Alarm IRQ just occurred!\n");
}
/*
* Check for a ram-clear interrupt. This happens if RIE=1 and RF=0
* when RCE=1 in 4B. This clears all NVRAM bytes in bank0 by setting
* each byte to a logic 1. This has no effect on any extended
* NV-SRAM that might be present, nor on the time/calendar/alarm
* registers. After a ram-clear is completed, there is a minimum
* recovery time of ~150ms in which all reads/writes are locked out.
* NOTE: A ram-clear can still occur if RCE=1 and RIE=0. We cannot
* catch this scenario.
*/
if ((ctrl4b & RTC_CTRL_4B_RIE) && (ctrl4a & RTC_CTRL_4A_RF)) {
rtc->write(rtc, RTC_EXT_CTRL_4A,
(ctrl4a & ~(RTC_CTRL_4A_RF)));
msleep(150);
/* Call the platform post_ram_clear function if defined. */
if (rtc->post_ram_clear != NULL)
rtc->post_ram_clear();
else
dev_warn(&pdev->dev,
"RAM-Clear IRQ just occurred!\n");
}
ds1685_rtc_switch_to_bank0(rtc);
mutex_unlock(rtc_mutex);
}
static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
struct omap_wdt_dev *wdev;
int new_margin;
static const struct watchdog_info ident = {
.identity = "OMAP Watchdog",
.options = WDIOF_SETTIMEOUT,
.firmware_version = 0,
};
wdev = file->private_data;
switch (cmd) {
case WDIOC_GETSUPPORT:
return copy_to_user((struct watchdog_info __user *)arg, &ident,
sizeof(ident));
case WDIOC_GETSTATUS:
return put_user(0, (int __user *)arg);
case WDIOC_GETBOOTSTATUS:
if (cpu_is_omap16xx())
return put_user(__raw_readw(ARM_SYSST),
(int __user *)arg);
if (cpu_is_omap24xx())
return put_user(omap_prcm_get_reset_sources(),
(int __user *)arg);
return -ENOTTY;
case WDIOC_KEEPALIVE:
spin_lock(&wdt_lock);
omap_wdt_ping(wdev);
spin_unlock(&wdt_lock);
return 0;
case WDIOC_SETTIMEOUT:
if (get_user(new_margin, (int __user *)arg))
return -EFAULT;
omap_wdt_adjust_timeout(new_margin);
spin_lock(&wdt_lock);
omap_wdt_disable(wdev);
omap_wdt_set_timeout(wdev);
omap_wdt_enable(wdev);
omap_wdt_ping(wdev);
spin_unlock(&wdt_lock);
/* Fall */
case WDIOC_GETTIMEOUT:
return put_user(timer_margin, (int __user *)arg);
default:
return -ENOTTY;
}
}
static const struct file_operations omap_wdt_fops = {
.owner = THIS_MODULE,
.write = omap_wdt_write,
.unlocked_ioctl = omap_wdt_ioctl,
.open = omap_wdt_open,
.release = omap_wdt_release,
.llseek = no_llseek,
};
static int omap_wdt_nb_func(struct notifier_block *nb, unsigned long val,
void *v)
{
struct omap_wdt_dev *wdev = container_of(nb, struct omap_wdt_dev, nb);
omap_wdt_ping(wdev);
return NOTIFY_OK;
}
static int __devinit omap_wdt_probe(struct platform_device *pdev)
{
struct resource *res, *mem, *res_irq;
struct omap_wdt_dev *wdev;
int ret;
/* reserve static register mappings */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
ret = -ENOENT;
goto err_get_resource;
}
if (omap_wdt_dev) {
ret = -EBUSY;
goto err_busy;
}
mem = request_mem_region(res->start, resource_size(res), pdev->name);
if (!mem) {
ret = -EBUSY;
goto err_busy;
}
res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
wdev = kzalloc(sizeof(struct omap_wdt_dev), GFP_KERNEL);
if (!wdev) {
ret = -ENOMEM;
goto err_kzalloc;
}
wdev->omap_wdt_users = 0;
wdev->mem = mem;
wdev->dev = &pdev->dev;
wdev->base = ioremap(res->start, resource_size(res));
if (!wdev->base) {
ret = -ENOMEM;
goto err_ioremap;
}
if (res_irq) {
ret = request_irq(res_irq->start, omap_wdt_interrupt, 0,
dev_name(&pdev->dev), wdev);
if (ret)
goto err_irq;
wdev->irq = res_irq->start;
}
platform_set_drvdata(pdev, wdev);
/*
* Note: PM runtime functions must be used only when watchdog driver
* is enabling/disabling. Dynamic handling of clock of watchdog timer on
* OMAP4/5 (like provided with runtime API) will cause system failure
*/
pm_runtime_enable(wdev->dev);
pm_runtime_irq_safe(wdev->dev);
pm_runtime_get_sync(wdev->dev);
omap_wdt_disable(wdev);
omap_wdt_adjust_timeout(timer_margin);
wdev->omap_wdt_miscdev.parent = &pdev->dev;
wdev->omap_wdt_miscdev.minor = WATCHDOG_MINOR;
wdev->omap_wdt_miscdev.name = "watchdog";
wdev->omap_wdt_miscdev.fops = &omap_wdt_fops;
ret = misc_register(&(wdev->omap_wdt_miscdev));
if (ret)
goto err_misc;
pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
__raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
timer_margin);
omap_wdt_dev = pdev;
if (kernelpet && wdev->irq) {
wdev->nb.notifier_call = omap_wdt_nb_func;
atomic_notifier_chain_register(&touch_watchdog_notifier_head,
&wdev->nb);
return omap_wdt_setup(wdev);
}
pm_runtime_put_sync(wdev->dev);
return 0;
err_misc:
pm_runtime_put_sync(wdev->dev);
platform_set_drvdata(pdev, NULL);
if (wdev->irq)
free_irq(wdev->irq, wdev);
err_irq:
iounmap(wdev->base);
err_ioremap:
wdev->base = NULL;
kfree(wdev);
err_kzalloc:
release_mem_region(res->start, resource_size(res));
err_busy:
err_get_resource:
return ret;
}
static void omap_wdt_shutdown(struct platform_device *pdev)
{
struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
if (wdev->omap_wdt_users) {
omap_wdt_disable(wdev);
pm_runtime_put_sync(wdev->dev);
}
}
static int __devexit omap_wdt_remove(struct platform_device *pdev)
{
struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENOENT;
misc_deregister(&(wdev->omap_wdt_miscdev));
release_mem_region(res->start, resource_size(res));
platform_set_drvdata(pdev, NULL);
if (wdev->irq)
free_irq(wdev->irq, wdev);
if (kernelpet && wdev->irq)
atomic_notifier_chain_unregister(&touch_watchdog_notifier_head,
&wdev->nb);
iounmap(wdev->base);
kfree(wdev);
omap_wdt_dev = NULL;
return 0;
}
#ifdef CONFIG_PM
/* REVISIT ... not clear this is the best way to handle system suspend; and
* it's very inappropriate for selective device suspend (e.g. suspending this
* through sysfs rather than by stopping the watchdog daemon). Also, this
* may not play well enough with NOWAYOUT...
*/
static int omap_wdt_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
if (wdev->omap_wdt_users) {
omap_wdt_disable(wdev);
pm_runtime_put_sync_suspend(wdev->dev);
}
return 0;
}
static int omap_wdt_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
if (wdev->omap_wdt_users) {
pm_runtime_get_sync(wdev->dev);
omap_wdt_enable(wdev);
omap_wdt_ping(wdev);
}
return 0;
}
#else
#define omap_wdt_suspend NULL
#define omap_wdt_resume NULL
#endif
static const struct dev_pm_ops omap_wdt_pm_ops = {
.suspend_noirq = omap_wdt_suspend,
.resume_noirq = omap_wdt_resume,
};
static struct platform_driver omap_wdt_driver = {
.probe = omap_wdt_probe,
.remove = __devexit_p(omap_wdt_remove),
.shutdown = omap_wdt_shutdown,
.driver = {
.owner = THIS_MODULE,
.name = "omap_wdt",
.pm = &omap_wdt_pm_ops,
},
};
static int __init omap_wdt_init(void)
{
spin_lock_init(&wdt_lock);
return platform_driver_register(&omap_wdt_driver);
}
static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
{
struct exynos_dp_device *dp = dev_get_drvdata(dev);
struct platform_device *pdev = to_platform_device(dev);
struct drm_device *drm_dev = data;
struct drm_encoder *encoder = &dp->encoder;
struct resource *res;
unsigned int irq_flags;
int pipe, ret = 0;
dp->dev = &pdev->dev;
dp->dpms_mode = DRM_MODE_DPMS_OFF;
dp->video_info = exynos_dp_dt_parse_pdata(&pdev->dev);
if (IS_ERR(dp->video_info))
return PTR_ERR(dp->video_info);
dp->phy = devm_phy_get(dp->dev, "dp");
if (IS_ERR(dp->phy)) {
dev_err(dp->dev, "no DP phy configured\n");
ret = PTR_ERR(dp->phy);
if (ret) {
/*
* phy itself is not enabled, so we can move forward
* assigning NULL to phy pointer.
*/
if (ret == -ENOSYS || ret == -ENODEV)
dp->phy = NULL;
else
return ret;
}
}
if (!dp->panel && !dp->ptn_bridge) {
ret = exynos_dp_dt_parse_panel(dp);
if (ret)
return ret;
}
dp->clock = devm_clk_get(&pdev->dev, "dp");
if (IS_ERR(dp->clock)) {
dev_err(&pdev->dev, "failed to get clock\n");
return PTR_ERR(dp->clock);
}
clk_prepare_enable(dp->clock);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(dp->reg_base))
return PTR_ERR(dp->reg_base);
dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0);
if (gpio_is_valid(dp->hpd_gpio)) {
/*
* Set up the hotplug GPIO from the device tree as an interrupt.
* Simply specifying a different interrupt in the device tree
* doesn't work since we handle hotplug rather differently when
* using a GPIO. We also need the actual GPIO specifier so
* that we can get the current state of the GPIO.
*/
ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN,
"hpd_gpio");
if (ret) {
dev_err(&pdev->dev, "failed to get hpd gpio\n");
return ret;
}
dp->irq = gpio_to_irq(dp->hpd_gpio);
irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
} else {
dp->hpd_gpio = -ENODEV;
dp->irq = platform_get_irq(pdev, 0);
irq_flags = 0;
}
if (dp->irq == -ENXIO) {
dev_err(&pdev->dev, "failed to get irq\n");
return -ENODEV;
}
INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler,
irq_flags, "exynos-dp", dp);
if (ret) {
dev_err(&pdev->dev, "failed to request irq\n");
return ret;
}
disable_irq(dp->irq);
dp->drm_dev = drm_dev;
pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
EXYNOS_DISPLAY_TYPE_LCD);
if (pipe < 0)
return pipe;
encoder->possible_crtcs = 1 << pipe;
DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
drm_encoder_init(drm_dev, encoder, &exynos_dp_encoder_funcs,
DRM_MODE_ENCODER_TMDS, NULL);
drm_encoder_helper_add(encoder, &exynos_dp_encoder_helper_funcs);
ret = exynos_dp_create_connector(encoder);
if (ret) {
DRM_ERROR("failed to create connector ret = %d\n", ret);
drm_encoder_cleanup(encoder);
return ret;
}
return 0;
}
static int ixp2000_flash_probe(struct device *_dev)
{
static const char *probes[] = { "RedBoot", "cmdlinepart", NULL };
struct platform_device *dev = to_platform_device(_dev);
struct ixp2000_flash_data *ixp_data = dev->dev.platform_data;
struct flash_platform_data *plat;
struct ixp2000_flash_info *info;
unsigned long window_size;
int err = -1;
if (!ixp_data)
return -ENODEV;
plat = ixp_data->platform_data;
if (!plat)
return -ENODEV;
window_size = dev->resource->end - dev->resource->start + 1;
dev_info(_dev, "Probe of IXP2000 flash(%d banks x %dMiB)\n",
ixp_data->nr_banks, ((u32)window_size >> 20));
if (plat->width != 1) {
dev_err(_dev, "IXP2000 MTD map only supports 8-bit mode, asking for %d\n",
plat->width * 8);
return -EIO;
}
info = kmalloc(sizeof(struct ixp2000_flash_info), GFP_KERNEL);
if(!info) {
err = -ENOMEM;
goto Error;
}
memzero(info, sizeof(struct ixp2000_flash_info));
dev_set_drvdata(&dev->dev, info);
/*
* Tell the MTD layer we're not 1:1 mapped so that it does
* not attempt to do a direct access on us.
*/
info->map.phys = NO_XIP;
info->nr_banks = ixp_data->nr_banks;
info->map.size = ixp_data->nr_banks * window_size;
info->map.bankwidth = 1;
/*
* map_priv_2 is used to store a ptr to to the bank_setup routine
*/
info->map.map_priv_2 = (void __iomem *) ixp_data->bank_setup;
info->map.name = dev->dev.bus_id;
info->map.read = ixp2000_flash_read8;
info->map.write = ixp2000_flash_write8;
info->map.copy_from = ixp2000_flash_copy_from;
info->map.copy_to = ixp2000_flash_copy_to;
info->res = request_mem_region(dev->resource->start,
dev->resource->end - dev->resource->start + 1,
dev->dev.bus_id);
if (!info->res) {
dev_err(_dev, "Could not reserve memory region\n");
err = -ENOMEM;
goto Error;
}
info->map.map_priv_1 =
(void __iomem *) ioremap(dev->resource->start,
dev->resource->end - dev->resource->start + 1);
if (!info->map.map_priv_1) {
dev_err(_dev, "Failed to ioremap flash region\n");
err = -EIO;
goto Error;
}
/*
* Setup read mode for FLASH
*/
*IXP2000_SLOWPORT_FRM = 1;
#if defined(__ARMEB__)
/*
* Enable erratum 44 workaround for NPUs with broken slowport
*/
errata44_workaround = ixp2000_has_broken_slowport();
dev_info(_dev, "Erratum 44 workaround %s\n",
erratum44_workaround ? "enabled" : "disabled");
#endif
info->mtd = do_map_probe(plat->map_name, &info->map);
if (!info->mtd) {
dev_err(_dev, "map_probe failed\n");
err = -ENXIO;
goto Error;
}
info->mtd->owner = THIS_MODULE;
err = parse_mtd_partitions(info->mtd, probes, &info->partitions, 0);
if (err > 0) {
err = add_mtd_partitions(info->mtd, info->partitions, err);
if(err)
dev_err(_dev, "Could not parse partitions\n");
}
if (err)
goto Error;
return 0;
Error:
ixp2000_flash_remove(_dev);
return err;
}
struct s3c_platform_fb *to_fb_plat(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
return (struct s3c_platform_fb *)pdev->dev.platform_data;
}
int s5ptvfb_init_fbinfo(int id)
{
struct fb_info *fb = s5ptv_status.fb;
struct fb_fix_screeninfo *fix = &fb->fix;
struct fb_var_screeninfo *var = &fb->var;
struct s5ptvfb_window *win = fb->par;
struct s5ptvfb_alpha *alpha = &win->alpha;
struct s5ptvfb_lcd *lcd = s5ptv_status.lcd;
struct s5ptvfb_lcd_timing *timing = &lcd->timing;
memset(win, 0, sizeof(struct s5ptvfb_window));
platform_set_drvdata(to_platform_device(s5ptv_status.dev_fb), fb);
strcpy(fix->id, S5PTVFB_NAME);
/* fimd specific */
win->id = id;
win->path = DATA_PATH_DMA;
win->dma_burst = 16;
alpha->mode = PLANE_BLENDING;
/* fbinfo */
fb->fbops = &s5ptvfb_ops;
fb->flags = FBINFO_FLAG_DEFAULT;
fb->pseudo_palette = &win->pseudo_pal;
fix->xpanstep = 0;
fix->ypanstep = 0;
fix->type = FB_TYPE_PACKED_PIXELS;
fix->accel = FB_ACCEL_NONE;
fix->visual = FB_VISUAL_TRUECOLOR;
var->xres = lcd->width;
var->yres = lcd->height;
var->xres_virtual = var->xres;
var->yres_virtual = var->yres + (var->yres * fix->ypanstep);
var->bits_per_pixel = 32;
var->xoffset = 0;
var->yoffset = 0;
var->width = 0;
var->height = 0;
var->transp.length = 0;
fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
fix->smem_len = fix->line_length * var->yres_virtual;
var->nonstd = 0;
var->activate = FB_ACTIVATE_NOW;
var->vmode = FB_VMODE_NONINTERLACED;
var->hsync_len = timing->h_sw;
var->vsync_len = timing->v_sw;
var->left_margin = timing->h_fp;
var->right_margin = timing->h_bp;
var->upper_margin = timing->v_fp;
var->lower_margin = timing->v_bp;
var->pixclock = lcd->freq * (var->left_margin + var->right_margin +
var->hsync_len + var->xres) *
(var->upper_margin + var->lower_margin +
var->vsync_len + var->yres);
dev_dbg(s5ptv_status.dev_fb, "pixclock: %d\n", var->pixclock);
s5ptvfb_set_bitfield(var);
s5ptvfb_set_alpha_info(var, win);
return 0;
}
static void s3cfb_init_fbinfo(struct s3cfb_global *ctrl, int id)
{
struct fb_info *fb = ctrl->fb[id];
struct fb_fix_screeninfo *fix = &fb->fix;
struct fb_var_screeninfo *var = &fb->var;
struct s3cfb_window *win = fb->par;
struct s3cfb_alpha *alpha = &win->alpha;
struct s3cfb_lcd *lcd = ctrl->lcd;
struct s3cfb_lcd_timing *timing = &lcd->timing;
memset(win, 0, sizeof(*win));
platform_set_drvdata(to_platform_device(ctrl->dev), ctrl);
strcpy(fix->id, S3CFB_NAME);
win->id = id;
win->path = DATA_PATH_DMA;
win->dma_burst = 16;
alpha->mode = PLANE_BLENDING;
fb->fbops = &s3cfb_ops;
fb->flags = FBINFO_FLAG_DEFAULT;
fb->pseudo_palette = &win->pseudo_pal;
#if (CONFIG_FB_S3C_NR_BUFFERS != 1)
fix->xpanstep = 2;
fix->ypanstep = 1;
#else
fix->xpanstep = 0;
fix->ypanstep = 0;
#endif
fix->type = FB_TYPE_PACKED_PIXELS;
fix->accel = FB_ACCEL_NONE;
fix->visual = FB_VISUAL_TRUECOLOR;
var->xres = lcd->width;
var->yres = lcd->height;
#if defined(CONFIG_FB_S3C_VIRTUAL)
var->xres_virtual = CONFIG_FB_S3C_X_VRES;
var->yres_virtual = CONFIG_FB_S3C_Y_VRES * CONFIG_FB_S3C_NR_BUFFERS;
#else
var->xres_virtual = var->xres;
var->yres_virtual = var->yres * CONFIG_FB_S3C_NR_BUFFERS;
#endif
var->bits_per_pixel = 32;
var->xoffset = 0;
var->yoffset = 0;
var->width = lcd->p_width;
var->height = lcd->p_height;
var->transp.length = 0;
fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
fix->smem_len = fix->line_length * var->yres_virtual;
var->nonstd = 0;
var->activate = FB_ACTIVATE_NOW;
var->vmode = FB_VMODE_NONINTERLACED;
var->hsync_len = timing->h_sw;
var->vsync_len = timing->v_sw;
var->left_margin = timing->h_fp;
var->right_margin = timing->h_bp;
var->upper_margin = timing->v_fp;
var->lower_margin = timing->v_bp;
ctrl->pixclock_hz = lcd->freq * (var->left_margin + var->right_margin +
var->hsync_len + var->xres) *
(var->upper_margin + var->lower_margin +
var->vsync_len + var->yres);
var->pixclock = KHZ2PICOS(ctrl->pixclock_hz / 1000);
dev_dbg(ctrl->dev, "pixclock: %d\n", var->pixclock);
s3cfb_set_bitfield(var);
s3cfb_set_alpha_info(var, win);
}
static int zylonite_mci_init(struct device *dev, irqreturn_t (*zylonite_detect_int)(int, void *, struct pt_regs *), void *data)
{
int err;
struct platform_device *pdev = to_platform_device(dev);
/*
* setup GPIO for Zylonite MMC controller
*/
if (pdev->id == 0) {
zylonite_enable_mmc1_pins();
#ifndef CONFIG_PXA3xx_MMC2
/* set direction of CD/WP to IN */
mhn_gpio_set_direction(MFP_MMC_CD_0_GPIO, GPIO_DIR_IN);
mhn_gpio_set_direction(MFP_MMC_WP_0_N_GPIO, GPIO_DIR_IN);
/* CD is configured to Falling/Rising Edge detect */
mhn_gpio_set_falling_edge_detect(MFP_MMC_CD_0_GPIO, 1);
mhn_gpio_set_rising_edge_detect (MFP_MMC_CD_0_GPIO, 1);
err = request_irq(MMC1_CD0, zylonite_detect_int, 0,
"MMC card detect slot 1", data);
if (err) {
printk(KERN_ERR
"MMC/SD: can't request MMC card detect"
" IRQ for slot 1\n");
return -1;
}
set_irq_type(MMC1_CD0, IRQT_BOTHEDGE);
#else
/* set direction of CD/WP to IN */
mhn_gpio_set_direction(MFP_MMC_CD_1_GPIO, GPIO_DIR_IN);
mhn_gpio_set_direction(MFP_MMC_WP_1_N_GPIO, GPIO_DIR_IN);
/* CD is configured to Falling/Rising Edge detect */
mhn_gpio_set_falling_edge_detect(MFP_MMC_CD_1_GPIO, 1);
mhn_gpio_set_rising_edge_detect (MFP_MMC_CD_1_GPIO, 1);
err = request_irq(MMC1_CD1, zylonite_detect_int, 0,
"MMC card detect slot 2", data);
if (err) {
printk(KERN_ERR
"MMC/SD: can't request MMC card detect"
" IRQ for slot 2\n");
return -1;
}
set_irq_type(MMC1_CD1, IRQT_BOTHEDGE);
#endif
}
#ifdef CONFIG_PXA310_MMC3 /* 3d MMC/SD slot on Monahans LV */
else if (pdev->id == 1) {
zylonite_enable_mmc3_pins();
/* set direction of CD/WP to IN */
mhn_gpio_set_direction(MFP_MMC_CD_3_GPIO, GPIO_DIR_IN);
mhn_gpio_set_direction(MFP_MMC_WP_3_N_GPIO, GPIO_DIR_IN);
/* CD is configured to Falling/Rising Edge detect */
mhn_gpio_set_falling_edge_detect(MFP_MMC_CD_3_GPIO, 1);
mhn_gpio_set_rising_edge_detect (MFP_MMC_CD_3_GPIO, 1);
err = request_irq(MMC1_CD3, zylonite_detect_int, 0,
"MMC card detect slot 3", data);
if (err) {
printk(KERN_ERR
"MMC/SD: can't request MMC card detect"
"IRQ for slot 3\n");
return -1;
}
set_irq_type(MMC1_CD3, IRQT_BOTHEDGE);
}
#endif
return 0;
}
static int s5p_ehci_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct s5p_ehci_hcd *s5p_ehci = platform_get_drvdata(pdev);
struct usb_hcd *hcd = s5p_ehci->hcd;
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
clk_enable(s5p_ehci->clk);
pm_runtime_resume(&pdev->dev);
s5p_ehci_phy_init(pdev);
/* if EHCI was off, hcd was removed */
if (!s5p_ehci->power_on) {
dev_info(dev, "Nothing to do for the device (power off)\n");
return 0;
}
if (time_before(jiffies, ehci->next_statechange))
msleep(10);
/* Mark hardware accessible again as we are out of D3 state by now */
set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF) {
int mask = INTR_MASK;
if (!hcd->self.root_hub->do_remote_wakeup)
mask &= ~STS_PCD;
ehci_writel(ehci, mask, &ehci->regs->intr_enable);
ehci_readl(ehci, &ehci->regs->intr_enable);
return 0;
}
ehci_dbg(ehci, "lost power, restarting\n");
usb_root_hub_lost_power(hcd->self.root_hub);
(void) ehci_halt(ehci);
(void) ehci_reset(ehci);
/* emptying the schedule aborts any urbs */
spin_lock_irq(&ehci->lock);
if (ehci->reclaim)
end_unlink_async(ehci);
ehci_work(ehci);
spin_unlock_irq(&ehci->lock);
ehci_writel(ehci, ehci->command, &ehci->regs->command);
ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
/* here we "know" root ports should always stay powered */
ehci_port_power(ehci, 1);
hcd->state = HC_STATE_SUSPENDED;
#ifdef CONFIG_MDM_HSIC_PM
set_host_stat(hsic_pm_dev, POWER_ON);
wait_dev_pwr_stat(hsic_pm_dev, POWER_ON);
#endif
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB) \
|| defined(CONFIG_MDM_HSIC_PM)
s5p_wait_for_cp_resume(pdev, hcd);
#endif
return 0;
}
static ssize_t max197_show_name(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct platform_device *pdev = to_platform_device(dev);
return sprintf(buf, "%s\n", pdev->name);
}