s32 tv_exit(void)
{
s32 sel;
for(sel=0; sel <SCREEN_COUNT; sel++) {
tv_disable(sel);
tve_low_exit(sel);
}
return 0;
}
void tvout_set_cur_mode(u8 type)
{
lcd_set_backlight(0); //close backlight
tvout_lcd_disen();
REG32(PCON0) &= ~(1<<29); // enable LCD clock
REG32(PCON0) &= ~(1<<22); // enable TV clock
if(TVOUT_MODE_LCD == type)
{
DB("tvout is lcd \n");
tv_disable();
tvout_mode = TVOUT_MODE_LCD;
tvout_w = lcd_get_w();
tvout_h = lcd_get_h();
DB("tvout_w =%d,tvout_h = %d \n",tvout_w,tvout_h);
tvout_lcd_clk_cfg(); //init clk
REG32(LCDCON0) &= ~((1<<9)|(1 << 7)|(1 << 6) | (1 << 5) |(1 << 4)|(1 << 3)|(LCD_INTERFACE_SEL<<1)|(1<<0)); //disabled
lcd_set_panel_colour(0,0,0);
lcd_init();
// REG32(LCDCON0) |= (0 << 8)|(1 << 6) |(1 << 0); //video_en,osd3_en,osd2_en,osd1_en,lcd_en
//=======after set clk=====
tvout_lcd_disen();
waittingLcdFrameEnd();
set_video_address(VIDEO_BASE_SDRAM_ADDR);
tvout_display_set(0,0,u32csi_Dma_Size_H,u32csi_Dma_Size_H,u32csi_Dma_Size_V,tvout_get_w(),tvout_get_h());
waittingLcdFrameEnd();
tvout_lcd_en();
// REG32(LCDCON0) &= ~BIT(7); //write back disable
//lcd_set_backlight(1); //open backlight
}
else if(TVOUT_MODE_NTSC == type)
{
DB("tvout is ntsc \n");
tvout_mode = TVOUT_MODE_NTSC;
tvout_w = 720;
tvout_h = 480;
DB("tvout_w =%d,tvout_h = %d \n",tvout_w,tvout_h);
tvout_clk_cfg(); //tvout clk set
tvout_ntsc_reg_init(); //ntsc reg init
SetIntSrc(LCD_INT); //open lcd int
REG32(LCDCON0) |= 1<<10;
tvout_set_panel(tvout_get_w()-1,tvout_get_h()-1,0,0,250);
tvout_display_set(0,0,u32csi_Dma_Size_H,u32csi_Dma_Size_H,u32csi_Dma_Size_V,tvout_get_w(),tvout_get_h());
REG32(LCDCON47) = (0<<0)//warped distance enable
| (4<<1)//warped distance (4 recommended)
| (ROTATEMODE<<4)//rotate mode 0\1 disable\180
| (MIRRORMODE<<5)//mirror mode 0\1\2\3 disable\up_and_down\left_and_right\up_and_down_left_and_right
| (1<<8);
REG32(LCDCON0) |= (0<<0) //[0]: lcd enable
| (LCD_INTERFACE_SEL<<1) //[2:1]: TV out
| (DISPLAY_CHANNEL<<3)//[3:6]: osd1ãosd2ãosd3ãvideo enable
| (1<<9); //[9]: odd_and_even line first 0/1 even/odd
tvout_lcd_en();
tv_enable();
Delay_MS(100); // let tvout work steady
}
else
{
DB("tvout is pal \n");
tvout_mode = TVOUT_MODE_PAL;
if(0 == PAL_DEFINITION)
{
tvout_w = 720;
tvout_h = 576;
}
else
{
tvout_w = 702;
tvout_h = 576;
}
DB("tvout_w =%d,tvout_h = %d \n",tvout_w,tvout_h);
tvout_clk_cfg(); //tvout clk set
tvout_pal_reg_init(); //pal reg init
SetIntSrc(LCD_INT); //open lcd int
REG32(LCDCON0) |= 1<<10;
tvout_set_panel(tvout_get_w()-1,tvout_get_h()-1,0,0,250);
tvout_display_set(0,0,u32csi_Dma_Size_H,u32csi_Dma_Size_H,u32csi_Dma_Size_V,tvout_get_w(),tvout_get_h());
REG32(LCDCON47) = (0<<0)//warped distance enable
| (4<<1)//warped distance (4 recommended)
| (ROTATEMODE<<4)//rotate mode 0\1 disable\180
| (MIRRORMODE<<5)//mirror mode 0\1\2\3 disable\up_and_down\left_and_right\up_and_down_left_and_right
| (1<<8);
REG32(LCDCON0) |= (0<<0) //[0]: lcd enable
| (LCD_INTERFACE_SEL<<1) //[2:1]: TV out
| (DISPLAY_CHANNEL<<3)//[3:6]: osd1ãosd2ãosd3ãvideo enable
| (0<<9) //[9]: odd_and_even line first 0/1 even/odd
| (0<<10)//one frame display finish pending interrupt
| (0<<11)//write back 8line finish pending interrupt
| (0<<12);//video or osd buffer empty pending interrupt
REG32(LCDCON0) &= ~((1 << 9) ); //[9]: odd_and_even line first 0/1 even/odd
tvout_lcd_en();
tv_enable();
Delay_MS(100); // let tvout work steady
}
OSDInfInit();
// tvout_reg_printf();
}
