//__attribute__ ((section (".irq")))
//__attribute__ ((interrupt("IRQ")))
void isr(void)
{
uint32_t pending;
nirqpass = 0;
while ((pending = *NIPEND)) {
if(bit_is_set(pending, INT_NUM_TMR)) {
/* dispatch to individual timer isrs if they exist */
/* timer isrs are responsible for determining if they
* caused an interrupt */
/* and clearing their own interrupt flags */
if (tmr_isr_funcs[0] != 0) { (tmr_isr_funcs[0])(); }
if (tmr_isr_funcs[1] != 0) { (tmr_isr_funcs[1])(); }
if (tmr_isr_funcs[2] != 0) { (tmr_isr_funcs[2])(); }
if (tmr_isr_funcs[3] != 0) { (tmr_isr_funcs[3])(); }
}
if(bit_is_set(pending, INT_NUM_MACA)) {
if(maca_isr != 0) { maca_isr(); }
}
if(bit_is_set(pending, INT_NUM_UART1)) {
if (ttyInterrupt != 0) { ttyInterrupt(); }
}
if(bit_is_set(pending, INT_NUM_UART2)) {
if(uart2_isr != 0) { uart2_isr(); }
}
if(bit_is_set(pending, INT_NUM_CRM)) {
if(rtc_wu_evt() && (rtc_isr != 0)) { rtc_isr(); }
if(kbi_evnt(4) && (kbi4_isr != 0)) { kbi4_isr(); }
if(kbi_evnt(5) && (kbi5_isr != 0)) { kbi5_isr(); }
if(kbi_evnt(6) && (kbi6_isr != 0)) { kbi6_isr(); }
if(kbi_evnt(7) && (kbi7_isr != 0)) { kbi7_isr(); }
if (CRM->STATUSbits.CAL_DONE && CRM->CAL_CNTLbits.CAL_IEN && cal_isr)
{
CRM->STATUSbits.CAL_DONE = 0;
cal_isr();
}
}
if(bit_is_set(pending, INT_NUM_ASM)) {
if(asm_isr != 0) { asm_isr(); }
}
if (bit_is_set(pending, INT_NUM_I2C)) {
if (i2c_isr != 0) { i2c_isr(); }
}
*INTFRC = 0; /* stop forcing interrupts */
nirqpass++;
}
}
/**************************************************
* Function name : void high_isr(void)
*
* Created by : Luca Lucci
* Date created : 18/10/12
* Description : Managment for high priority interrupt
* Notes : -
**************************************************/
void high_isr(void)
{
if(INTCONbits.TMR0IF)
{
INTCONbits.TMR0IE = 0; //clear int flag
INTCONbits.TMR0IF = 0; //clear int flag
led_st1 = ~led_st1;
WriteTimer0(0xbdc);
INTCONbits.TMR0IE = 1; //clear int flag
}
if( INTCONbits.INT0IF )
{
/* Note: the interrupt latency will be three to four instruction cycles. The
* exact latency is the same for one or two-cycle instructions. Individual
* interrupt flag bits are set regardless of the status of their
* corresponding enable bit or the GIE bit.
* There is no priority bit associated with INT0; it always a high priority
* interrupt source */
INTCONbits.INT0IF = 0; // Required to reset in software before re-enable
}
can_isr();
uart_isr();
// used for debug interface
uart2_isr();
}
