void
main_task(void *arg)
{
while (1) {
uart_print((char *) arg);
uart_print("led 1\n");
if (get_led_1() == LED_ON)
set_led_1(LED_OFF);
else
set_led_1(LED_ON);
if (time == 10) {
uart_print("delete task 3\n");
while (delete_task_request(30) != -1) {
uart_print("waiting task 3 to delete\n");
sleep(1);
}
uart_print("task 3 not exist now\n");
}
++time;
/* Sleep 1 second */
sleep(1);
}
}
static void manageOldCompletePage() {
uart_print("manageOldCompletePage\r\n");
for (int chunkIdx=0; chunkIdx<CHUNKS_PER_PAGE; chunkIdx++){
uart_print("Chunk "); uart_print_int(chunkIdx); uart_print("\r\n");
manageOldChunkForCompletePageWrite(chunkIdx);
}
}
UINT32 getLpnForCompletePage(const UINT32 bank, LogCtrlBlock * ctrlBlock)
{
uart_print("getLpnForCompletePage bank "); uart_print_int(bank); uart_print("\r\n");
if (ctrlBlock[bank].useRecycledPage)
{
UINT32 pageOffset = LogPageToOffset(ctrlBlock[bank].logLpn);
if (pageOffset == 0)
{
#if PrintStats
uart_print_level_1("-\r\n");
#endif
decrementValidChunksByN(&heapDataSecondUsage, bank, LogPageToLogBlk(ctrlBlock[bank].logLpn), CHUNKS_PER_PAGE);
ctrlBlock[bank].logLpn = ctrlBlock[bank].logLpn + 2;
}
else
{
if (pageOffset % 2 == 1)
{
#if PrintStats
uart_print_level_1("-\r\n");
#endif
decrementValidChunksByN(&heapDataSecondUsage, bank, LogPageToLogBlk(ctrlBlock[bank].logLpn), CHUNKS_PER_PAGE);
ctrlBlock[bank].logLpn ++;
}
}
}
return ctrlBlock[bank].logLpn;
}
void flashtest(){
int i;
short *flash = (short*)FLASH_TEST_BASE;
short status;
uart_print("Try to write in Flash at the address ");
uart_printhex(flash);
uart_skipline();
uart_println("Unlock the block");
unlock_block(flash);
uart_println("Write memory");
for(i=0; i<FLASHTEST_SIZE; i++){
status = flash_write(FLASH_TEST_BASE+i*2, i+0x0);
uart_print("write status = ");
uart_printhex(status);
uart_skipline();
}
//flash_erase_block(flash);
uart_println("Try to dump memory, it should return the numbers from 0 to 9");
for(i=0; i<FLASHTEST_SIZE; i++){
uart_printhex(flash_read(flash++));
uart_skipline();
}
}
static void flushLogBufferDuringGC(const UINT32 bank)
{
uart_print("flushLogBufferDuringGC bank="); uart_print_int(bank); uart_print("\r\n");
UINT32 newLogLpn = getRWLpn(bank); // TODO: completely ignoring SW Log. Should use prepare_to_new_write if we want to use it
uart_print("FlushLog to lpn="); uart_print_int(newLogLpn); uart_print("\r\n");
UINT32 vBlk = get_log_vbn(bank, LogPageToLogBlk(newLogLpn));
UINT32 pageOffset = LogPageToOffset(newLogLpn);
nand_page_program(bank, vBlk, pageOffset, LOG_BUF(bank), RETURN_ON_ISSUE);
for(int i=0; i<CHUNKS_PER_PAGE; i++)
{
UINT32 lChunkAddr = (newLogLpn * CHUNKS_PER_PAGE) + i;
if( (chunkInLpnsList(RWCtrl[bank].lpnsListPtr, LogPageToOffset(newLogLpn), i)) >= (DRAM_BASE + DRAM_SIZE))
{
uart_print_level_1("ERROR in write::flushLogBufferDuringGC 1: writing to "); uart_print_level_1_int(chunkInLpnsList(RWCtrl[bank].lpnsListPtr, LogPageToOffset(newLogLpn), i)); uart_print_level_1("\r\n");
}
write_dram_32(chunkInLpnsList(RWCtrl[bank].lpnsListPtr, LogPageToOffset(newLogLpn), i), logBufMeta[bank].dataLpn[i]);
if (logBufMeta[bank].dataLpn[i] != INVALID)
{
write_dram_32(ChunksMapTable(logBufMeta[bank].dataLpn[i], logBufMeta[bank].chunkIdx[i]), (bank * LOG_BLK_PER_BANK * CHUNKS_PER_BLK) + lChunkAddr);
}
else
{
decrementValidChunks(&heapDataWrite, bank, LogPageToLogBlk(newLogLpn)); // decrement blk with previous copy
}
}
increaseRWLpn(bank);
}
void interrupt_nsptimer(int irq, void *pregs, void *pdata )
{
uint32_t ctl;
struct arch_regs *regs = pregs;
uart_print( "=======================================\n\r" );
HVMM_TRACE_ENTER();
/* Disable NS Physical Timer Interrupt */
ctl = read_cntp_ctl();
ctl &= ~(0x1);
write_cntp_ctl(ctl);
/* Trigger another interrupt */
test_start_timer();
/* Test guest context switch */
if ( (regs->cpsr & 0x1F) != 0x1A ) {
/* Not from Hyp, switch the guest context */
context_dump_regs( regs );
context_switchto(sched_policy_determ_next());
}
HVMM_TRACE_EXIT();
uart_print( "=======================================\n\r" );
}
/* NOTE: This function calls rebuildPageToFtlBuf with GcMode, therefore the valid chunks counters of old blocks are already managed.
* Do not call manageOldChunks before calling this!
*/
static void appendPageToSWBlock (const UINT32 dataLpn, const UINT32 sectOffset, const UINT32 nSects)
{
uart_print("appendPageToSWBlock dataLpn="); uart_print_int(dataLpn);
uart_print(", sectOffset="); uart_print_int(sectOffset);
uart_print(", nSects="); uart_print_int(nSects); uart_print("\r\n");
UINT32 nSectsToWrite = SECTORS_PER_PAGE - sectOffset;
UINT32 logLpn = getSWLpn(bank_);
UINT32 vBlk = get_log_vbn(bank_, LogPageToLogBlk(logLpn));
UINT32 dst = FTL_BUF(0) + (sectOffset*BYTES_PER_SECTOR);
UINT32 src = WR_BUF_PTR(g_ftl_write_buf_id)+(sectOffset*BYTES_PER_SECTOR);
rebuildPageToFtlBuf(dataLpn, 0, SECTORS_PER_PAGE, GcMode); // Rebuild rest of the page in FTL buffer (rebuild entire page to be sure that all chunks are correctly garbage collected, especially if they are in DRAM)
//waitBusyBank(bank_);
flash_finish();
mem_copy(dst, src, nSectsToWrite * BYTES_PER_SECTOR); // Fill FTL buffer with new data
//TODO: this program shouldn't be sincronous, need a global variable storing last bank writing data from FTL_BUF(0)
nand_page_program(bank_, vBlk, LogPageToOffset(logLpn), FTL_BUF(0), RETURN_WHEN_DONE); // Write FTL buffer to the next sequential page
UINT32 chunkIdx;
for(chunkIdx=0; chunkIdx<sectOffset / SECTORS_PER_CHUNK; ++chunkIdx)
{ // For sector before the start of new data we update only if previously there was some valid data, which is now in the new page, otherwise we insert invalid in the lpns list to speed up GC later
if (ChunksMapTable(dataLpn, chunkIdx) > DRAM_BASE + DRAM_SIZE)
{
uart_print_level_1("ERROR in appendPageToSWBlk 1: reading above DRAM address space\r\n");
}
if (read_dram_32(ChunksMapTable(dataLpn, chunkIdx)) != INVALID)
{
UINT32 lChunkAddr = (logLpn * CHUNKS_PER_PAGE) + chunkIdx;
if((chunkInLpnsList(SWCtrl[bank_].lpnsListPtr, LogPageToOffset(logLpn), chunkIdx)) >=(DRAM_BASE + DRAM_SIZE))
{
uart_print_level_1("ERROR in write::appendPageToSWBlk 1: writing to "); uart_print_level_1_int(chunkInLpnsList(SWCtrl[bank_].lpnsListPtr, LogPageToOffset(logLpn), chunkIdx)); uart_print_level_1("\r\n");
}
write_dram_32(chunkInLpnsList(SWCtrl[bank_].lpnsListPtr, LogPageToOffset(logLpn), chunkIdx), dataLpn);
write_dram_32(ChunksMapTable(dataLpn, chunkIdx), (bank_ * LOG_BLK_PER_BANK * CHUNKS_PER_BLK) + lChunkAddr);
}
else
{ //Decrement valid chunks in the blk we're going to write in because we inserted null data
if((chunkInLpnsList(SWCtrl[bank_].lpnsListPtr, LogPageToOffset(logLpn), chunkIdx)) >=(DRAM_BASE + DRAM_SIZE))
{
uart_print_level_1("ERROR in write::appendPageToSWBlk 2: writing to "); uart_print_level_1_int(chunkInLpnsList(SWCtrl[bank_].lpnsListPtr, LogPageToOffset(logLpn), chunkIdx)); uart_print_level_1("\r\n");
}
write_dram_32(chunkInLpnsList(SWCtrl[bank_].lpnsListPtr, LogPageToOffset(logLpn), chunkIdx), INVALID);
decrementValidChunks(&heapDataWrite, bank_, LogPageToLogBlk(logLpn));
}
}
for( ; chunkIdx < CHUNKS_PER_PAGE; ++chunkIdx)
{ // The new sectors are instead all valid, therefore we don't bother checking if they were valid before
UINT32 lChunkAddr = (logLpn * CHUNKS_PER_PAGE) + chunkIdx;
if((chunkInLpnsList(SWCtrl[bank_].lpnsListPtr, LogPageToOffset(logLpn), chunkIdx)) >=(DRAM_BASE + DRAM_SIZE))
{
uart_print_level_1("ERROR in write::appendPageToSWBlk 3: writing to "); uart_print_level_1_int(chunkInLpnsList(SWCtrl[bank_].lpnsListPtr, LogPageToOffset(logLpn), chunkIdx)); uart_print_level_1("\r\n");
}
write_dram_32(chunkInLpnsList(SWCtrl[bank_].lpnsListPtr, LogPageToOffset(logLpn), chunkIdx), dataLpn);
write_dram_32(ChunksMapTable(dataLpn, chunkIdx), (bank_ * LOG_BLK_PER_BANK * CHUNKS_PER_BLK) + lChunkAddr);
}
SWCtrl[bank_].nextDataLpn=dataLpn+1;
increaseSWLpn(bank_);
g_ftl_write_buf_id = (g_ftl_write_buf_id + 1) % NUM_WR_BUFFERS;
SETREG (BM_STACK_WRSET, g_ftl_write_buf_id);
SETREG (BM_STACK_RESET, 0x01);
}
static void updateChunkPtr()
{
uart_print("updateChunkPtr\r\n");
chunkPtr[bank_] = (chunkPtr[bank_] + 1) % CHUNKS_PER_PAGE;
uart_print("new chunkPtr for bank "); uart_print_int(bank_); uart_print(" is "); uart_print_int(chunkPtr[bank_]); uart_print("\r\n");
if (chunkPtr[bank_] == 0)
flushLogBuffer();
}
static void updateChunkPtrDuringGC(const UINT32 bank)
{
uart_print("updateChunkPtrDuringGC\r\n");
chunkPtr[bank] = (chunkPtr[bank] + 1) % CHUNKS_PER_PAGE;
uart_print("new chunkPtr for bank "); uart_print_int(bank); uart_print(" is "); uart_print_int(chunkPtr[bank]); uart_print("\r\n");
if (chunkPtr[bank] == 0)
flushLogBufferDuringGC(bank);
}
// set log vbn to log block mapping table
void set_log_vbn (UINT32 const bank, UINT32 const log_lbn, UINT32 const vblock)
{
uart_print("set_log_vbn(bank="); uart_print_int(bank);
uart_print(", log_lbn="); uart_print_int(log_lbn);
uart_print(", vblock="); uart_print_int(vblock);
uart_print(")\r\n");
Write_log_bmt(bank, log_lbn, vblock);
//write_dram_16 (LOG_BMT_ADDR + ((bank * LOG_BLK_PER_BANK + log_lbn) * sizeof (UINT16)), vblock);
}
void interrupt_pwmtimer(void *pdata)
{
pwm_timer_disable_int();
uart_print("=======================================\n\r");
HVMM_TRACE_ENTER();
HVMM_TRACE_EXIT();
uart_print("=======================================\n\r");
pwm_timer_enable_int();
}
void DataSink::on_uartOpenClose_clicked(void)
{
if (uart->isOpen()) {
uart->close();
ui->uartOpenClose->setText(tr("Open"));
ui->uartSend->setEnabled(false);
ui->uartStatus->setText(tr("Closed"));
} else {
if (ui->uartDevice->count() < 1) {
uart_print(tr("Unable to open UART, no port present."));
return;
}
QString port = ui->uartDevice->itemText(ui->uartDevice->currentIndex());
uart->setPortName(port);
switch(ui->uartBaudrate->currentIndex())
{
case 0:
uart->setBaudRate(BAUD300);
break;
case 1:
uart->setBaudRate(BAUD600);
break;
case 2:
uart->setBaudRate(BAUD1200);
break;
case 3:
uart->setBaudRate(BAUD2400);
break;
case 4:
uart->setBaudRate(BAUD4800);
break;
case 5:
uart->setBaudRate(BAUD9600);
break;
case 6:
uart->setBaudRate(BAUD19200);
break;
case 7:
uart->setBaudRate(BAUD38400);
break;
case 8:
uart->setBaudRate(BAUD57600);
break;
case 9:
uart->setBaudRate(BAUD115200);
break;
}
if (uart->open(QIODevice::ReadWrite)) {
ui->uartOpenClose->setText(tr("Close"));
ui->uartSend->setEnabled(true);
ui->uartStatus->setText(uart->portName() + " " + tr("open"));
} else {
uart_print("Unable to open uart port: " + uart->portName());
}
}
}
static void updateOwChunkPtr()
{
uart_print("updateOwChunkPtr\r\n");
owChunkPtr[bank_] = (owChunkPtr[bank_] + 1) % CHUNKS_PER_PAGE;
uart_print("new owChunkPtr for bank "); uart_print_int(bank_); uart_print(" is "); uart_print_int(owChunkPtr[bank_]); uart_print("\r\n");
if (owChunkPtr[bank_] == 0)
{
flushOwLogBuffer();
}
}
/* } */
void ftl_test(void)
{
uart_print("start ftl test...");
/* fillup_dataspace(); */
//tc_write_seq(0, 500000, NUM_PSECTORS_64KB);
tc_write_rand(0, 200000, NUM_PSECTORS_16KB);
//tc_write_rand(0, 200000, NUM_PSECTORS_4KB);
/* tc_write_rand(0, 2000000, NUM_PSECTORS_4KB); */
uart_print("ftl test passed!");
}
static UINT8 readOwCounter(UINT32 bank, UINT32 lbn, UINT32 pageOffset)
{
UINT32 page = pageOffset == 0 ? 0 : (pageOffset+1)/2;
UINT8 counter = read_dram_8(OwCounter(bank, lbn, page));
uart_print("readOwCounter bank="); uart_print_int(bank);
uart_print(" lbn="); uart_print_int(lbn);
uart_print(" pageOffset="); uart_print_int(pageOffset);
uart_print(" => counter="); uart_print_int(counter); uart_print("\r\n");
return counter;
}
static void increaseOwCounter(UINT32 bank, UINT32 lbn, UINT32 pageOffset)
{
UINT32 page = pageOffset == 0 ? 0 : (pageOffset+1)/2;
UINT8 counter = read_dram_8(OwCounter(bank, lbn, page));
counter = counter + 1;
uart_print("increaseOwCounter bank="); uart_print_int(bank);
uart_print(" lbn="); uart_print_int(lbn);
uart_print(" pageOffset="); uart_print_int(pageOffset);
uart_print(" => new counter="); uart_print_int(counter); uart_print("\r\n");
write_dram_8(OwCounter(bank, lbn, page), counter);
}
void EVENT_USB_Device_ControlRequest(void){
void* buffer = NULL;
uint16_t length = 0;
if(change != NULL) {
usb_set_device(change, 1);
Endpoint_ClearSETUP();
Endpoint_ClearIN();
Endpoint_ClearOUT();
} else {
Endpoint_ClearSETUP();
}
uart_print("Type: %x, req: %x, val: %x, idx: %x, len: %d\n",
USB_ControlRequest.bmRequestType,
USB_ControlRequest.bRequest,
USB_ControlRequest.wValue,
USB_ControlRequest.wIndex,
USB_ControlRequest.wLength);
device->handle_configuration( device,
USB_ControlRequest.bmRequestType,
USB_ControlRequest.bRequest,
USB_ControlRequest.wValue,
USB_ControlRequest.wIndex,
USB_ControlRequest.wLength,
&buffer,
&length);
if(buffer) {
if(length == 0xFFFF) {
return;
}
if(length) {
if(length & CONST_PTR) {
Endpoint_Write_Control_PStream_LE(buffer, length & ~CONST_PTR);
} else {
Endpoint_Write_Control_Stream_LE(buffer, length);
}
}
Endpoint_ClearStatusStage();
if(deferred_addr >= 0) {
_usb_set_addr(deferred_addr);
uart_print("Setting addr to %d\n", deferred_addr);
deferred_addr = -1;
}
} else {
Endpoint_StallTransaction();
uart_print("STALLED!\n");
}
}
void printValidChunksInFirstUsageBlk(const UINT32 bank, const LogCtrlBlock * ctrlBlock, const UINT32 lbn)
{
UINT32 validChunks[9] = {0,0,0,0,0,0,0,0,0};
for(UINT32 pageOffset=0; pageOffset < 125; )
{
uart_print("readPage: bank="); uart_print_int(bank); uart_print(" ");
uart_print("pageOffset="); uart_print_int(pageOffset);
UINT32 nValidChunksInPage=0;
UINT32 victimLpns[CHUNKS_PER_PAGE];
mem_copy(victimLpns, ctrlBlock[bank].lpnsListAddr+(pageOffset*CHUNKS_PER_PAGE)*CHUNK_ADDR_BYTES, CHUNKS_PER_PAGE * sizeof(UINT32));
UINT32 logChunkAddr = (bank*LOG_BLK_PER_BANK*CHUNKS_PER_BLK) + (lbn*CHUNKS_PER_BLK) + (pageOffset*CHUNKS_PER_PAGE);
for(UINT32 chunkOffset=0; chunkOffset<CHUNKS_PER_PAGE; chunkOffset++)
{ // This loops finds valid chunks is the page. Note that chunks in GC Buf won't be considered as they temporarily don't occupy space in Log
UINT32 victimLpn = victimLpns[chunkOffset];
if (victimLpn != INVALID)
{
UINT32 i = mem_search_equ_dram_4_bytes(ChunksMapTable(victimLpn, 0), CHUNKS_PER_PAGE, logChunkAddr);
if(i<CHUNKS_PER_PAGE)
{
nValidChunksInPage++;
}
}
logChunkAddr++;
}
validChunks[nValidChunksInPage]++;
if (pageOffset == 0)
{
pageOffset++;
}
else
{
pageOffset += 2;
}
}
#if PrintStats
uart_print_level_1("REUSE ");
for(UINT32 i=0; i<9; ++i)
{
uart_print_level_1_int(validChunks[i]);
uart_print_level_1(" ");
}
uart_print_level_1("\r\n");
#endif
}
void nand_page_read_to_host(UINT32 const bank, UINT32 const vblock, UINT32 const page_num)
{
#if PrintStats
uart_print_level_1("FR ");
uart_print_level_1_int(SECTORS_PER_PAGE);
uart_print_level_1("\r\n");
#endif
UINT32 row;
ASSERT(bank < NUM_BANKS);
ASSERT(vblock < VBLKS_PER_BANK);
ASSERT(page_num < PAGES_PER_BLK);
row = (vblock * PAGES_PER_BLK) + page_num;
uart_print("nand_page_read_to_host bank="); uart_print_int(bank);
uart_print(", vblock="); uart_print_int(vblock);
uart_print(", page="); uart_print_int(page_num); uart_print("\r\n");
uart_print("Reading row="); uart_print_int(row); uart_print("\r\n");
uart_print("read flash: bank="); uart_print_int(bank);
uart_print(", page="); uart_print_int(row); uart_print("\r\n");
SETREG(FCP_CMD, FC_COL_ROW_READ_OUT);
SETREG(FCP_DMA_ADDR, RD_BUF_PTR(g_ftl_read_buf_id));
SETREG(FCP_DMA_CNT, BYTES_PER_PAGE);
SETREG(FCP_COL, 0);
#if OPTION_FTL_TEST == TRUE
SETREG(FCP_OPTION, FO_P | FO_E);
#else
SETREG(FCP_OPTION, FO_P | FO_E | FO_B_SATA_R);
#endif
SETREG(FCP_ROW_L(bank), row);
SETREG(FCP_ROW_H(bank), row);
g_ftl_read_buf_id = (g_ftl_read_buf_id + 1) % NUM_RD_BUFFERS;
#if OPTION_FTL_TEST == FALSE
{
int count=0;
while (1) {
count ++;
if (count > 100000) {
uart_print_level_1("Warning1 in nand_page_read_to_host\r\n");
count=0;
}
UINT32 sata_id = GETREG(SATA_RBUF_PTR);
if (g_ftl_read_buf_id != sata_id)
break;
}
}
#endif
flash_issue_cmd(bank, RETURN_ON_ISSUE);
}
void
third_task(void *arg)
{
while (1) {
if (delete_task_request(30) == OS_TASK_DEL_REQ) {
uart_print("[3]: I am going to delete myself\n");
sleep(5);
uart_print("[3]: I had deleted myself\n");
delete_task(30);
}
uart_print("3\n");
sleep(1);
}
}
UINT8 writeChunkOnLogBlockDuringGC(const UINT32 dataLpn, const UINT32 dataChunkOffset, const UINT32 chunkOffsetInBuf, const UINT32 bufAddr)
{
/* Need this function because during GC can't use the global variables, because those might be related to an outstanding write (which triggered the GC) */
UINT32 bank = chooseNewBank();
uart_print("writeChunkOnLogBlockDuringGC, bank="); uart_print_int(bank); uart_print(" dataLpn="); uart_print_int(dataLpn);
uart_print(", dataChunkOffset="); uart_print_int(dataChunkOffset); uart_print("\r\n");
int sectOffset = dataChunkOffset * SECTORS_PER_CHUNK;
UINT32 src = bufAddr + (chunkOffsetInBuf * BYTES_PER_CHUNK);
UINT32 dst = LOG_BUF(bank) + (chunkPtr[bank] * BYTES_PER_CHUNK); // base address of the destination chunk
waitBusyBank(bank);
mem_copy(dst, src, BYTES_PER_CHUNK);
updateDramBufMetadataDuringGc(bank, dataLpn, sectOffset);
updateChunkPtrDuringGC(bank);
return 0;
}
void
second_task(void *arg)
{
while (1) {
uart_print((char *) arg);
uart_print(" led 2\n");
if (get_led_2() == LED_ON)
set_led_2(LED_OFF);
else
set_led_2(LED_ON);
/* Sleep 1 second */
sleep(1);
}
}
void nand_block_erase_sync(UINT32 const bank, UINT32 const vblock)
{
uart_print("nand_block_erase_sync(bank="); uart_print_int(bank);
uart_print(", vblock="); uart_print_int(vblock); uart_print(")\r\n");
ASSERT(bank < NUM_BANKS);
ASSERT(vblock < VBLKS_PER_BANK);
SETREG(FCP_CMD, FC_ERASE);
SETREG(FCP_BANK, REAL_BANK(bank));
SETREG(FCP_OPTION, FO_P); // if OPTION_2_PLANE == 0, FO_P will be zero.
SETREG(FCP_ROW_H(bank), vblock * PAGES_PER_VBLK);
SETREG(FCP_ROW_L(bank), vblock * PAGES_PER_VBLK);
flash_issue_cmd(bank, RETURN_WHEN_DONE);
}
void writeToLogBlk (UINT32 const dataLpn, UINT32 const sectOffset, UINT32 const nSects)
{
//uart_print_level_1("2 ");
uart_print("writeToLogBlk dataLpn="); uart_print_int(dataLpn);
uart_print(", sect_offset="); uart_print_int(sectOffset);
uart_print(", num_sectors="); uart_print_int(nSects); uart_print("\r\n");
if ( sectOffset + nSects == SECTORS_PER_PAGE )
{
for (UINT32 bank=0; bank < NUM_BANKS; ++bank)
{
if(SWCtrl[bank].nextDataLpn == dataLpn)
{
uart_print("Found stripe continuation on bank "); uart_print_int(bank); uart_print("\r\n");
bank_ = bank;
appendPageToSWBlock (dataLpn, sectOffset, nSects);
return;
}
}
}
bank_ = chooseNewBank();
initWrite(dataLpn, sectOffset, nSects);
//if (!isNewWrite_)
//{
if (nSects_ != SECTORS_PER_PAGE)
{
//manageOldPartialPage();
syncWithWriteLimit();
writePartialPageOld();
}
else
{ // writing entire page, so write directly to
manageOldCompletePage();
writeCompletePage();
}
//}
//else
//{
//if (nSects_ != SECTORS_PER_PAGE)
//{
//syncWithWriteLimit();
//writePartialPageNew();
//}
//else
//{ // writing entire page, so write directly to
//writeCompletePage();
//}
//}
}
void ADT_wake()
{
uint8_t i;
//power on sensors
for(i=0;i<ADT_sensor_count;i++)
{
#ifdef debug
uart_print("ADT wake:");
uart_num(i,1);
uart_nl();
#endif
if(bit_get(ADT_status,BIT(i)))
{
#ifdef debug
uart_println("SKIP");
#endif
continue;//jump to next sensor, this one is broken
}
i2c_start(ADT_addr_base|i,I2C_WRITE);
i2c_write(0x03);//config reg
i2c_write(0b10000000);
i2c_stop();
}
}
static void handle_timestamp_overflow()
{
uart_print("warning: pmt cache timestamp overflowed!");
/* reassign timestamp by order */
UINT32 timestamp_low_bound;
UINT32 min_timestamp;
/* update the timestamp of potentially all page */
for (UINT32 i = 0; i < NUM_PC_SUB_PAGES; i++) {
timestamp_low_bound = i;
min_timestamp = NULL_TIMESTAMP;
/* find the i-th minimum timestamp */
for (UINT32 j = 0; j < NUM_PC_SUB_PAGES; j++) {
UINT32 j_timestamp = cached_pmt_timestamps[j];
if (j_timestamp < timestamp_low_bound) continue;
if (j_timestamp >= min_timestamp) continue;
min_timestamp = j_timestamp;
}
if (min_timestamp == NULL_TIMESTAMP) break;
if (min_timestamp == timestamp_low_bound) continue;
/* i-th minimum timestamp is set to i */
for (UINT32 k = 0; k < NUM_PC_SUB_PAGES; k++)
if (cached_pmt_timestamps[k] == min_timestamp)
cached_pmt_timestamps[k] = timestamp_low_bound;
}
/* count timestamp from minnimal */
current_timestamp = ++timestamp_low_bound;
}
void readFromLogBlk (UINT32 const dataLpn, UINT32 const sectOffset, UINT32 const nSects){
uart_print("readFromLogBlk dataLpn="); uart_print_int(dataLpn);
uart_print(", sect_offset="); uart_print_int(sectOffset);
uart_print(", num_sectors="); uart_print_int(nSects); uart_print("\r\n");
UINT32 dst = RD_BUF_PTR(g_ftl_read_buf_id)+(sectOffset*BYTES_PER_SECTOR);
UINT32 src = FTL_BUF(0)+(sectOffset*BYTES_PER_SECTOR);
rebuildPageToFtlBuf(dataLpn, sectOffset, nSects, ReadMode);
mem_copy(dst, src, nSects*BYTES_PER_SECTOR);
g_ftl_read_buf_id = (g_ftl_read_buf_id + 1) % NUM_RD_BUFFERS;
SETREG (BM_STACK_RDSET, g_ftl_read_buf_id); // change bm_read_limit
SETREG (BM_STACK_RESET, 0x02); // change bm_read_limit
//UINT32 bank = choose new bank
//int bankToGarbageCollect = (bank + NUM_BANKS - 1) % NUM_BANKS;
//callPM(bankToGarbageCollect);
}
void ADT_shutdown()
{
uint8_t i;
//shutdown
for(i=0;i<ADT_sensor_count;i++)
{
#ifdef debug
uart_print("ADT shutdown:");
uart_num(i,1);
uart_nl();
#endif
if(bit_get(ADT_status,BIT(i)))
{
#ifdef debug
uart_println("SKIP");
#endif
continue;
}
i2c_start(ADT_addr_base|i,I2C_WRITE);
i2c_write(0x03);//config reg
i2c_write(0b11100000);//7: 16bit res, 6~5: shutdown mode
i2c_stop();
}
#ifdef debug
uart_println("ADTs off");
#endif
}
static void readCompletePage(UINT32 *chunksInPage, UINT32 *srcChunkByteOffsets, UINT32 *chunkIdxs, UINT8 *decreaseInOW)
{
uart_print("readCompletePage\r\n");
UINT32 oldLogBank = ChunkToBank(oldChunkAddr_);
UINT32 oldLogVbn = get_log_vbn(oldLogBank, ChunkToLbn(oldChunkAddr_));
UINT32 oldLogPageOffset = ChunkToPageOffset(oldChunkAddr_);
nand_page_ptread(oldLogBank, oldLogVbn, oldLogPageOffset, 0, SECTORS_PER_PAGE, TEMP_BUF_ADDR, RETURN_WHEN_DONE);
for (int i=0; i<*chunksInPage; i++)
{
UINT32 src = TEMP_BUF_ADDR + srcChunkByteOffsets[i];
UINT32 dst = FTL_BUF(0) + chunkIdxs[i] * BYTES_PER_CHUNK;
mem_copy(dst, src, BYTES_PER_CHUNK);
chunksDone_[chunkIdxs[i]]=1;
if(mode_ == GcMode)
{
#if Overwrite
if (decreaseInOW[i])
{
decrementValidChunks(&heapDataOverwrite, oldLogBank, ChunkToLbn(oldChunkAddr_));
}
else
#endif
{
decrementValidChunks(&heapDataWrite, oldLogBank, ChunkToLbn(oldChunkAddr_));
}
}
}
}
void scheduler_test_switch_to_next_guest(void *pdata){
struct arch_regs *regs = pdata;
uint64_t pct = read_cntpct();
uint32_t tval = read_cnthp_tval();
uart_print( "cntpct:"); uart_print_hex64(pct); uart_print("\n\r");
uart_print( "cnth_tval:"); uart_print_hex32(tval); uart_print("\n\r");
/* Note: As of context_switchto() and context_perform_switch() are available,
no need to test if trapped from Hyp mode.
context_perform_switch() takes care of it
*/
/* Test guest context switch */
if ( (regs->cpsr & 0x1F) != 0x1A ) {
scheduler_schedule();
}
}
