static UCS_CLASS_INIT_FUNC(uct_rc_mlx5_ep_t, uct_iface_h tl_iface)
{
uct_rc_mlx5_iface_t *iface = ucs_derived_of(tl_iface, uct_rc_mlx5_iface_t);
ucs_status_t status;
UCS_CLASS_CALL_SUPER_INIT(uct_rc_ep_t, &iface->super);
status = uct_ib_mlx5_get_txwq(iface->super.super.super.worker, self->super.qp,
&self->tx.wq);
if (status != UCS_OK) {
ucs_error("Failed to get mlx5 QP information");
return status;
}
self->super.available = self->tx.wq.bb_max;
self->qp_num = self->super.qp->qp_num;
return UCS_OK;
}
static ucs_status_t uct_dc_mlx5_iface_init_dcis(uct_dc_mlx5_iface_t *iface)
{
ucs_status_t status;
uint16_t bb_max;
int i;
bb_max = 0;
for (i = 0; i < iface->super.tx.ndci; i++) {
status = uct_ib_mlx5_get_txwq(iface->super.super.super.super.worker,
iface->super.tx.dcis[i].txqp.qp,
&iface->dci_wqs[i]);
if (status != UCS_OK) {
return status;
}
bb_max = iface->dci_wqs[i].bb_max;
uct_rc_txqp_available_set(&iface->super.tx.dcis[i].txqp, bb_max);
}
iface->super.super.config.tx_qp_len = bb_max;
return UCS_OK;
}
static UCS_CLASS_INIT_FUNC(uct_ud_mlx5_iface_t,
uct_pd_h pd, uct_worker_h worker,
const char *dev_name, size_t rx_headroom,
const uct_iface_config_t *tl_config)
{
uct_ud_iface_config_t *config = ucs_derived_of(tl_config,
uct_ud_iface_config_t);
ucs_status_t status;
int i;
ucs_trace_func("");
UCS_CLASS_CALL_SUPER_INIT(uct_ud_iface_t, &uct_ud_mlx5_iface_ops,
pd, worker,
dev_name, rx_headroom, 0, config);
self->super.ops.async_progress = uct_ud_mlx5_iface_async_progress;
self->super.ops.tx_skb = uct_ud_mlx5_ep_tx_ctl_skb;
status = uct_ib_mlx5_get_cq(self->super.super.send_cq, &self->tx.cq);
if (status != UCS_OK) {
return status;
}
if (uct_ib_mlx5_cqe_size(&self->tx.cq) != sizeof(struct mlx5_cqe64)) {
ucs_error("TX CQE size (%d) is not %d",
uct_ib_mlx5_cqe_size(&self->tx.cq),
(int)sizeof(struct mlx5_cqe64));
return UCS_ERR_IO_ERROR;
}
status = uct_ib_mlx5_get_cq(self->super.super.recv_cq, &self->rx.cq);
if (status != UCS_OK) {
return UCS_ERR_IO_ERROR;
}
if (uct_ib_mlx5_cqe_size(&self->rx.cq) != sizeof(struct mlx5_cqe64)) {
ucs_error("RX CQE size (%d) is not %d",
uct_ib_mlx5_cqe_size(&self->rx.cq),
(int)sizeof(struct mlx5_cqe64));
return UCS_ERR_IO_ERROR;
}
status = uct_ib_mlx5_get_txwq(self->super.super.super.worker, self->super.qp,
&self->tx.wq);
if (status != UCS_OK) {
return UCS_ERR_IO_ERROR;
}
self->super.tx.available = self->tx.wq.bb_max;
status = uct_ib_mlx5_get_rxwq(self->super.qp, &self->rx.wq);
if (status != UCS_OK) {
return UCS_ERR_IO_ERROR;
}
/* write buffer sizes */
for (i = 0; i <= self->rx.wq.mask; i++) {
self->rx.wq.wqes[i].byte_count = htonl(self->super.super.config.rx_payload_offset +
self->super.super.config.seg_size);
}
while (self->super.rx.available >= self->super.config.rx_max_batch) {
uct_ud_mlx5_iface_post_recv(self);
}
/* TODO: add progress on first ep creation */
uct_worker_progress_register(worker, uct_ud_mlx5_iface_progress, self);
uct_ud_leave(&self->super);
return UCS_OK;
}
