void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
sched_process_timer();
#else
up_idlepm();
/* SW-425 */
if (tsb_get_rev_id() > tsb_rev_es2) {
asm("wfi");
} else {
/* We theorize that instruction fetch on the bridge silicon may stall an
* in-progress USB DMA transfer. The ideal solution is to halt the processor
* during idle via WFI (wait for interrupt), but that degrades the JTAG
* debugging experience (see discussion below).
*
* For es2 builds, we'll try a work-around suggested by Olin Siebert, namely
* to execute a sequence of 16-bit nop instructions. The theory is that the CM3
* core will fetch two 16-bit instructions at a time, but execute them
* sequentially, dropping instruction fetch bandwidth by 50% during idle
* periods, and offering USB DMA transfers the opportunity to progress and
* complete.
*/
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
}
#endif
}
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
sched_process_timer();
#else
/* Perform IDLE mode power management */
BEGIN_IDLE();
up_idlepm();
END_IDLE();
#endif
}
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
sched_process_timer();
#else
/* Perform IDLE mode power management */
up_idlepm();
/* Sleep until an interrupt occurs to save power.
*
* NOTE: There is an STM32F107 errata that is fixed by the following
* workaround:
*
* "2.17.11 Ethernet DMA not working after WFI/WFE instruction
* Description
* If a WFI/WFE instruction is executed to put the system in sleep mode
* while the Ethernet MAC master clock on the AHB bus matrix is ON and all
* remaining masters clocks are OFF, the Ethernet DMA will be not able to
* perform any AHB master accesses during sleep mode."
*
* Workaround
* Enable DMA1 or DMA2 clocks in the RCC_AHBENR register before
* executing the WFI/WFE instruction."
*
* Here the workaround is just to avoid SLEEP mode for the connectivity
* line parts if Ethernet is enabled. The errate recommends a more
* general solution: Enabling DMA1/2 clocking in stm32f10xx_rcc.c if the
* STM32107 Ethernet peripheral is enabled.
*/
#if !defined(CONFIG_STM32_CONNECTIVITYLINE) || !defined(CONFIG_STM32_ETHMAC)
#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG))
BEGIN_IDLE();
asm("WFI");
END_IDLE();
#endif
#endif
#endif
}
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
sched_process_timer();
#else
/* Perform IDLE mode power management */
up_idlepm();
/* Sleep until an interrupt occurs to save power. */
#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG))
BEGIN_IDLE();
asm("WFI");
END_IDLE();
#endif
#endif
}
