static void Delayms(kal_uint32 data)
{
while(data--)
{
ust_busy_wait(1000);
}
}
/*************************************************************************
* FUNCTION
* mdci_read_and_wait
*
* DESCRIPTION
* This function reads data through either mailbox channel or stream
* channel. ONLY USED WHEN NO INTERRUPT
*
* PARAMETERS
* channel - logical channel
* buff - pointer to channel buffer
*
* RETURNS
* MDIF error code.
*
*************************************************************************/
kal_uint32 mdci_read_and_wait(MDCI_CHANNEL_T channel, MDCI_BUFF_T *buff, kal_uint32 ticks)
{
MDCI_RETURNVAL_T ret;
MDCI_BUFF_T *chdata;
kal_uint32 index, cur_phych;
volatile kal_uint32 reserved_value=0;
volatile kal_uint32 chk_channel=0;
/* query if used in init stage or exception */
if (KAL_TRUE != kal_query_systemInit() && KAL_TRUE != INT_QueryExceptionStatus())
{
return MDCI_API_INVALID;
}
/* check parameters */
if (channel >= MDCI_MAX_CHANNEL)
return MDCI_INVALID_PARAM;
if (buff == NULL)
return MDCI_INVALID_PARAM;
/* check state */
ret = MDCI_NOT_RECEIVE;
while (ticks > 0)
{
for (index = mdci_readindx_for_MD; index < mdci_readindx_for_MD + MDIF_MAX_PHY; index++)
{
cur_phych = index % MDIF_MAX_PHY;
chdata = (MDCI_BUFF_T *)MDIF_RXCHDATA + cur_phych;
reserved_value = *(volatile kal_uint32 *)(&(chdata->reserved));
chk_channel = *(volatile kal_uint32 *)(&(chdata->channel));
if (reserved_value == MDCI_EXCEPTION_CHECK_ID && chk_channel == channel)
{
kal_mem_cpy(buff, chdata, sizeof(MDCI_BUFF_T));
mdci_readindx_for_MD = cur_phych;
*(volatile kal_uint32*)(&(chdata->reserved)) = 0;
return MDCI_SUCCESS;
}
}
ust_busy_wait(1);
ticks--;
}
return ret;
}
/*
* FUNCTION
* adc_pwrdown_disable
*
* DESCRIPTION
* This function is to disable adc power down control
*
* CALLS
*
* PARAMETERS
* None
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* Note that this function must be called between SaveAndSetIRQMask()
* and RestoreIRQMask().
*/
void adc_pwrdown_disable(void)
{
#ifndef DRV_ADC_NOT_EXIST
#if defined(__OLD_PDN_ARCH__)
#ifdef ADC_DRVPDN_FAST
DRVPDN_DISABLE2(ADC_CG_PDN_CON_ADDR,ADC_CG_PDN_CON_BIT,PDN_ADC);
#else /*ADC_DRVPDN_FAST*/
DRVPDN_Disable(ADC_CG_PDN_CON_ADDR,ADC_CG_PDN_CON_BIT,PDN_ADC);
#endif /*ADC_DRVPDN_FAST*/
#else // #if defined(__OLD_PDN_ARCH__)
#ifdef ADC_DRVPDN_FAST
DRVPDN_DISABLE2(PDN_ADC);
#else /*ADC_DRVPDN_FAST*/
#if !defined(__DRV_SUPPORT_LPWR__)
PDN_CLR(PDN_ADC);
L1SM_SleepDisable(ADCSM_handler);
#else
DRVPDN_Disable(PDN_ADC);
#endif //#if !defined(__DRV_SUPPORT_LPWR__)
#endif /*ADC_DRVPDN_FAST*/
#endif // #if defined(__OLD_PDN_ARCH__)
#if defined(DRV_DIE_TO_DIE_INTERFACE)
{
kal_uint32 mask;
mask = SaveAndSetIRQMask();
auxadc_die2die_enable = KAL_TRUE;
PDN_CLR(PDN_ADC); // TP use the AuxADC PDN, make sure the PDN is disable
DRV_ADC_SetBits(ABB_WR_PATH0, F26M_CLK_EN); //enable clock for die to die interface, MT6250E1
//DRV_ADC_SetBits(ABB_RSV_CON1, AUXADC_FSM_CTRL|AUXADC_26M_CLK_CTRL); //enable clock for die to die interface, MT6250E2
DRV_ADC_SetBits(ABB_RSV_CON1, AUXADC_26M_CLK_CTRL); //enable clock for die to die interface, MT6250E2
ust_busy_wait(2);
DRV_ADC_SetBits(ABB_RSV_CON1, AUXADC_FSM_CTRL); //enable clock for die to die interface, MT6250E2
DRV_ADC_SetBits(0xa0160020,0x8000);
DRV_ADC_SetBits(ABBA_WR_PATH0, ABBA_AUX_PWDB); // enable clock for auxadc analog interface logic
DRV_ADC_SetBits(ABB_WR_PATH0, AUX_PWDB); //triggle die to die interface to send and receive auxadc data
ust_busy_wait(8);
DRV_ADC_SetBits(ABB_AUX_CON0, AUX_FIFO_CLK_EN); // auxadc fifo enable
DRV_ADC_SetBits(ABB_AUX_CON0, AUX_FIFO_EN); // auxadc fifo enable
RestoreIRQMask(mask);
}
#elif defined(DRV_DIE_TO_DIE_INTERFACE_V2)
{
DRV_ADC_SetBits(D2D_D_APC_AUX_CON1, D2D_D_F26M_AUX_EN);
DRV_ADC_SetBits(D2D_A_APC_AUD_CON1, D2D_A_AUX_EN);
DRV_ADC_Reg(D2D_A_APC_AUD_CON1);
DRV_ADC_SetBits(D2D_D_APC_AUX_CON1, D2D_D_AUX_EN|D2D_D_F26M_AUX_EN);
}
#endif
#endif // #ifndef DRV_ADC_NOT_EXIST
}
/*************************************************************************
* FUNCTION
* ds_mdci_write_and_wait
*
* DESCRIPTION
* This function writes data through either mailbox channel or stream
* channel. ONLY USED WHEN NO INTERRUPT
*
* PARAMETERS
* channel - logical channel
* buff - pointer to channel buffer
*
* RETURNS
* MDIF error code.
*
*************************************************************************/
kal_int32 mdci_write_and_wait(MDCI_CHANNEL_T channel, MDCI_BUFF_T *buff, kal_uint32 ticks)
{
kal_uint32 mdci_busy, phy_chann, saveaddr = 0;
kal_int32 ret;
MDCI_BUFF_T *chdata;
volatile kal_uint32 reserved_value=0;
/* query if used in init stage or exception */
if (KAL_TRUE != kal_query_systemInit() && KAL_TRUE != INT_QueryExceptionStatus())
{
return MDCI_API_INVALID;
}
/* check parameters */
if (channel >= MDCI_MAX_CHANNEL)
return MDCI_INVALID_PARAM;
if (buff == NULL)
return MDCI_INVALID_PARAM;
*MDIF_ACK = 0xFFFFFFFF;
/* check state */
ret = MDCI_NOT_RECEIVE;
buff->reserved = MDCI_EXCEPTION_CHECK_ID;
/* get one physical channel */
mdci_busy = *MDIF_BUSY;
if (0xFF == mdci_busy)
{
return MDCI_NO_PHY_CHANNEL;
}
for (phy_chann = mdci_writeindx_for_FC ; phy_chann < (mdci_writeindx_for_FC + MDIF_MAX_PHY); phy_chann++)
{
phy_chann %= MDIF_MAX_PHY;
chdata = (MDCI_BUFF_T *)MDIF_TXCHDATA + phy_chann;
reserved_value = *(volatile kal_uint32*)(&(chdata->reserved));
if (reserved_value == MDCI_EXCEPTION_CHECK_ID)
{
return MDCI_NO_PHY_CHANNEL;
}
else
{
/* set BUSY bit */
*MDIF_BUSY |= (1 << phy_chann);
mdci_writeindx_for_FC = (phy_chann + 1)%MDIF_MAX_PHY;
break;
}
}
/* set logical channel number */
buff->channel = channel;
/* copy channel buffer */
chdata = (MDCI_BUFF_T *)MDIF_TXCHDATA + phy_chann;
kal_mem_cpy(chdata, buff, sizeof(MDCI_BUFF_T));
/* restore the stream buffer address */
if (!MDCI_IS_MAILBOX(buff)) {
MDCI_STREAM_ADDR(buff) = saveaddr;
}
/* start MDIF */
*MDIF_TCHNUM = phy_chann;
while (ticks > 0)
{
reserved_value = *(volatile kal_uint32*)(&(chdata->reserved));
if (reserved_value != MDCI_EXCEPTION_CHECK_ID)
{
ret = MDCI_SUCCESS;
break;
}
ust_busy_wait(1);
ticks--;
}
return ret;
}
