void msm_axi_subdev_release(struct v4l2_subdev *sd)
{
struct msm_cam_media_controller *pmctl =
(struct msm_cam_media_controller *)v4l2_get_subdev_hostdata(sd);
struct axi_ctrl_t *axi_ctrl = v4l2_get_subdevdata(sd);
if (!axi_ctrl->share_ctrl->vfebase) {
pr_err("%s: base address unmapped\n", __func__);
return;
}
CDBG("%s, free_irq\n", __func__);
disable_irq(axi_ctrl->vfeirq->start);
tasklet_kill(&axi_ctrl->vfe40_tasklet);
msm_cam_clk_enable(&axi_ctrl->pdev->dev, vfe40_clk_info,
axi_ctrl->vfe_clk, ARRAY_SIZE(vfe40_clk_info), 0);
if (axi_ctrl->fs_vfe) {
regulator_disable(axi_ctrl->fs_vfe);
regulator_put(axi_ctrl->fs_vfe);
axi_ctrl->fs_vfe = NULL;
}
iounmap(axi_ctrl->share_ctrl->vfebase);
axi_ctrl->share_ctrl->vfebase = NULL;
if (atomic_read(&axi_ctrl->share_ctrl->irq_cnt))
pr_warning("%s, Warning IRQ Count not ZERO\n", __func__);
msm_camio_bus_scale_cfg(
pmctl->sdata->pdata->cam_bus_scale_table, S_EXIT);
}
static int fimc_lite_hw_init(struct fimc_lite *fimc)
{
struct fimc_pipeline *pipeline = &fimc->pipeline;
struct fimc_sensor_info *sensor;
unsigned long flags;
if (pipeline->subdevs[IDX_SENSOR] == NULL)
return -ENXIO;
if (fimc->fmt == NULL)
return -EINVAL;
sensor = v4l2_get_subdev_hostdata(pipeline->subdevs[IDX_SENSOR]);
spin_lock_irqsave(&fimc->slock, flags);
flite_hw_set_camera_bus(fimc, &sensor->pdata);
flite_hw_set_source_format(fimc, &fimc->inp_frame);
flite_hw_set_window_offset(fimc, &fimc->inp_frame);
flite_hw_set_output_dma(fimc, &fimc->out_frame, true);
flite_hw_set_interrupt_mask(fimc);
flite_hw_set_test_pattern(fimc, fimc->test_pattern->val);
if (debug > 0)
flite_hw_dump_regs(fimc, __func__);
spin_unlock_irqrestore(&fimc->slock, flags);
return 0;
}
/**
* fimc_sensor_notify - v4l2_device notification from a sensor subdev
* @sd: pointer to a subdev generating the notification
* @notification: the notification type, must be S5P_FIMC_TX_END_NOTIFY
* @arg: pointer to an u32 type integer that stores the frame payload value
*
* The End Of Frame notification sent by sensor subdev in its still capture
* mode. If there is only a single VSYNC generated by the sensor at the
* beginning of a frame transmission, FIMC does not issue the LastIrq
* (end of frame) interrupt. And this notification is used to complete the
* frame capture and returning a buffer to user-space. Subdev drivers should
* call this notification from their last 'End of frame capture' interrupt.
*/
void fimc_sensor_notify(struct v4l2_subdev *sd, unsigned int notification,
void *arg)
{
struct fimc_sensor_info *sensor;
struct fimc_vid_buffer *buf;
struct fimc_md *fmd;
struct fimc_dev *fimc;
unsigned long flags;
if (sd == NULL)
return;
sensor = v4l2_get_subdev_hostdata(sd);
fmd = entity_to_fimc_mdev(&sd->entity);
spin_lock_irqsave(&fmd->slock, flags);
fimc = sensor ? sensor->host : NULL;
if (fimc && arg && notification == S5P_FIMC_TX_END_NOTIFY &&
test_bit(ST_CAPT_PEND, &fimc->state)) {
unsigned long irq_flags;
spin_lock_irqsave(&fimc->slock, irq_flags);
if (!list_empty(&fimc->vid_cap.active_buf_q)) {
buf = list_entry(fimc->vid_cap.active_buf_q.next,
struct fimc_vid_buffer, list);
vb2_set_plane_payload(&buf->vb, 0, *((u32 *)arg));
}
/**
* fimc_md_set_camclk - peripheral sensor clock setup
* @sd: sensor subdev to configure sclk_cam clock for
* @on: 1 to enable or 0 to disable the clock
*
* There are 2 separate clock outputs available in the SoC for external
* image processors. These clocks are shared between all registered FIMC
* devices to which sensors can be attached, either directly or through
* the MIPI CSI receiver. The clock is allowed here to be used by
* multiple sensors concurrently if they use same frequency.
* The per sensor subdev clk_on attribute helps to synchronize accesses
* to the sclk_cam clocks from the video and media device nodes.
* This function should only be called when the graph mutex is held.
*/
int fimc_md_set_camclk(struct v4l2_subdev *sd, bool on)
{
struct fimc_sensor_info *s_info = v4l2_get_subdev_hostdata(sd);
struct fimc_md *fmd = entity_to_fimc_mdev(&sd->entity);
return __fimc_md_set_camclk(fmd, s_info, on);
}
void gsc_hw_set_input_path(struct gsc_ctx *ctx)
{
struct gsc_dev *dev = ctx->gsc_dev;
u32 cfg = readl(dev->regs + GSC_IN_CON);
cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
if (ctx->in_path == GSC_DMA) {
cfg |= GSC_IN_PATH_MEMORY;
} else {
cfg |= GSC_IN_PATH_LOCAL;
if (ctx->in_path == GSC_WRITEBACK) {
cfg |= GSC_IN_LOCAL_FIMD_WB;
} else {
struct v4l2_subdev *sd = dev->pipeline.sensor;
struct gsc_sensor_info *s_info =
v4l2_get_subdev_hostdata(sd);
if (s_info->pdata->cam_port == CAM_PORT_A)
cfg |= GSC_IN_LOCAL_CAM0;
else
cfg |= GSC_IN_LOCAL_CAM1;
}
}
writel(cfg, dev->regs + GSC_IN_CON);
}
/*
* Configure MIPI CSI physical parameters.
* @port: ATOMISP_CAMERA_PORT_PRIMARY or ATOMISP_CAMERA_PORT_SECONDARY
* @lanes: for ATOMISP_CAMERA_PORT_PRIMARY, there could be 2 or 4 lanes
* for ATOMISP_CAMERA_PORT_SECONDARY, there is only one lane.
* @format: MIPI CSI pixel format, see include/linux/atomisp_platform.h
* @bayer_order: MIPI CSI bayer order, see include/linux/atomisp_platform.h
*/
int camera_sensor_csi(struct v4l2_subdev *sd, u32 port,
u32 lanes, u32 format, u32 bayer_order, int flag)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
struct camera_mipi_info *csi = NULL;
if (flag) {
csi = kzalloc(sizeof(*csi), GFP_KERNEL);
if (!csi) {
dev_err(&client->dev, "out of memory\n");
return -ENOMEM;
}
csi->port = port;
csi->num_lanes = lanes;
csi->input_format = format;
csi->raw_bayer_order = bayer_order;
v4l2_set_subdev_hostdata(sd, (void *)csi);
csi->metadata_format = ATOMISP_INPUT_FORMAT_EMBEDDED;
csi->metadata_effective_width = NULL;
dev_info(&client->dev,
"camera pdata: port: %d lanes: %d order: %8.8x\n",
port, lanes, bayer_order);
} else {
csi = v4l2_get_subdev_hostdata(sd);
kfree(csi);
}
return 0;
}
static int msm_vpe_subdev_close(struct v4l2_subdev *sd,
struct v4l2_subdev_fh *fh)
{
struct vpe_ctrl_type *vpe_ctrl = v4l2_get_subdevdata(sd);
struct msm_mctl_pp_frame_info *frame_info = vpe_ctrl->pp_frame_info;
struct msm_cam_media_controller *mctl;
mctl = v4l2_get_subdev_hostdata(sd);
if (atomic_read(&vpe_ctrl->active) == 0) {
pr_err("%s already closed\n", __func__);
return -EINVAL;
}
D("%s E ", __func__);
if (frame_info) {
D("%s Unmap the pending item from the queue ", __func__);
msm_mctl_unmap_user_frame(&frame_info->src_frame,
frame_info->p_mctl->client, mctl->domain_num);
msm_mctl_unmap_user_frame(&frame_info->dest_frame,
frame_info->p_mctl->client, mctl->domain_num);
// LGE_CHANGE_S, [email protected] 2012.12.30, this Patch is for ION MMUNMAP
// Because of this, getting VT during the video capture always goes to Kernel Crash.
kfree(frame_info);
vpe_ctrl->pp_frame_info = NULL;
// LGE_CHANGE_E, [email protected] 2012.12.30, this Patch is for ION MMUNMAP
}
/* Drain the payload queue. */
msm_queue_drain(&vpe_ctrl->eventData_q, list_eventdata);
atomic_dec(&vpe_ctrl->active);
return 0;
}
/*
* Configure MIPI CSI physical parameters.
* @port: ATOMISP_CAMERA_PORT_PRIMARY or ATOMISP_CAMERA_PORT_SECONDARY
* @lanes: for ATOMISP_CAMERA_PORT_PRIMARY, there could be 2 or 4 lanes
* for ATOMISP_CAMERA_PORT_SECONDARY, there is only one lane.
* @format: MIPI CSI pixel format, see include/linux/atomisp_platform.h
* @bayer_order: MIPI CSI bayer order, see include/linux/atomisp_platform.h
*/
int camera_sensor_csi(struct v4l2_subdev *sd, u32 port,
u32 lanes, u32 format, u32 bayer_order,
bool need_sof_signal, int flag)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
struct camera_mipi_info *csi = NULL;
if (flag) {
csi = kzalloc(sizeof(*csi), GFP_KERNEL);
if (!csi) {
dev_err(&client->dev, "out of memory\n");
return -ENOMEM;
}
csi->port = port;
csi->num_lanes = lanes;
csi->input_format = format;
csi->raw_bayer_order = bayer_order;
csi->need_sof_signal = need_sof_signal;
v4l2_set_subdev_hostdata(sd, (void *)csi);
} else {
csi = v4l2_get_subdev_hostdata(sd);
kfree(csi);
}
return 0;
}
static int ov2680_h_flip(struct v4l2_subdev *sd, s32 value)
{
struct ov2680_device *dev = to_ov2680_sensor(sd);
struct camera_mipi_info *ov2680_info = NULL;
struct i2c_client *client = v4l2_get_subdevdata(sd);
int ret;
u16 val;
u8 index;
dev_dbg(&client->dev, "@%s: value:%d\n", __func__, value);
ret = ov2680_read_reg(client, OV2680_8BIT, OV2680_MIRROR_REG, &val);
if (ret)
return ret;
if (value) {
val |= OV2680_FLIP_MIRROR_BIT_ENABLE;
} else {
val &= ~OV2680_FLIP_MIRROR_BIT_ENABLE;
}
ret = ov2680_write_reg(client, OV2680_8BIT,
OV2680_MIRROR_REG, val);
if (ret)
return ret;
index = (v_flag>0?OV2680_FLIP_BIT:0) | (h_flag>0?OV2680_MIRROR_BIT:0);
ov2680_info = v4l2_get_subdev_hostdata(sd);
if (ov2680_info) {
ov2680_info->raw_bayer_order = ov2680_bayer_order_mapping[index];
dev->format.code = ov2680_translate_bayer_order(
ov2680_info->raw_bayer_order);
}
return ret;
}
static int fimc_lite_hw_init(struct fimc_lite *fimc, bool isp_output)
{
struct fimc_source_info *si;
unsigned long flags;
if (fimc->sensor == NULL)
return -ENXIO;
if (fimc->inp_frame.fmt == NULL || fimc->out_frame.fmt == NULL)
return -EINVAL;
/* Get sensor configuration data from the sensor subdev */
si = v4l2_get_subdev_hostdata(fimc->sensor);
if (!si)
return -EINVAL;
spin_lock_irqsave(&fimc->slock, flags);
flite_hw_set_camera_bus(fimc, si);
flite_hw_set_source_format(fimc, &fimc->inp_frame);
flite_hw_set_window_offset(fimc, &fimc->inp_frame);
flite_hw_set_dma_buf_mask(fimc, 0);
flite_hw_set_output_dma(fimc, &fimc->out_frame, !isp_output);
flite_hw_set_interrupt_mask(fimc);
flite_hw_set_test_pattern(fimc, fimc->test_pattern->val);
if (debug > 0)
flite_hw_dump_regs(fimc, __func__);
spin_unlock_irqrestore(&fimc->slock, flags);
return 0;
}
int find_subdev_mipi(struct decon_device *decon)
{
struct exynos_md *md;
if (decon->id && decon->pdata->dsi_mode == DSI_MODE_SINGLE) {
decon_err("failed to get subdev of dsim\n");
return -EINVAL;
}
md = (struct exynos_md *)module_name_to_driver_data(MDEV_MODULE_NAME);
if (!md) {
decon_err("failed to get mdev device(%d)\n", decon->id);
return -ENODEV;
}
decon->output_sd = md->dsim_sd[decon->id];
decon->out_type = DECON_OUT_DSI;
if (IS_ERR_OR_NULL(decon->output_sd))
decon_warn("couldn't find dsim%d subdev\n", decon->id);
v4l2_subdev_call(decon->output_sd, core, ioctl, DSIM_IOC_GET_LCD_INFO, NULL);
decon->lcd_info = (struct decon_lcd *)v4l2_get_subdev_hostdata(decon->output_sd);
if (IS_ERR_OR_NULL(decon->lcd_info)) {
decon_err("failed to get lcd information\n");
return -EINVAL;
}
return 0;
}
static int msm_vpe_subdev_close(struct v4l2_subdev *sd,
struct v4l2_subdev_fh *fh)
{
struct vpe_ctrl_type *vpe_ctrl = v4l2_get_subdevdata(sd);
struct msm_mctl_pp_frame_info *frame_info = vpe_ctrl->pp_frame_info;
struct msm_cam_media_controller *mctl;
mctl = v4l2_get_subdev_hostdata(sd);
if (atomic_read(&vpe_ctrl->active) == 0) {
pr_err("%s already closed\n", __func__);
return -EINVAL;
}
D("%s E ", __func__);
if (frame_info) {
D("%s Unmap the pending item from the queue ", __func__);
msm_mctl_unmap_user_frame(&frame_info->src_frame,
frame_info->p_mctl->client, mctl->domain_num);
msm_mctl_unmap_user_frame(&frame_info->dest_frame,
frame_info->p_mctl->client, mctl->domain_num);
}
vpe_ctrl->pp_frame_info = NULL;
/* Drain the payload queue. */
msm_queue_drain(&vpe_ctrl->eventData_q, list_eventdata);
atomic_dec(&vpe_ctrl->active);
return 0;
}
static int nxp_video_streamon(struct file *file, void *fh,
enum v4l2_buf_type i)
{
int ret;
u32 pad;
struct nxp_video *me = file->private_data;
struct v4l2_subdev *subdev = _get_remote_subdev(me, i, &pad);
void *hostdata_back;
vmsg("%s: me %p, %s\n", __func__, me, me->name);
if (me->vbq) {
ret = vb2_streamon(me->vbq, i);
if (ret < 0) {
pr_err("%s: failed to vb2_streamon()\n", __func__);
return ret;
}
} else {
struct vb2_queue *vq = v4l2_m2m_get_vq(me->m2m_ctx, i);
ret = vb2_streamon(vq, i);
if (ret < 0) {
pr_err("%s: m2m, failed to vb2_streamon()\n", __func__);
return ret;
}
}
/* for mlc subdev */
hostdata_back = v4l2_get_subdev_hostdata(subdev);
v4l2_set_subdev_hostdata(subdev, me->name);
ret = v4l2_subdev_call(subdev, video, s_stream, 1);
v4l2_set_subdev_hostdata(subdev, hostdata_back);
return ret;
}
static int fimc_lite_subdev_registered(struct v4l2_subdev *sd)
{
struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
struct vb2_queue *q = &fimc->vb_queue;
struct video_device *vfd = &fimc->vfd;
int ret;
memset(vfd, 0, sizeof(*vfd));
fimc->fmt = &fimc_lite_formats[0];
fimc->out_path = FIMC_IO_DMA;
snprintf(vfd->name, sizeof(vfd->name), "fimc-lite.%d.capture",
fimc->index);
vfd->fops = &fimc_lite_fops;
vfd->ioctl_ops = &fimc_lite_ioctl_ops;
vfd->v4l2_dev = sd->v4l2_dev;
vfd->minor = -1;
vfd->release = video_device_release_empty;
vfd->lock = &fimc->lock;
fimc->ref_count = 0;
fimc->reqbufs_count = 0;
INIT_LIST_HEAD(&fimc->pending_buf_q);
INIT_LIST_HEAD(&fimc->active_buf_q);
memset(q, 0, sizeof(*q));
q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
q->io_modes = VB2_MMAP | VB2_USERPTR;
q->ops = &fimc_lite_qops;
q->mem_ops = &vb2_dma_contig_memops;
q->buf_struct_size = sizeof(struct flite_buffer);
q->drv_priv = fimc;
ret = vb2_queue_init(q);
if (ret < 0)
return ret;
fimc->vd_pad.flags = MEDIA_PAD_FL_SINK;
ret = media_entity_init(&vfd->entity, 1, &fimc->vd_pad, 0);
if (ret < 0)
return ret;
video_set_drvdata(vfd, fimc);
fimc->pipeline_ops = v4l2_get_subdev_hostdata(sd);
ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
if (ret < 0) {
media_entity_cleanup(&vfd->entity);
fimc->pipeline_ops = NULL;
return ret;
}
v4l2_info(sd->v4l2_dev, "Registered %s as /dev/%s\n",
vfd->name, video_device_node_name(vfd));
return 0;
}
/**
* fimc_md_set_camclk - peripheral sensor clock setup
* @sd: sensor subdev to configure sclk_cam clock for
* @on: 1 to enable or 0 to disable the clock
*
* There are 2 separate clock outputs available in the SoC for external
* image processors. These clocks are shared between all registered FIMC
* devices to which sensors can be attached, either directly or through
* the MIPI CSI receiver. The clock is allowed here to be used by
* multiple sensors concurrently if they use same frequency.
* This function should only be called when the graph mutex is held.
*/
int fimc_md_set_camclk(struct v4l2_subdev *sd, bool on)
{
struct fimc_sensor_info *s_info = v4l2_get_subdev_hostdata(sd);
if ((gfmd->fimc[0]->vid_cap.use_isp) && !s_info) {
s_info = &gfmd->sensor[0];
gfmd->fimc[0]->vid_cap.s_info = s_info;
gfmd->fimc[1]->vid_cap.s_info = s_info;
s_info->pdata->clk_id = 1;
}
return __fimc_md_set_camclk(gfmd, s_info, on);
}
static int msm_isp_notify_vpe(struct v4l2_subdev *sd, void *arg)
{
struct msm_sync *sync =
(struct msm_sync *)v4l2_get_subdev_hostdata(sd);
struct msm_vpe_resp *vdata = (struct msm_vpe_resp *)arg;
if (sync == NULL) {
pr_err("%s: VPE subdev hostdata not set\n", __func__);
return -EINVAL;
}
msm_mctl_pp_notify(&sync->pcam_sync->mctl,
(struct msm_mctl_pp_frame_info *)vdata->extdata);
return 0;
}
/**
* __fimc_md_create_fimc_links - create links to all FIMC entities
* @fmd: fimc media device
* @source: the source entity to create links to all fimc entities from
* @sensor: sensor subdev linked to FIMC[fimc_id] entity, may be null
* @pad: the source entity pad index
* @fimc_id: index of the fimc device for which link should be enabled
*/
static int __fimc_md_create_fimc_links(struct fimc_md *fmd,
struct media_entity *source,
struct v4l2_subdev *sensor,
int pad, int fimc_id)
{
struct fimc_sensor_info *s_info;
struct media_entity *sink;
unsigned int flags;
int ret, i;
for (i = 0; i < FIMC_MAX_DEVS; i++) {
if (!fmd->fimc[i])
break;
/*
* Some FIMC variants are not fitted with camera capture
* interface. Skip creating a link from sensor for those.
*/
if (sensor->grp_id == SENSOR_GROUP_ID &&
!fmd->fimc[i]->variant->has_cam_if)
continue;
flags = (i == fimc_id) ? MEDIA_LNK_FL_ENABLED : 0;
sink = &fmd->fimc[i]->vid_cap.subdev->entity;
ret = media_entity_create_link(source, pad, sink,
FIMC_SD_PAD_SINK, flags);
if (ret)
return ret;
/* Notify FIMC capture subdev entity */
ret = media_entity_call(sink, link_setup, &sink->pads[0],
&source->pads[pad], flags);
if (ret)
break;
v4l2_info(&fmd->v4l2_dev, "created link [%s] %c> [%s]",
source->name, flags ? '=' : '-', sink->name);
if (flags == 0)
continue;
s_info = v4l2_get_subdev_hostdata(sensor);
if (!WARN_ON(s_info == NULL)) {
unsigned long irq_flags;
spin_lock_irqsave(&fmd->slock, irq_flags);
s_info->host = fmd->fimc[i];
spin_unlock_irqrestore(&fmd->slock, irq_flags);
}
}
return 0;
}
void flite_hw_set_sensor_type(struct flite_dev *dev)
{
struct v4l2_subdev *sd = dev->pipeline.sensor;
struct flite_sensor_info *s_info = v4l2_get_subdev_hostdata(sd);
u32 cfg = 0;
cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
if (s_info->pdata->bus_type == CAM_TYPE_ITU)
cfg &= ~FLITE_REG_CIGCTRL_SELCAM_MIPI;
else
cfg |= FLITE_REG_CIGCTRL_SELCAM_MIPI;
writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
}
static int fimc_isp_subdev_registered(struct v4l2_subdev *sd)
{
struct fimc_isp *isp = v4l2_get_subdevdata(sd);
int ret;
/* Use pipeline object allocated by the media device. */
isp->video_capture.ve.pipe = v4l2_get_subdev_hostdata(sd);
ret = fimc_isp_video_device_register(isp, sd->v4l2_dev,
V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
if (ret < 0)
isp->video_capture.ve.pipe = NULL;
return ret;
}
void msm_vpe_subdev_release(struct v4l2_subdev *sd)
{
struct msm_cam_media_controller *mctl;
mctl = v4l2_get_subdev_hostdata(sd);
if (!atomic_read(&vpe_init_done)) {
/* no VPE object created */
pr_err("%s: no VPE object to release", __func__);
return;
}
vpe_reset();
vpe_disable(mctl);
iounmap(vpe_ctrl->vpebase);
vpe_ctrl->vpebase = NULL;
atomic_set(&vpe_init_done, 0);
}
int sensor_module_s_stream(struct v4l2_subdev *subdev, int enable)
{
int ret = 0;
struct fimc_is_device_sensor *device = NULL;
BUG_ON(!subdev);
device = (struct fimc_is_device_sensor *)v4l2_get_subdev_hostdata(subdev);
BUG_ON(!device);
ret = fimc_is_sensor_peri_s_stream(device, enable);
if (ret)
err("[SEN] fimc_is_sensor_peri_s_stream is fail(%d)", ret);
return ret;
}
/* Set up image sensor subdev -> FIMC capture node notifications. */
static void __setup_sensor_notification(struct fimc_md *fmd,
struct v4l2_subdev *sensor,
struct v4l2_subdev *fimc_sd)
{
struct fimc_source_info *src_inf;
struct fimc_sensor_info *md_si;
unsigned long flags;
src_inf = v4l2_get_subdev_hostdata(sensor);
if (!src_inf || WARN_ON(fmd == NULL))
return;
md_si = source_to_sensor_info(src_inf);
spin_lock_irqsave(&fmd->slock, flags);
md_si->host = v4l2_get_subdevdata(fimc_sd);
spin_unlock_irqrestore(&fmd->slock, flags);
}
void flite_hw_set_inverse_polarity(struct flite_dev *dev)
{
struct v4l2_subdev *sd = dev->pipeline.sensor;
struct flite_sensor_info *s_info = v4l2_get_subdev_hostdata(sd);
u32 cfg = 0;
cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
cfg &= ~(FLITE_REG_CIGCTRL_INVPOLPCLK | FLITE_REG_CIGCTRL_INVPOLVSYNC
| FLITE_REG_CIGCTRL_INVPOLHREF);
if (s_info->pdata->flags & CAM_CLK_INV_PCLK)
cfg |= FLITE_REG_CIGCTRL_INVPOLPCLK;
if (s_info->pdata->flags & CAM_CLK_INV_VSYNC)
cfg |= FLITE_REG_CIGCTRL_INVPOLVSYNC;
if (s_info->pdata->flags & CAM_CLK_INV_HREF)
cfg |= FLITE_REG_CIGCTRL_INVPOLHREF;
writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
}
static int hm5040_s_mbus_fmt(struct v4l2_subdev *sd,
struct v4l2_mbus_framefmt *fmt)
{
struct hm5040_device *dev = to_hm5040_sensor(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
struct camera_mipi_info *hm5040_info = NULL;
int ret = 0;
hm5040_info = v4l2_get_subdev_hostdata(sd);
if (hm5040_info == NULL)
return -EINVAL;
pr_info("%s\n", __func__);
mutex_lock(&dev->input_lock);
ret = hm5040_try_mbus_fmt(sd, fmt);
if (ret == -1) {
dev_err(&client->dev, "try fmt fail\n");
goto err;
}
dev->fmt_idx = get_resolution_index(fmt->width,
fmt->height);
if (dev->fmt_idx == -1) {
dev_err(&client->dev, "get resolution fail\n");
mutex_unlock(&dev->input_lock);
return -EINVAL;
}
ret = startup(sd);
if (ret)
dev_err(&client->dev, "hm5040 startup err\n");
ret = hm5040_get_intg_factor(client, hm5040_info,
&hm5040_res[dev->fmt_idx]);
if (ret) {
dev_err(&client->dev, "failed to get integration_factor\n");
goto err;
}
err:
mutex_unlock(&dev->input_lock);
return ret;
}
static void gsc_set_cam_clock(struct gsc_dev *gsc, bool on)
{
struct v4l2_subdev *sd = NULL;
struct gsc_sensor_info *s_info = NULL;
if (gsc->pipeline.sensor) {
sd = gsc->pipeline.sensor;
s_info = v4l2_get_subdev_hostdata(sd);
}
if (on) {
clk_enable(gsc->clock);
if (gsc->pipeline.sensor)
clk_enable(s_info->camclk);
} else {
clk_disable(gsc->clock);
if (gsc->pipeline.sensor)
clk_disable(s_info->camclk);
}
}
static int fimc_capture_hw_init(struct fimc_dev *fimc)
{
struct fimc_ctx *ctx = fimc->vid_cap.ctx;
struct fimc_pipeline *p = &fimc->pipeline;
struct fimc_sensor_info *sensor;
unsigned long flags;
int ret = 0;
if (p->subdevs[IDX_SENSOR] == NULL || ctx == NULL)
return -ENXIO;
if (ctx->s_frame.fmt == NULL)
return -EINVAL;
sensor = v4l2_get_subdev_hostdata(p->subdevs[IDX_SENSOR]);
spin_lock_irqsave(&fimc->slock, flags);
fimc_prepare_dma_offset(ctx, &ctx->d_frame);
fimc_set_yuv_order(ctx);
fimc_hw_set_camera_polarity(fimc, &sensor->pdata);
fimc_hw_set_camera_type(fimc, &sensor->pdata);
fimc_hw_set_camera_source(fimc, &sensor->pdata);
fimc_hw_set_camera_offset(fimc, &ctx->s_frame);
ret = fimc_set_scaler_info(ctx);
if (!ret) {
fimc_hw_set_input_path(ctx);
fimc_hw_set_prescaler(ctx);
fimc_hw_set_mainscaler(ctx);
fimc_hw_set_target_format(ctx);
fimc_hw_set_rotation(ctx);
fimc_hw_set_effect(ctx);
fimc_hw_set_output_path(ctx);
fimc_hw_set_out_dma(ctx);
if (fimc->variant->has_alpha)
fimc_hw_set_rgb_alpha(ctx);
clear_bit(ST_CAPT_APPLY_CFG, &fimc->state);
}
spin_unlock_irqrestore(&fimc->slock, flags);
return ret;
}
int msm_vpe_subdev_init(struct v4l2_subdev *sd)
{
int rc = 0;
struct msm_cam_media_controller *mctl;
mctl = v4l2_get_subdev_hostdata(sd);
D("%s:begin", __func__);
if (atomic_read(&vpe_init_done)) {
pr_err("%s: VPE has been initialized", __func__);
return -EBUSY;
}
atomic_set(&vpe_init_done, 1);
rc = msm_vpe_resource_init();
if (rc < 0) {
atomic_set(&vpe_init_done, 0);
return rc;
}
spin_lock_init(&vpe_ctrl->lock);
D("%s:end", __func__);
return rc;
}
static int ov5693_s_mbus_fmt(struct v4l2_subdev *sd,
struct v4l2_mbus_framefmt *fmt)
{
struct ov5693_device *dev = to_ov5693_sensor(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
struct camera_mipi_info *ov5693_info = NULL;
int ret = 0;
ov5693_info = v4l2_get_subdev_hostdata(sd);
if (ov5693_info == NULL)
return -EINVAL;
mutex_lock(&dev->input_lock);
ret = __ov5693_try_mbus_fmt(sd, fmt);
if (ret == -1) {
dev_err(&client->dev, "try fmt fail\n");
goto done;
}
dev->fmt_idx = get_resolution_index(sd, fmt->width, fmt->height);
if (dev->fmt_idx == -1) {
dev_err(&client->dev, "get resolution fail\n");
goto done;
}
ret = ov5693_write_reg_array(client, dev->ov5693_res[dev->fmt_idx].regs);
if (ret) {
dev_err(&client->dev, "ov5693 write fmt register err.\n");
goto done;
}
ret = ov5693_get_intg_factor(client, ov5693_info,
&dev->ov5693_res[dev->fmt_idx]);
if (ret)
dev_err(&client->dev, "failed to get integration_factor\n");
done:
mutex_unlock(&dev->input_lock);
return ret;
}
static int nxp_video_streamoff(struct file *file, void *fh,
enum v4l2_buf_type i)
{
int ret;
u32 pad;
struct nxp_video *me;
struct v4l2_subdev *subdev;
void *hostdata_back;
me = file->private_data;
subdev = _get_remote_subdev(me, i, &pad);
if (me->vbq) {
ret = vb2_streamoff(me->vbq, i);
if (ret < 0) {
printk(KERN_ERR "%s: failed to vb2_streamoff() %s\n", __func__, me->name);
return 0;
}
} else {
struct vb2_queue *vq = v4l2_m2m_get_vq(me->m2m_ctx, i);
ret = vb2_streamoff(vq, i);
if (ret < 0) {
pr_err(KERN_ERR "%s: m2m, failed to vb2_streamoff() %s\n", __func__, me->name);
return 0;
}
}
vmsg("%s %s\n", __func__, me->name);
hostdata_back = v4l2_get_subdev_hostdata(subdev);
v4l2_set_subdev_hostdata(subdev, me->name);
ret = v4l2_subdev_call(subdev, video, s_stream, 0);
v4l2_set_subdev_hostdata(subdev, hostdata_back);
vmsg("%s: %s exit\n", __func__, me->name);
return ret;
}
static long msm_vpe_subdev_ioctl(struct v4l2_subdev *sd,
unsigned int cmd, void *arg)
{
struct msm_vpe_cfg_cmd *vpe_cmd;
int rc = 0;
struct msm_cam_media_controller *mctl;
mctl = v4l2_get_subdev_hostdata(sd);
switch (cmd) {
case VIDIOC_MSM_VPE_INIT: {
msm_vpe_subdev_init(sd);
break;
}
case VIDIOC_MSM_VPE_RELEASE:
msm_vpe_subdev_release(sd);
break;
case MSM_CAM_V4L2_IOCTL_CFG_VPE: {
vpe_cmd = (struct msm_vpe_cfg_cmd *)arg;
rc = msm_vpe_process_vpe_cmd(vpe_cmd, mctl);
if (rc < 0) {
pr_err("%s Error processing VPE cmd %d ",
__func__, vpe_cmd->cmd_type);
break;
}
break;
}
case MSM_CAM_V4L2_IOCTL_GET_EVENT_PAYLOAD: {
struct msm_device_queue *queue = &vpe_ctrl->eventData_q;
struct msm_queue_cmd *event_qcmd;
struct msm_mctl_pp_event_info pp_event_info;
struct msm_mctl_pp_frame_info *pp_frame_info;
struct msm_camera_v4l2_ioctl_t *v4l2_ioctl = arg;
event_qcmd = msm_dequeue(queue, list_eventdata);
if (!event_qcmd) {
pr_err("%s No events in the queue", __func__);
return -EFAULT;
}
pp_frame_info = event_qcmd->command;
D("%s Unmapping source and destination buffers ",
__func__);
msm_mctl_unmap_user_frame(&pp_frame_info->src_frame,
pp_frame_info->p_mctl->client, mctl->domain_num);
msm_mctl_unmap_user_frame(&pp_frame_info->dest_frame,
pp_frame_info->p_mctl->client, mctl->domain_num);
pp_event_info.event = MCTL_PP_EVENT_CMD_ACK;
pp_event_info.ack.cmd = pp_frame_info->user_cmd;
pp_event_info.ack.status = 0;
pp_event_info.ack.cookie = pp_frame_info->pp_frame_cmd.cookie;
D("%s Sending payload %d %d %d", __func__,
pp_event_info.ack.cmd, pp_event_info.ack.status,
pp_event_info.ack.cookie);
if (copy_to_user((void __user *)v4l2_ioctl->ioctl_ptr,
&pp_event_info, sizeof(struct msm_mctl_pp_event_info)))
pr_err("%s PAYLOAD Copy to user failed ", __func__);
kfree(pp_frame_info);
kfree(event_qcmd);
#ifdef CONFIG_PANTECH_CAMERA // pp_fram_info init
pp_frame_info = NULL;
event_qcmd = NULL;
#endif
break;
}
default:
break;
}
return rc;
}
