void __init mach_early_init (void)
{
ANNA_ILBEN = 0;
V850E2_CSC(0) = 0x402F;
V850E2_CSC(1) = 0x4000;
V850E2_BPC = 0;
V850E2_BSC = 0xAAAA;
V850E2_BEC = 0;
#if 0
V850E2_BHC = 0xFFFF; /* icache all memory, dcache all */
#else
V850E2_BHC = 0; /* cache no memory */
#endif
V850E2_BCT(0) = 0xB088;
V850E2_BCT(1) = 0x0008;
V850E2_DWC(0) = 0x0027;
V850E2_DWC(1) = 0;
V850E2_BCC = 0x0006;
V850E2_ASC = 0;
V850E2_LBS = 0x0089;
V850E2_SCR(3) = 0x21A9;
V850E2_RFS(3) = 0x8121;
v850e_intc_disable_irqs ();
}
void __init rte_cb_early_init (void)
{
v850e_intc_disable_irqs ();
#ifdef CONFIG_RTE_CB_MULTI
multi_init ();
#endif
}
void __init mach_early_init (void)
{
#ifndef CONFIG_ROM_KERNEL
const u32 *src;
register u32 *dst asm ("ep");
#endif
AS85EP1_CSC(0) = 0x0403;
AS85EP1_BCT(0) = 0xB8B8;
AS85EP1_DWC(0) = 0x0104;
AS85EP1_BCC = 0x0012;
AS85EP1_ASC = 0;
AS85EP1_LBS = 0x00A9;
AS85EP1_PORT_PMC(6) = 0xFF; /* valid A0,A1,A20-A25 */
AS85EP1_PORT_PMC(7) = 0x0E; /* valid CS1-CS3 */
AS85EP1_PORT_PMC(9) = 0xFF; /* valid D16-D23 */
AS85EP1_PORT_PMC(10) = 0xFF; /* valid D24-D31 */
AS85EP1_RFS(1) = 0x800c;
AS85EP1_RFS(3) = 0x800c;
AS85EP1_SCR(1) = 0x20A9;
AS85EP1_SCR(3) = 0x20A9;
#ifndef CONFIG_ROM_KERNEL
/* The early chip we have is buggy, and writing the interrupt
vectors into low RAM may screw up, so for non-ROM kernels, we
only rely on the reset vector being downloaded, and copy the
rest of the interrupt vectors into place here. The specific bug
is that writing address N, where (N & 0x10) == 0x10, will _also_
write to address (N - 0x10). We avoid this (effectively) by
writing in 16-byte chunks backwards from the end. */
AS85EP1_IRAMM = 0x3; /* "write-mode" for the internal instruction memory */
src = (u32 *)(((u32)&_intv_copy_src_end - 1) & ~0xF);
dst = (u32 *)&_intv_copy_dst_start
+ (src - (u32 *)&_intv_copy_src_start);
do {
u32 t0 = src[0], t1 = src[1], t2 = src[2], t3 = src[3];
dst[0] = t0;
dst[1] = t1;
dst[2] = t2;
dst[3] = t3;
dst -= 4;
src -= 4;
} while (src > (u32 *)&_intv_copy_src_start);
AS85EP1_IRAMM = 0x0; /* "read-mode" for the internal instruction memory */
#endif /* !CONFIG_ROM_KERNEL */
v850e_intc_disable_irqs ();
}