u32 vcd_enable_clock(struct vcd_dev_ctxt *dev_ctxt,
struct vcd_clnt_ctxt *cctxt)
{
u32 rc = VCD_S_SUCCESS;
u32 set_perf_lvl;
if (dev_ctxt->pwr_clk_state == VCD_PWRCLK_STATE_OFF) {
VCD_MSG_ERROR("vcd_enable_clock(): Already in state "
"VCD_PWRCLK_STATE_OFF\n");
rc = VCD_ERR_FAIL;
} else if (dev_ctxt->pwr_clk_state ==
VCD_PWRCLK_STATE_ON_NOTCLOCKED) {
set_perf_lvl =
dev_ctxt->reqd_perf_lvl >
0 ? dev_ctxt->
reqd_perf_lvl : VCD_MIN_PERF_LEVEL;
rc = vcd_set_perf_level(dev_ctxt, set_perf_lvl);
if (!VCD_FAILED(rc)) {
if (res_trk_enable_clocks()) {
dev_ctxt->pwr_clk_state =
VCD_PWRCLK_STATE_ON_CLOCKED;
}
} else {
rc = VCD_ERR_FAIL;
}
}
if (!VCD_FAILED(rc))
dev_ctxt->active_clnts++;
return rc;
}
u32 vcd_client_power_event(struct vcd_dev_ctxt *dev_ctxt, struct vcd_clnt_ctxt
*cctxt, u32 event)
{
u32 rc = VCD_ERR_FAIL;
switch (event) {
case VCD_EVT_PWR_CLNT_CMD_BEGIN:
rc = vcd_un_gate_clock(dev_ctxt);
break;
case VCD_EVT_PWR_CLNT_CMD_END:
rc = vcd_gate_clock(dev_ctxt);
break;
case VCD_EVT_PWR_CLNT_CMD_FAIL:
if (!vcd_core_is_busy(dev_ctxt))
rc = vcd_gate_clock(dev_ctxt);
break;
case VCD_EVT_PWR_CLNT_PAUSE:
case VCD_EVT_PWR_CLNT_LAST_FRAME:
case VCD_EVT_PWR_CLNT_ERRFATAL:
if (!cctxt)
break;
rc = VCD_S_SUCCESS;
if (cctxt->status.req_perf_lvl) {
dev_ctxt->reqd_perf_lvl -= cctxt->reqd_perf_lvl;
cctxt->status.req_perf_lvl = false;
rc = vcd_set_perf_level(dev_ctxt,
dev_ctxt->reqd_perf_lvl, cctxt);
}
break;
case VCD_EVT_PWR_CLNT_RESUME:
case VCD_EVT_PWR_CLNT_FIRST_FRAME:
if (!cctxt)
break;
rc = VCD_S_SUCCESS;
if (!cctxt->status.req_perf_lvl) {
dev_ctxt->reqd_perf_lvl += cctxt->reqd_perf_lvl;
cctxt->status.req_perf_lvl = true;
rc = vcd_set_perf_level(dev_ctxt,
dev_ctxt->reqd_perf_lvl, cctxt);
}
break;
}
return rc;
}
u32 vcd_device_power_event(struct vcd_dev_ctxt *dev_ctxt, u32 event,
struct vcd_clnt_ctxt *cctxt)
{
u32 rc = VCD_ERR_FAIL;
u32 set_perf_lvl;
switch (event) {
case VCD_EVT_PWR_DEV_INIT_BEGIN:
if (dev_ctxt->pwr_clk_state == VCD_PWRCLK_STATE_OFF &&
res_trk_get_max_perf_level(
&dev_ctxt->max_perf_lvl) &&
res_trk_power_up()) {
dev_ctxt->pwr_clk_state =
VCD_PWRCLK_STATE_ON_NOTCLOCKED;
dev_ctxt->curr_perf_lvl = 0;
dev_ctxt->reqd_perf_lvl = 0;
dev_ctxt->active_clnts = 0;
dev_ctxt->set_perf_lvl_pending = false;
rc = vcd_enable_clock(dev_ctxt, cctxt);
if (VCD_FAILED(rc)) {
res_trk_power_down();
dev_ctxt->pwr_clk_state = VCD_PWRCLK_STATE_OFF;
}
}
break;
case VCD_EVT_PWR_DEV_INIT_END:
case VCD_EVT_PWR_DEV_TERM_FAIL:
case VCD_EVT_PWR_DEV_SLEEP_BEGIN:
case VCD_EVT_PWR_DEV_HWTIMEOUT:
rc = vcd_gate_clock(dev_ctxt);
break;
case VCD_EVT_PWR_DEV_INIT_FAIL:
case VCD_EVT_PWR_DEV_TERM_END:
if (dev_ctxt->pwr_clk_state != VCD_PWRCLK_STATE_OFF) {
vcd_disable_clock(dev_ctxt);
res_trk_power_down();
dev_ctxt->pwr_clk_state = VCD_PWRCLK_STATE_OFF;
dev_ctxt->curr_perf_lvl = 0;
dev_ctxt->reqd_perf_lvl = 0;
dev_ctxt->active_clnts = 0;
dev_ctxt->set_perf_lvl_pending = false;
rc = VCD_S_SUCCESS;
}
break;
case VCD_EVT_PWR_DEV_TERM_BEGIN:
case VCD_EVT_PWR_DEV_SLEEP_END:
rc = vcd_un_gate_clock(dev_ctxt);
break;
case VCD_EVT_PWR_DEV_SET_PERFLVL:
set_perf_lvl = dev_ctxt->reqd_perf_lvl > 0 ?
dev_ctxt->reqd_perf_lvl : VCD_MIN_PERF_LEVEL;
rc = vcd_set_perf_level(dev_ctxt, set_perf_lvl, cctxt);
break;
}
return rc;
}
u32 vcd_update_clnt_perf_lvl(
struct vcd_clnt_ctxt *cctxt,
struct vcd_property_frame_rate *fps, u32 frm_p_units)
{
u32 rc = VCD_S_SUCCESS;
struct vcd_dev_ctxt *dev_ctxt = cctxt->dev_ctxt;
u32 new_perf_lvl;
new_perf_lvl = frm_p_units *\
(fps->fps_numerator / fps->fps_denominator);
if (cctxt->status.req_perf_lvl) {
dev_ctxt->reqd_perf_lvl =
dev_ctxt->reqd_perf_lvl - cctxt->reqd_perf_lvl +
new_perf_lvl;
rc = vcd_set_perf_level(cctxt->dev_ctxt,
dev_ctxt->reqd_perf_lvl);
}
cctxt->reqd_perf_lvl = new_perf_lvl;
return rc;
}
u32 vcd_enable_clock(struct vcd_dev_ctxt_type *p_dev_ctxt,
struct vcd_clnt_ctxt_type_t *p_cctxt)
{
u32 rc = VCD_S_SUCCESS;
u32 n_set_perf_lvl;
if (p_dev_ctxt->e_pwr_clk_state == VCD_PWRCLK_STATE_OFF) {
VCD_MSG_ERROR("vcd_enable_clock(): Already in state "
"VCD_PWRCLK_STATE_OFF\n");
vcd_assert();
rc = VCD_ERR_FAIL;
} else if (p_dev_ctxt->e_pwr_clk_state ==
VCD_PWRCLK_STATE_ON_NOTCLOCKED) {
n_set_perf_lvl =
p_dev_ctxt->n_reqd_perf_lvl >
0 ? p_dev_ctxt->
n_reqd_perf_lvl : VCD_MIN_PERF_LEVEL;
rc = vcd_set_perf_level(p_dev_ctxt, n_set_perf_lvl,
p_cctxt);
if (!VCD_FAILED(rc)) {
if (res_trk_enable_clocks()) {
p_dev_ctxt->e_pwr_clk_state =
VCD_PWRCLK_STATE_ON_CLOCKED;
}
} else {
rc = VCD_ERR_FAIL;
}
}
if (!VCD_FAILED(rc))
p_dev_ctxt->n_active_clnts++;
return rc;
}
u32 vcd_update_clnt_perf_lvl(
struct vcd_clnt_ctxt_type_t *p_cctxt,
struct vcd_property_frame_rate_type *p_fps, u32 n_frm_p_units)
{
u32 rc = VCD_S_SUCCESS;
struct vcd_dev_ctxt_type *p_dev_ctxt = p_cctxt->p_dev_ctxt;
u32 n_new_perf_lvl;
n_new_perf_lvl =
n_frm_p_units * p_fps->n_fps_numerator / p_fps->n_fps_denominator;
if (p_cctxt->status.b_req_perf_lvl) {
p_dev_ctxt->n_reqd_perf_lvl =
p_dev_ctxt->n_reqd_perf_lvl - p_cctxt->n_reqd_perf_lvl +
n_new_perf_lvl;
rc = vcd_set_perf_level(p_cctxt->p_dev_ctxt,
p_dev_ctxt->n_reqd_perf_lvl, p_cctxt);
}
p_cctxt->n_reqd_perf_lvl = n_new_perf_lvl;
return rc;
}
u32 vcd_client_power_event(
struct vcd_dev_ctxt_type *p_dev_ctxt,
struct vcd_clnt_ctxt_type_t *p_cctxt, u32 event)
{
u32 rc = VCD_ERR_FAIL;
switch (event) {
case VCD_EVT_PWR_CLNT_CMD_BEGIN:
{
rc = vcd_un_gate_clock(p_dev_ctxt);
break;
}
case VCD_EVT_PWR_CLNT_CMD_END:
{
rc = vcd_gate_clock(p_dev_ctxt);
break;
}
case VCD_EVT_PWR_CLNT_CMD_FAIL:
{
if (!vcd_core_is_busy(p_dev_ctxt))
rc = vcd_gate_clock(p_dev_ctxt);
break;
}
case VCD_EVT_PWR_CLNT_PAUSE:
case VCD_EVT_PWR_CLNT_LAST_FRAME:
case VCD_EVT_PWR_CLNT_ERRFATAL:
{
if (p_cctxt) {
rc = VCD_S_SUCCESS;
if (p_cctxt->status.b_req_perf_lvl) {
p_dev_ctxt->n_reqd_perf_lvl -=
p_cctxt->n_reqd_perf_lvl;
p_cctxt->status.b_req_perf_lvl = FALSE;
rc = vcd_set_perf_level(p_dev_ctxt,
p_dev_ctxt->n_reqd_perf_lvl,
p_cctxt);
}
}
break;
}
case VCD_EVT_PWR_CLNT_RESUME:
case VCD_EVT_PWR_CLNT_FIRST_FRAME:
{
if (p_cctxt) {
rc = VCD_S_SUCCESS;
if (!p_cctxt->status.b_req_perf_lvl) {
p_dev_ctxt->n_reqd_perf_lvl +=
p_cctxt->n_reqd_perf_lvl;
p_cctxt->status.b_req_perf_lvl = TRUE;
rc = vcd_set_perf_level(p_dev_ctxt,
p_dev_ctxt->n_reqd_perf_lvl,
p_cctxt);
}
}
break;
}
}
return rc;
}
u32 vcd_device_power_event(struct vcd_dev_ctxt_type *p_dev_ctxt, u32 event,
struct vcd_clnt_ctxt_type_t *p_cctxt)
{
u32 rc = VCD_ERR_FAIL;
u32 n_set_perf_lvl;
switch (event) {
case VCD_EVT_PWR_DEV_INIT_BEGIN:
{
if (p_dev_ctxt->e_pwr_clk_state ==
VCD_PWRCLK_STATE_OFF) {
if (res_trk_get_max_perf_level(&p_dev_ctxt->
n_max_perf_lvl)) {
if (res_trk_power_up()) {
p_dev_ctxt->e_pwr_clk_state =
VCD_PWRCLK_STATE_ON_NOTCLOCKED;
p_dev_ctxt->n_curr_perf_lvl = 0;
p_dev_ctxt->n_reqd_perf_lvl = 0;
p_dev_ctxt->n_active_clnts = 0;
p_dev_ctxt->
b_set_perf_lvl_pending = FALSE;
rc = vcd_enable_clock(p_dev_ctxt,
p_cctxt);
if (VCD_FAILED(rc)) {
(void)res_trk_power_down();
p_dev_ctxt->e_pwr_clk_state =
VCD_PWRCLK_STATE_OFF;
}
}
}
}
break;
}
case VCD_EVT_PWR_DEV_INIT_END:
case VCD_EVT_PWR_DEV_TERM_FAIL:
case VCD_EVT_PWR_DEV_SLEEP_BEGIN:
case VCD_EVT_PWR_DEV_HWTIMEOUT:
{
rc = vcd_gate_clock(p_dev_ctxt);
break;
}
case VCD_EVT_PWR_DEV_INIT_FAIL:
case VCD_EVT_PWR_DEV_TERM_END:
{
if (p_dev_ctxt->e_pwr_clk_state !=
VCD_PWRCLK_STATE_OFF) {
(void)vcd_disable_clock(p_dev_ctxt);
(void)res_trk_power_down();
p_dev_ctxt->e_pwr_clk_state =
VCD_PWRCLK_STATE_OFF;
p_dev_ctxt->n_curr_perf_lvl = 0;
p_dev_ctxt->n_reqd_perf_lvl = 0;
p_dev_ctxt->n_active_clnts = 0;
p_dev_ctxt->b_set_perf_lvl_pending = FALSE;
rc = VCD_S_SUCCESS;
}
break;
}
case VCD_EVT_PWR_DEV_TERM_BEGIN:
case VCD_EVT_PWR_DEV_SLEEP_END:
{
rc = vcd_un_gate_clock(p_dev_ctxt);
break;
}
case VCD_EVT_PWR_DEV_SET_PERFLVL:
{
n_set_perf_lvl =
p_dev_ctxt->n_reqd_perf_lvl >
0 ? p_dev_ctxt->
n_reqd_perf_lvl : VCD_MIN_PERF_LEVEL;
rc = vcd_set_perf_level(p_dev_ctxt, n_set_perf_lvl,
p_cctxt);
break;
}
}
return rc;
}
