void uart_init(INT8U uart_num)
{
UART_SFR* pUart = get_UART_SFR_base(uart_num);
// 8 bits, 1 stop bit, no parity check, RX disabled
pUart->CTRL= (C_UART_CTRL_UART_ENABLE | C_UART_CTRL_WORD_8BIT);
#ifdef UART_PIN_POS
#if UART_PIN_POS == UART_TX_IOH2__RX_IOH3
R_GPIOCTRL = 0; /*switch off ice*/
R_FUNPOS0 |= 1;
#else
R_FUNPOS0 &= ~(1);
#endif
#endif
#if _OPERATING_SYSTEM == 1
if(sw_uart_sem[uart_num] == NULL)
{
sw_uart_sem[uart_num] = OSSemCreate(1);
}
#endif
#if _OPERATING_SYSTEM != _OS_NONE // Soft Protect for critical section
sw_uart_lock(uart_num);
#endif
uart_tx_on[uart_num] = 0; // TX is disabled by software
#if _OPERATING_SYSTEM != _OS_NONE
sw_uart_unlock(uart_num);
#endif
uart_sw_fifo_init(uart_num);
vic_irq_register(VIC_UART, uart_isr); // Non vector interrupt register
vic_irq_enable(VIC_UART);
//uart_set_to_int(uart_num,UART_ENABLE); /* enable rx timeout interrupt */
}
void matre_scaninit(void)
{
KS_finish_Flag = 0;
KS_Number = 0;
KS_DATA = 0;
//R_IOA_DIR = 0x00ff;
//R_IOA_ATTRIB = 0x00ff;
//R_IOA_BUFFER = 0x00ff;
R_TIMERD_PRELOAD = 0x10000-(48000000/256/60);
R_TIMERD_CTRL = 0xa062;
vic_irq_register(VIC_KEY_SCAN, keyscan_isr1);
vic_irq_enable(VIC_KEY_SCAN);
R_KEYSCAN_CTRL0 = C_KS_INT_Status | C_KS_INT_Enable | C_KS_AUTO |C_KS_SMART| C_KS_STIME_128 | C_KS_TSEL_TimerD;
R_KEYSCAN_CTRL0 = C_KS_Key_Status|C_KS_Velocity_Enable|C_KS_64Key_Enable;
}
void drvl1_csi_init(void)
{
R_CSI_TG_CTRL0 = C_CSI_CTRL1_DEDICATE_IRQ | C_CSI_CTRL1_OUT_YUV | C_CSI_CTRL1_IN_YUV | C_CSI_CTRL1_CAP;
R_CSI_TG_CTRL1 = C_CSI_CTRL2_HIGH_PRIORITY | C_CSI_CTRL2_NON_STOP;
R_CSI_SEN_CTRL = 0x0;
R_CSI_TG_HLSTART = 0x0; // Horizontal latch start
R_CSI_TG_VL0START = 0x0; // Field 0 vertical latch start
R_CSI_TG_VL1START = 0x0; // Field 1 vertical latch start
R_CSI_TG_HWIDTH = 640; // Sensor width
R_CSI_TG_VHEIGHT = 480; // Sensor height
R_CSI_TG_HRATIO = 0x0; // Horizontal compress ratio control
R_CSI_TG_VRATIO = 0x0; // Vertical compress ratio control
*P_CSI_TG_FBSADDR = C_CSI_DRV_DUMMY_BUFFER; // Frame buffer start address(FIFO frame buffer A when FIFO mode is used)
*P_CSI_TG_FBSADDR_B = C_CSI_DRV_DUMMY_BUFFER; // FIFO frame buffer B when FIFO mode is used
R_TGR_IRQ_EN = 0x0; // Disable IRQ
R_TGR_IRQ_STATUS = R_TGR_IRQ_STATUS; // Clear IRQ status
// Set black screen region
R_CSI_TG_HSTART = 0x0; // Black screen horizontal start
R_CSI_TG_HEND = 0xFFF; // Black screen horizontal end
R_CSI_TG_VSTART = 0x0; // Black screen vertical start
R_CSI_TG_VEND = 0xFFF; // Black screen vertical end
*P_CSI_MD_FBADDR = C_CSI_DRV_DUMMY_BUFFER;
R_CSI_MD_CTRL = 0x0;
for (buf_write=0; buf_write<C_CSI_DRV_MAX_FRAME_NUM; buf_write++) {
free_queue_buffer[buf_write] = C_CSI_DRV_DUMMY_BUFFER;
}
buf_read = buf_write = 0;
vic_irq_register(VIC_CSI, csi_isr);
vic_irq_enable(VIC_CSI);
}
