/*
* We are going ot alloc a page during init per window for small transfers.
* Small transfers will go VME -> buffer -> user space. Larger (more than a
* page) transfers will lock the user space buffer into memory and then
* transfer the data directly into the user space buffers.
*/
static ssize_t resource_to_user(int minor, char __user *buf, size_t count,
loff_t *ppos)
{
ssize_t retval;
ssize_t copied = 0;
if (count <= image[minor].size_buf) {
/* We copy to kernel buffer */
copied = vme_master_read(image[minor].resource,
image[minor].kern_buf, count, *ppos);
if (copied < 0) {
return (int)copied;
}
retval = __copy_to_user(buf, image[minor].kern_buf,
(unsigned long)copied);
if (retval != 0) {
copied = (copied - retval);
printk("User copy failed\n");
return -EINVAL;
}
} else {
/* XXX Need to write this */
printk("Currently don't support large transfers\n");
/* Map in pages from userspace */
/* Call vme_master_read to do the transfer */
return -EINVAL;
}
return copied;
}
static void pio2_int(int level, int vector, void *ptr)
{
int vec, i, channel, retval;
u8 reg;
struct pio2_card *card = ptr;
vec = vector & ~PIO2_VME_VECTOR_MASK;
switch (vec) {
case 0:
dev_warn(&card->vdev->dev, "Spurious Interrupt\n");
break;
case 1:
case 2:
case 3:
case 4:
/* Channels 0 to 7 */
retval = vme_master_read(card->window, ®, 1,
PIO2_REGS_INT_STAT[vec - 1]);
if (retval < 0) {
dev_err(&card->vdev->dev,
"Unable to read IRQ status register\n");
return;
}
for (i = 0; i < 8; i++) {
channel = ((vec - 1) * 8) + i;
if (reg & PIO2_CHANNEL_BIT[channel])
dev_info(&card->vdev->dev,
"Interrupt on I/O channel %d\n",
channel);
}
break;
case 5:
case 6:
case 7:
case 8:
case 9:
case 10:
/* Counters are dealt with by their own handler */
dev_err(&card->vdev->dev,
"Counter interrupt\n");
break;
}
}
/*
* We return whether this has been successful - this is used in the probe to
* ensure we have a valid card.
*/
int pio2_gpio_reset(struct pio2_card *card)
{
int retval = 0;
int i, j;
u8 data = 0;
/* Zero output registers */
for (i = 0; i < 4; i++) {
retval = vme_master_write(card->window, &data, 1,
PIO2_REGS_DATA[i]);
if (retval < 0)
return retval;
card->bank[i].value = 0;
}
/* Set input interrupt masks */
for (i = 0; i < 4; i++) {
retval = vme_master_write(card->window, &data, 1,
PIO2_REGS_INT_MASK[i * 2]);
if (retval < 0)
return retval;
retval = vme_master_write(card->window, &data, 1,
PIO2_REGS_INT_MASK[(i * 2) + 1]);
if (retval < 0)
return retval;
for (j = 0; j < 8; j++)
card->bank[i].irq[j] = NONE;
}
/* Ensure all I/O interrupts are cleared */
for (i = 0; i < 4; i++) {
do {
retval = vme_master_read(card->window, &data, 1,
PIO2_REGS_INT_STAT[i]);
if (retval < 0)
return retval;
} while (data != 0);
}
return 0;
}
static int pio2_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
u8 reg;
int retval;
struct pio2_card *card = gpio_to_pio2_card(chip);
if ((card->bank[PIO2_CHANNEL_BANK[offset]].config == OUTPUT) |
(card->bank[PIO2_CHANNEL_BANK[offset]].config == NOFIT)) {
dev_err(&card->vdev->dev, "Channel not available as input\n");
return 0;
}
retval = vme_master_read(card->window, ®, 1,
PIO2_REGS_DATA[PIO2_CHANNEL_BANK[offset]]);
if (retval < 0) {
dev_err(&card->vdev->dev, "Unable to read from GPIO\n");
return 0;
}
/*
* Remember, input on channels configured as both input and output
* are inverted!
*/
if (reg & PIO2_CHANNEL_BIT[offset]) {
if (card->bank[PIO2_CHANNEL_BANK[offset]].config != BOTH)
return 0;
else
return 1;
} else {
if (card->bank[PIO2_CHANNEL_BANK[offset]].config != BOTH)
return 1;
else
return 0;
}
}
static int __devinit pio2_probe(struct vme_dev *vdev)
{
struct pio2_card *card;
int retval;
int i;
u8 reg;
int vec;
card = kzalloc(sizeof(struct pio2_card), GFP_KERNEL);
if (card == NULL) {
dev_err(&vdev->dev, "Unable to allocate card structure\n");
retval = -ENOMEM;
goto err_struct;
}
card->id = vdev->num;
card->bus = bus[card->id];
card->base = base[card->id];
card->irq_vector = vector[card->id];
card->irq_level = level[card->id] & PIO2_VME_INT_MASK;
strncpy(card->variant, variant[card->id], PIO2_VARIANT_LENGTH);
card->vdev = vdev;
for (i = 0; i < PIO2_VARIANT_LENGTH; i++) {
if (isdigit(card->variant[i]) == 0) {
dev_err(&card->vdev->dev, "Variant invalid\n");
retval = -EINVAL;
goto err_variant;
}
}
/*
* Bottom 4 bits of VME interrupt vector used to determine source,
* provided vector should only use upper 4 bits.
*/
if (card->irq_vector & ~PIO2_VME_VECTOR_MASK) {
dev_err(&card->vdev->dev,
"Invalid VME IRQ Vector, vector must not use lower 4 bits\n");
retval = -EINVAL;
goto err_vector;
}
/*
* There is no way to determine the build variant or whether each bank
* is input, output or both at run time. The inputs are also inverted
* if configured as both.
*
* We pass in the board variant and use that to determine the
* configuration of the banks.
*/
for (i = 1; i < PIO2_VARIANT_LENGTH; i++) {
switch (card->variant[i]) {
case '0':
card->bank[i-1].config = NOFIT;
break;
case '1':
case '2':
case '3':
case '4':
card->bank[i-1].config = INPUT;
break;
case '5':
card->bank[i-1].config = OUTPUT;
break;
case '6':
case '7':
case '8':
case '9':
card->bank[i-1].config = BOTH;
break;
}
}
/* Get a master window and position over regs */
card->window = vme_master_request(vdev, VME_A24, VME_SCT, VME_D16);
if (card->window == NULL) {
dev_err(&card->vdev->dev,
"Unable to assign VME master resource\n");
retval = -EIO;
goto err_window;
}
retval = vme_master_set(card->window, 1, card->base, 0x10000, VME_A24,
(VME_SCT | VME_USER | VME_DATA), VME_D16);
if (retval) {
dev_err(&card->vdev->dev,
"Unable to configure VME master resource\n");
goto err_set;
}
/*
* There is also no obvious register which we can probe to determine
* whether the provided base is valid. If we can read the "ID Register"
* offset and the reset function doesn't error, assume we have a valid
* location.
*/
retval = vme_master_read(card->window, ®, 1, PIO2_REGS_ID);
if (retval < 0) {
dev_err(&card->vdev->dev, "Unable to read from device\n");
goto err_read;
}
dev_dbg(&card->vdev->dev, "ID Register:%x\n", reg);
/*
* Ensure all the I/O is cleared. We can't read back the states, so
* this is the only method we have to ensure that the I/O is in a known
* state.
*/
retval = pio2_reset_card(card);
if (retval) {
dev_err(&card->vdev->dev,
"Failed to reset card, is location valid?");
retval = -ENODEV;
goto err_reset;
}
/* Configure VME Interrupts */
reg = card->irq_level;
if (pio2_get_led(card))
reg |= PIO2_LED;
if (loopback)
reg |= PIO2_LOOP;
retval = vme_master_write(card->window, ®, 1, PIO2_REGS_CTRL);
if (retval < 0)
return retval;
/* Set VME vector */
retval = vme_master_write(card->window, &card->irq_vector, 1,
PIO2_REGS_VME_VECTOR);
if (retval < 0)
return retval;
/* Attach spurious interrupt handler. */
vec = card->irq_vector | PIO2_VME_VECTOR_SPUR;
retval = vme_irq_request(vdev, card->irq_level, vec,
&pio2_int, (void *)card);
if (retval < 0) {
dev_err(&card->vdev->dev,
"Unable to attach VME interrupt vector0x%x, level 0x%x\n",
vec, card->irq_level);
goto err_irq;
}
/* Attach GPIO interrupt handlers. */
for (i = 0; i < 4; i++) {
vec = card->irq_vector | PIO2_VECTOR_BANK[i];
retval = vme_irq_request(vdev, card->irq_level, vec,
&pio2_int, (void *)card);
if (retval < 0) {
dev_err(&card->vdev->dev,
"Unable to attach VME interrupt vector0x%x, level 0x%x\n",
vec, card->irq_level);
goto err_gpio_irq;
}
}
/* Attach counter interrupt handlers. */
for (i = 0; i < 6; i++) {
vec = card->irq_vector | PIO2_VECTOR_CNTR[i];
retval = vme_irq_request(vdev, card->irq_level, vec,
&pio2_int, (void *)card);
if (retval < 0) {
dev_err(&card->vdev->dev,
"Unable to attach VME interrupt vector0x%x, level 0x%x\n",
vec, card->irq_level);
goto err_cntr_irq;
}
}
/* Register IO */
retval = pio2_gpio_init(card);
if (retval < 0) {
dev_err(&card->vdev->dev,
"Unable to register with GPIO framework\n");
goto err_gpio;
}
/* Set LED - This also sets interrupt level */
retval = pio2_set_led(card, 0);
if (retval < 0) {
dev_err(&card->vdev->dev, "Unable to set LED\n");
goto err_led;
}
dev_set_drvdata(&card->vdev->dev, card);
dev_info(&card->vdev->dev,
"PIO2 (variant %s) configured at 0x%lx\n", card->variant,
card->base);
return 0;
err_led:
pio2_gpio_exit(card);
err_gpio:
i = 6;
err_cntr_irq:
while (i > 0) {
i--;
vec = card->irq_vector | PIO2_VECTOR_CNTR[i];
vme_irq_free(vdev, card->irq_level, vec);
}
i = 4;
err_gpio_irq:
while (i > 0) {
i--;
vec = card->irq_vector | PIO2_VECTOR_BANK[i];
vme_irq_free(vdev, card->irq_level, vec);
}
vec = (card->irq_vector & PIO2_VME_VECTOR_MASK) | PIO2_VME_VECTOR_SPUR;
vme_irq_free(vdev, card->irq_level, vec);
err_irq:
pio2_reset_card(card);
err_reset:
err_read:
vme_master_set(card->window, 0, 0, 0, VME_A16, 0, VME_D16);
err_set:
vme_master_free(card->window);
err_window:
err_vector:
err_variant:
kfree(card);
err_struct:
return retval;
}
