void msm_send_frame_to_vpe(uint32_t pyaddr, uint32_t pcbcraddr,
struct timespec *ts)
{
uint32_t temp_pyaddr, temp_pcbcraddr;
CDBG("vpe input, pyaddr = 0x%x, pcbcraddr = 0x%x\n",
pyaddr, pcbcraddr);
msm_io_w(pyaddr, vpe_device->vpebase + VPE_SRCP0_ADDR_OFFSET);
msm_io_w(pcbcraddr, vpe_device->vpebase + VPE_SRCP1_ADDR_OFFSET);
if (vpe_ctrl->state == 1)
CDBG(" =====VPE is busy!!! Wrong!========\n");
else
vpe_ctrl->ts = *ts;
if (vpe_ctrl->dis_en) {
/* Changing the VPE output CBCR address,
to make Y/CBCR continuous */
vpe_ctrl->pcbcr_before_dis = msm_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
temp_pyaddr = msm_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
temp_pcbcraddr = temp_pyaddr + vpe_ctrl->pcbcr_dis_offset;
msm_io_w(temp_pcbcraddr, vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
}
vpe_ctrl->state = 1;
vpe_start();
}
static int msm_send_frame_to_vpe(void)
{
int rc = 0;
unsigned long flags;
spin_lock_irqsave(&vpe_ctrl->lock, flags);
msm_io_w((vpe_ctrl->pp_frame_info->src_frame.sp.phy_addr +
vpe_ctrl->pp_frame_info->src_frame.sp.y_off),
vpe_ctrl->vpebase + VPE_SRCP0_ADDR_OFFSET);
msm_io_w((vpe_ctrl->pp_frame_info->src_frame.sp.phy_addr +
vpe_ctrl->pp_frame_info->src_frame.sp.cbcr_off),
vpe_ctrl->vpebase + VPE_SRCP1_ADDR_OFFSET);
msm_io_w((vpe_ctrl->pp_frame_info->dest_frame.sp.phy_addr +
vpe_ctrl->pp_frame_info->dest_frame.sp.y_off),
vpe_ctrl->vpebase + VPE_OUTP0_ADDR_OFFSET);
msm_io_w((vpe_ctrl->pp_frame_info->dest_frame.sp.phy_addr +
vpe_ctrl->pp_frame_info->dest_frame.sp.cbcr_off),
vpe_ctrl->vpebase + VPE_OUTP1_ADDR_OFFSET);
vpe_ctrl->state = VPE_STATE_ACTIVE;
//HTC_START chris, 20120310 fix unknown reset which is caused by vpe clk disabled when vpe state is active.
vpe_ctrl->vpe_event_done = 0;
//HTC_END
spin_unlock_irqrestore(&vpe_ctrl->lock, flags);
vpe_start();
return rc;
}
void msm_send_frame_to_vpe(uint32_t pyaddr, uint32_t pcbcraddr,
struct timespec *ts, int output_type)
{
uint32_t temp_pyaddr = 0, temp_pcbcraddr = 0;
CDBG("[CAM] vpe input, pyaddr = 0x%x, pcbcraddr = 0x%x\n",
pyaddr, pcbcraddr);
msm_io_w(pyaddr, vpe_device->vpebase + VPE_SRCP0_ADDR_OFFSET);
msm_io_w(pcbcraddr, vpe_device->vpebase + VPE_SRCP1_ADDR_OFFSET);
if (vpe_ctrl->state == 1)
pr_err("[CAM] =====VPE is busy!!! Wrong!========\n");
if (output_type != OUTPUT_TYPE_ST_R)
vpe_ctrl->ts = *ts;
if (output_type == OUTPUT_TYPE_ST_L) {
vpe_ctrl->pcbcr_before_dis = msm_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
temp_pyaddr = msm_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
if (vpe_ctrl->frame_pack == TOP_DOWN_FULL)
temp_pcbcraddr = temp_pyaddr + (vpe_ctrl->out_w * vpe_ctrl->out_h * 2);
else if ((vpe_ctrl->frame_pack == SIDE_BY_SIDE_HALF) ||
(vpe_ctrl->frame_pack == SIDE_BY_SIDE_FULL))
temp_pcbcraddr = temp_pyaddr +
PAD_TO_2K((vpe_ctrl->out_w * 2) * vpe_ctrl->out_h,
vpe_ctrl->pad_2k_bool);
else
CDBG("[CAM] %s: Invalid Frame Packing = %d\n", __func__,
vpe_ctrl->frame_pack);
msm_io_w(temp_pcbcraddr, vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
}
if (vpe_ctrl->dis_en) {
/* Changing the VPE output CBCR address,
to make Y/CBCR continuous */
vpe_ctrl->pcbcr_before_dis = msm_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
temp_pyaddr = msm_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
temp_pcbcraddr = temp_pyaddr + vpe_ctrl->pcbcr_dis_offset;
msm_io_w(temp_pcbcraddr, vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
}
vpe_ctrl->output_type = output_type;
vpe_ctrl->state = 1;
vpe_start();
}
void msm_send_frame_to_vpe(uint32_t p0_phy_add, uint32_t p1_phy_add,
struct timespec *ts, int output_type)
{
uint32_t temp_pyaddr = 0, temp_pcbcraddr = 0;
CDBG("vpe input, p0_phy_add = 0x%x, p1_phy_add = 0x%x\n",
p0_phy_add, p1_phy_add);
msm_camera_io_w(p0_phy_add,
vpe_device->vpebase + VPE_SRCP0_ADDR_OFFSET);
msm_camera_io_w(p1_phy_add,
vpe_device->vpebase + VPE_SRCP1_ADDR_OFFSET);
if (vpe_ctrl->state == VPE_STATE_ACTIVE)
CDBG(" =====VPE is busy!!! Wrong!========\n");
if (output_type != OUTPUT_TYPE_ST_R)
vpe_ctrl->ts = *ts;
if (output_type == OUTPUT_TYPE_ST_L) {
vpe_ctrl->pcbcr_before_dis =
msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
temp_pyaddr = msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
temp_pcbcraddr = temp_pyaddr + PAD_TO_2K(vpe_ctrl->out_w *
vpe_ctrl->out_h * 2, vpe_ctrl->pad_2k_bool);
msm_camera_io_w(temp_pcbcraddr, vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
}
if (vpe_ctrl->dis_en) {
/* Changing the VPE output CBCR address,
to make Y/CBCR continuous */
vpe_ctrl->pcbcr_before_dis =
msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
temp_pyaddr = msm_camera_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
temp_pcbcraddr = temp_pyaddr + vpe_ctrl->pcbcr_dis_offset;
msm_camera_io_w(temp_pcbcraddr, vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
}
vpe_ctrl->output_type = output_type;
vpe_ctrl->state = VPE_STATE_ACTIVE;
vpe_start();
}
static int msm_send_frame_to_vpe(void)
{
int rc = 0;
unsigned long flags;
unsigned long srcP0, srcP1, outP0, outP1;
struct msm_mctl_pp_frame_info *frame_info = vpe_ctrl->pp_frame_info;
if (!frame_info) {
pr_err("%s Invalid frame", __func__);
return -EINVAL;
}
spin_lock_irqsave(&vpe_ctrl->lock, flags);
if (frame_info->src_frame.frame.num_planes > 1) {
srcP0 = frame_info->src_frame.map[0].paddr +
frame_info->src_frame.map[0].data_offset;
srcP1 = frame_info->src_frame.map[1].paddr +
frame_info->src_frame.map[1].data_offset;
outP0 = frame_info->dest_frame.map[0].paddr +
frame_info->dest_frame.map[0].data_offset;
outP1 = frame_info->dest_frame.map[1].paddr +
frame_info->dest_frame.map[1].data_offset;
} else {
srcP0 = frame_info->src_frame.map[0].paddr;
srcP1 = frame_info->src_frame.map[0].paddr +
frame_info->src_frame.map[0].data_offset;
outP0 = frame_info->dest_frame.map[0].paddr;
outP1 = frame_info->dest_frame.map[0].paddr +
frame_info->dest_frame.map[0].data_offset;
}
D("%s VPE Configured with Src %x, %x Dest %x, %x",
__func__, (uint32_t)srcP0, (uint32_t)srcP1,
(uint32_t)outP0, (uint32_t)outP1);
msm_camera_io_w(srcP0, vpe_ctrl->vpebase + VPE_SRCP0_ADDR_OFFSET);
msm_camera_io_w(srcP1, vpe_ctrl->vpebase + VPE_SRCP1_ADDR_OFFSET);
msm_camera_io_w(outP0, vpe_ctrl->vpebase + VPE_OUTP0_ADDR_OFFSET);
msm_camera_io_w(outP1, vpe_ctrl->vpebase + VPE_OUTP1_ADDR_OFFSET);
vpe_ctrl->state = VPE_STATE_ACTIVE;
spin_unlock_irqrestore(&vpe_ctrl->lock, flags);
vpe_start();
return rc;
}
static int msm_send_frame_to_vpe(void)
{
int rc = 0;
unsigned long flags;
unsigned long srcP0, srcP1, outP0, outP1;
struct msm_mctl_pp_frame_info *frame = vpe_ctrl->pp_frame_info;
spin_lock_irqsave(&vpe_ctrl->lock, flags);
if (frame->src_frame.num_planes > 1) {
srcP0 = vpe_ctrl->pp_frame_info->src_frame.mp[0].phy_addr +
vpe_ctrl->pp_frame_info->src_frame.mp[0].data_offset;
srcP1 = vpe_ctrl->pp_frame_info->src_frame.mp[1].phy_addr +
vpe_ctrl->pp_frame_info->src_frame.mp[1].data_offset;
outP0 = vpe_ctrl->pp_frame_info->dest_frame.mp[0].phy_addr +
vpe_ctrl->pp_frame_info->dest_frame.mp[0].data_offset;
outP1 = vpe_ctrl->pp_frame_info->dest_frame.mp[1].phy_addr +
vpe_ctrl->pp_frame_info->dest_frame.mp[1].data_offset;
} else {
srcP0 = vpe_ctrl->pp_frame_info->src_frame.sp.phy_addr +
vpe_ctrl->pp_frame_info->src_frame.sp.y_off;
srcP1 = vpe_ctrl->pp_frame_info->src_frame.sp.phy_addr +
vpe_ctrl->pp_frame_info->src_frame.sp.cbcr_off;
outP0 = vpe_ctrl->pp_frame_info->dest_frame.sp.phy_addr +
vpe_ctrl->pp_frame_info->dest_frame.sp.y_off;
outP1 = vpe_ctrl->pp_frame_info->dest_frame.sp.phy_addr +
vpe_ctrl->pp_frame_info->dest_frame.sp.cbcr_off;
}
msm_camera_io_w(srcP0, vpe_ctrl->vpebase + VPE_SRCP0_ADDR_OFFSET);
msm_camera_io_w(srcP1, vpe_ctrl->vpebase + VPE_SRCP1_ADDR_OFFSET);
msm_camera_io_w(outP0, vpe_ctrl->vpebase + VPE_OUTP0_ADDR_OFFSET);
msm_camera_io_w(outP1, vpe_ctrl->vpebase + VPE_OUTP1_ADDR_OFFSET);
vpe_ctrl->state = VPE_STATE_ACTIVE;
spin_unlock_irqrestore(&vpe_ctrl->lock, flags);
vpe_start();
return rc;
}
static int msm_send_frame_to_vpe(void)
{
int rc = 0;
unsigned long flags;
spin_lock_irqsave(&vpe_ctrl->lock, flags);
msm_io_w((vpe_ctrl->pp_frame_info->src_frame.sp.phy_addr +
vpe_ctrl->pp_frame_info->src_frame.sp.y_off),
vpe_ctrl->vpebase + VPE_SRCP0_ADDR_OFFSET);
msm_io_w((vpe_ctrl->pp_frame_info->src_frame.sp.phy_addr +
vpe_ctrl->pp_frame_info->src_frame.sp.cbcr_off),
vpe_ctrl->vpebase + VPE_SRCP1_ADDR_OFFSET);
msm_io_w((vpe_ctrl->pp_frame_info->dest_frame.sp.phy_addr +
vpe_ctrl->pp_frame_info->dest_frame.sp.y_off),
vpe_ctrl->vpebase + VPE_OUTP0_ADDR_OFFSET);
msm_io_w((vpe_ctrl->pp_frame_info->dest_frame.sp.phy_addr +
vpe_ctrl->pp_frame_info->dest_frame.sp.cbcr_off),
vpe_ctrl->vpebase + VPE_OUTP1_ADDR_OFFSET);
vpe_ctrl->state = VPE_STATE_ACTIVE;
spin_unlock_irqrestore(&vpe_ctrl->lock, flags);
vpe_start();
return rc;
}
static int vpe_proc_general(struct msm_vpe_cmd *cmd)
{
int rc = 0;
uint32_t *cmdp = NULL;
struct msm_queue_cmd *qcmd = NULL;
struct msm_vpe_buf_info *vpe_buf;
int turbo_mode = 0;
struct msm_sync *sync = (struct msm_sync *)vpe_ctrl->syncdata;
CDBG("vpe_proc_general: cmdID = %s, length = %d\n",
vpe_general_cmd[cmd->id], cmd->length);
switch (cmd->id) {
case VPE_ENABLE:
cmdp = kmalloc(cmd->length, GFP_ATOMIC);
if (!cmdp) {
rc = -ENOMEM;
goto vpe_proc_general_done;
}
if (copy_from_user(cmdp,
(void __user *)(cmd->value),
cmd->length)) {
rc = -EFAULT;
goto vpe_proc_general_done;
}
turbo_mode = *((int *)(cmd->value));
rc = turbo_mode ? vpe_enable(VPE_TURBO_MODE_CLOCK_RATE)
: vpe_enable(VPE_NORMAL_MODE_CLOCK_RATE);
break;
case VPE_DISABLE:
rc = vpe_disable();
break;
case VPE_RESET:
case VPE_ABORT:
rc = vpe_reset();
break;
case VPE_START:
rc = vpe_start();
break;
case VPE_INPUT_PLANE_CFG:
cmdp = kmalloc(cmd->length, GFP_ATOMIC);
if (!cmdp) {
rc = -ENOMEM;
goto vpe_proc_general_done;
}
if (copy_from_user(cmdp,
(void __user *)(cmd->value),
cmd->length)) {
rc = -EFAULT;
goto vpe_proc_general_done;
}
vpe_input_plane_config(cmdp);
break;
case VPE_OPERATION_MODE_CFG:
CDBG("cmd->length = %d\n", cmd->length);
if (cmd->length != VPE_OPERATION_MODE_CFG_LEN_ZSL) {
rc = -EINVAL;
goto vpe_proc_general_done;
}
cmdp = kmalloc(VPE_OPERATION_MODE_CFG_LEN_ZSL,
GFP_ATOMIC);
if (copy_from_user(cmdp,
(void __user *)(cmd->value),
VPE_OPERATION_MODE_CFG_LEN_ZSL)) {
rc = -EFAULT;
goto vpe_proc_general_done;
}
rc = vpe_operation_config(cmdp);
CDBG("rc = %d \n", rc);
break;
case VPE_OUTPUT_PLANE_CFG:
cmdp = kmalloc(cmd->length, GFP_ATOMIC);
if (!cmdp) {
rc = -ENOMEM;
goto vpe_proc_general_done;
}
if (copy_from_user(cmdp,
(void __user *)(cmd->value),
cmd->length)) {
rc = -EFAULT;
goto vpe_proc_general_done;
}
vpe_output_plane_config(cmdp);
break;
case VPE_SCALE_CFG_TYPE:
cmdp = kmalloc(cmd->length, GFP_ATOMIC);
if (!cmdp) {
rc = -ENOMEM;
goto vpe_proc_general_done;
}
if (copy_from_user(cmdp,
(void __user *)(cmd->value),
cmd->length)) {
rc = -EFAULT;
goto vpe_proc_general_done;
}
vpe_update_scale_coef(cmdp);
break;
case VPE_CMD_DIS_OFFSET_CFG: {
struct msm_vfe_resp *vdata;
/* first get the dis offset and frame id. */
cmdp = kmalloc(cmd->length, GFP_ATOMIC);
if (!cmdp) {
rc = -ENOMEM;
goto vpe_proc_general_done;
}
if (copy_from_user(cmdp,
(void __user *)(cmd->value),
cmd->length)) {
rc = -EFAULT;
goto vpe_proc_general_done;
}
/* get the offset. */
vpe_ctrl->dis_offset = *(struct dis_offset_type *)cmdp;
qcmd = msm_dequeue_vpe(&sync->vpe_q, list_vpe_frame);
if (!qcmd) {
pr_err("%s: no video frame.\n", __func__);
kfree(cmdp);
return -EAGAIN;
}
vdata = (struct msm_vfe_resp *)(qcmd->command);
vpe_buf = &vdata->vpe_bf;
vpe_update_scaler_with_dis(&(vpe_buf->vpe_crop),
&(vpe_ctrl->dis_offset));
msm_send_frame_to_vpe(vpe_buf->y_phy, vpe_buf->cbcr_phy,
&(vpe_buf->ts), OUTPUT_TYPE_V);
if (!qcmd || !atomic_read(&qcmd->on_heap)) {
kfree(cmdp);
return -EAGAIN;
}
if (!atomic_sub_return(1, &qcmd->on_heap))
kfree(qcmd);
break;
}
default:
break;
}
vpe_proc_general_done:
kfree(cmdp);
return rc;
}
