static int rockchip_vpu_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct rockchip_vpu_ctx *ctx;
ctx = container_of(ctrl->handler,
struct rockchip_vpu_ctx, ctrl_handler);
vpu_debug(1, "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val);
switch (ctrl->id) {
case V4L2_CID_JPEG_COMPRESSION_QUALITY:
ctx->jpeg_quality = ctrl->val;
break;
default:
return -EINVAL;
}
return 0;
}
/*
* The hardware takes care only of ext hdr and dct partition. The software
* must take care of frame header.
*
* Buffer layout as received from hardware:
* |<--gap-->|<--ext hdr-->|<-gap->|<---dct part---
* |<-------dct part offset------->|
*
* Required buffer layout:
* |<--hdr-->|<--ext hdr-->|<---dct part---
*/
void rk3288_vpu_vp8e_assemble_bitstream(struct rk3288_vpu_ctx *ctx,
struct rk3288_vpu_buf *dst_buf)
{
size_t ext_hdr_size = dst_buf->vp8e.ext_hdr_size;
size_t dct_size = dst_buf->vp8e.dct_size;
size_t hdr_size = dst_buf->vp8e.hdr_size;
size_t dst_size;
size_t tag_size;
void *dst;
u32 *tag;
dst_size = vb2_plane_size(&dst_buf->b, 0);
dst = vb2_plane_vaddr(&dst_buf->b, 0);
tag = dst; /* To access frame tag words. */
if (WARN_ON(hdr_size + ext_hdr_size + dct_size > dst_size))
return;
if (WARN_ON(dst_buf->vp8e.dct_offset + dct_size > dst_size))
return;
vpu_debug(1, "%s: hdr_size = %u, ext_hdr_size = %u, dct_size = %u\n",
__func__, hdr_size, ext_hdr_size, dct_size);
memmove(dst + hdr_size + ext_hdr_size,
dst + dst_buf->vp8e.dct_offset, dct_size);
memcpy(dst, dst_buf->vp8e.header, hdr_size);
/* Patch frame tag at first 32-bit word of the frame. */
if (dst_buf->b.v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
tag_size = VP8_KEY_FRAME_HDR_SIZE;
tag[0] &= ~VP8_FRAME_TAG_KEY_FRAME_BIT;
} else {
tag_size = VP8_INTER_FRAME_HDR_SIZE;
tag[0] |= VP8_FRAME_TAG_KEY_FRAME_BIT;
}
tag[0] &= ~VP8_FRAME_TAG_LENGTH_MASK;
tag[0] |= (hdr_size + ext_hdr_size - tag_size)
<< VP8_FRAME_TAG_LENGTH_SHIFT;
vb2_set_plane_payload(&dst_buf->b, 0,
hdr_size + ext_hdr_size + dct_size);
}