void CamResetAllEntry(struct net_device *dev)
{
u32 ulcommand = 0;
ulcommand |= BIT31|BIT30;
write_nic_dword(dev, RWCAM, ulcommand);
}
void CAM_read_entry(struct net_device *dev, u32 iIndex)
{
u32 target_command=0;
u32 target_content=0;
u8 entry_i=0;
u32 ulStatus;
s32 i=100;
for(entry_i=0;entry_i<CAM_CONTENT_COUNT;entry_i++)
{
target_command= entry_i+CAM_CONTENT_COUNT*iIndex;
target_command= target_command | BIT31;
#if 1
while((i--)>=0)
{
ulStatus = read_nic_dword(dev, RWCAM);
if(ulStatus & BIT31){
continue;
}
else{
break;
}
}
#endif
write_nic_dword(dev, RWCAM, target_command);
RT_TRACE(COMP_SEC,"CAM_read_entry(): WRITE A0: %x \n",target_command);
target_content = read_nic_dword(dev, RCAMO);
RT_TRACE(COMP_SEC, "CAM_read_entry(): WRITE A8: %x \n",target_content);
}
printk("\n");
}
int rtl8192E_suspend(struct pci_dev *pdev, pm_message_t state)
{
struct net_device *dev = pci_get_drvdata(pdev);
struct r8192_priv *priv = rtllib_priv(dev);
u32 ulRegRead;
netdev_info(dev, "============> r8192E suspend call.\n");
del_timer_sync(&priv->gpio_polling_timer);
cancel_delayed_work(&priv->gpio_change_rf_wq);
priv->polling_timer_on = 0;
if (!netif_running(dev)) {
netdev_info(dev,
"RTL819XE:UI is open out of suspend function\n");
goto out_pci_suspend;
}
if (dev->netdev_ops->ndo_stop)
dev->netdev_ops->ndo_stop(dev);
netif_device_detach(dev);
if (!priv->rtllib->bSupportRemoteWakeUp) {
MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_INIT, true);
ulRegRead = read_nic_dword(dev, CPU_GEN);
ulRegRead |= CPU_GEN_SYSTEM_RESET;
write_nic_dword(dev, CPU_GEN, ulRegRead);
} else {
write_nic_dword(dev, WFCRC0, 0xffffffff);
write_nic_dword(dev, WFCRC1, 0xffffffff);
write_nic_dword(dev, WFCRC2, 0xffffffff);
write_nic_byte(dev, PMR, 0x5);
write_nic_byte(dev, MacBlkCtrl, 0xa);
}
out_pci_suspend:
netdev_info(dev, "WOL is %s\n", priv->rtllib->bSupportRemoteWakeUp ?
"Supported" : "Not supported");
pci_save_state(pdev);
pci_disable_device(pdev);
pci_enable_wake(pdev, pci_choose_state(pdev, state),
priv->rtllib->bSupportRemoteWakeUp ? 1 : 0);
pci_set_power_state(pdev, pci_choose_state(pdev, state));
mdelay(20);
return 0;
}
void CamPrintDbgReg(struct net_device* dev)
{
unsigned long rvalue;
unsigned char ucValue;
write_nic_dword(dev, DCAM, 0x80000000);
msleep(40);
rvalue = read_nic_dword(dev, DCAM);
RT_TRACE(COMP_SEC, " TX CAM=%8lX ",rvalue);
if((rvalue & 0x40000000) != 0x4000000)
RT_TRACE(COMP_SEC, "-->TX Key Not Found ");
msleep(20);
write_nic_dword(dev, DCAM, 0x00000000);
rvalue = read_nic_dword(dev, DCAM);
RT_TRACE(COMP_SEC, "RX CAM=%8lX ",rvalue);
if((rvalue & 0x40000000) != 0x4000000)
RT_TRACE(COMP_SEC, "-->CAM Key Not Found ");
ucValue = read_nic_byte(dev, SECR);
RT_TRACE(COMP_SEC, "WPA_Config=%x \n",ucValue);
}
void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel)
{
u32 TxAGC=0;
struct r8192_priv *priv = ieee80211_priv(dev);
#ifdef RTL8190P
u8 byte0, byte1;
TxAGC |= ((powerlevel<<8)|powerlevel);
TxAGC += priv->CCKTxPowerLevelOriginalOffset;
if(priv->bDynamicTxLowPower == true //cosa 04282008 for cck long range
/*pMgntInfo->bScanInProgress == TRUE*/ ) //cosa 05/22/2008 for scan
{
if(priv->CustomerID == RT_CID_819x_Netcore)
TxAGC = 0x2222;
else
TxAGC += ((priv->CckPwEnl<<8)|priv->CckPwEnl);
}
byte0 = (u8)(TxAGC & 0xff);
byte1 = (u8)((TxAGC & 0xff00)>>8);
if(byte0 > 0x24)
byte0 = 0x24;
if(byte1 > 0x24)
byte1 = 0x24;
if(priv->rf_type == RF_2T4R) //Only 2T4R you have to care the Antenna Tx Power offset
{ // check antenna C over the max index 0x24
if(priv->RF_C_TxPwDiff > 0)
{
if( (byte0 + (u8)priv->RF_C_TxPwDiff) > 0x24)
byte0 = 0x24 - priv->RF_C_TxPwDiff;
if( (byte1 + (u8)priv->RF_C_TxPwDiff) > 0x24)
byte1 = 0x24 - priv->RF_C_TxPwDiff;
}
}
TxAGC = (byte1<<8) |byte0;
write_nic_dword(dev, CCK_TXAGC, TxAGC);
#else
#ifdef RTL8192E
TxAGC = powerlevel;
if(priv->bDynamicTxLowPower == true)//cosa 04282008 for cck long range
{
if(priv->CustomerID == RT_CID_819x_Netcore)
TxAGC = 0x22;
else
TxAGC += priv->CckPwEnl;
}
if(TxAGC > 0x24)
TxAGC = 0x24;
rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
#endif
#endif
}
static void MlmeDisassociateRequest(struct r8192_priv *priv, u8 *asSta,
u8 asRsn)
{
u8 i;
RemovePeerTS(priv->ieee80211, asSta);
SendDisassociation( priv->ieee80211, asSta, asRsn );
if(memcpy(priv->ieee80211->current_network.bssid,asSta,6) == NULL)
{
//ShuChen TODO: change media status.
//ShuChen TODO: What to do when disassociate.
priv->ieee80211->state = IEEE80211_NOLINK;
for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i] = 0x22;
priv->OpMode = RT_OP_MODE_NO_LINK;
{
RT_OP_MODE OpMode = priv->OpMode;
u8 btMsr = read_nic_byte(priv, MSR);
btMsr &= 0xfc;
switch(OpMode)
{
case RT_OP_MODE_INFRASTRUCTURE:
btMsr |= MSR_LINK_MANAGED;
break;
case RT_OP_MODE_IBSS:
btMsr |= MSR_LINK_ADHOC;
// led link set separate
break;
case RT_OP_MODE_AP:
btMsr |= MSR_LINK_MASTER;
break;
default:
btMsr |= MSR_LINK_NONE;
break;
}
write_nic_byte(priv, MSR, btMsr);
}
ieee80211_disassociate(priv->ieee80211);
write_nic_word(priv, BSSIDR, ((u16*)priv->ieee80211->current_network.bssid)[0]);
write_nic_dword(priv, BSSIDR+2, ((u32*)(priv->ieee80211->current_network.bssid+2))[0]);
}
}
static void MgntDisconnectAP(struct r8192_priv *priv, u8 asRsn)
{
bool bFilterOutNonAssociatedBSSID = false;
u32 RegRCR, Type;
/* If disconnect, clear RCR CBSSID bit */
bFilterOutNonAssociatedBSSID = false;
Type = bFilterOutNonAssociatedBSSID;
RegRCR = read_nic_dword(priv, RCR);
priv->ReceiveConfig = RegRCR;
if (Type == true)
RegRCR |= (RCR_CBSSID);
else if (Type == false)
RegRCR &= (~RCR_CBSSID);
write_nic_dword(priv, RCR, RegRCR);
priv->ReceiveConfig = RegRCR;
MlmeDisassociateRequest(priv, priv->ieee80211->current_network.bssid, asRsn);
priv->ieee80211->state = IEEE80211_NOLINK;
}
void rtl8225z2_rf_set_mode(struct net_device *dev)
{
struct r8180_priv *priv = ieee80211_priv(dev);
if (priv->ieee80211->mode == IEEE_A) {
write_rtl8225(dev, 0x5, 0x1865);
write_nic_dword(dev, RF_PARA, 0x10084);
write_nic_dword(dev, RF_TIMING, 0xa8008);
write_phy_ofdm(dev, 0x0, 0x0);
write_phy_ofdm(dev, 0xa, 0x6);
write_phy_ofdm(dev, 0xb, 0x99);
write_phy_ofdm(dev, 0xf, 0x20);
write_phy_ofdm(dev, 0x11, 0x7);
rtl8225z2_set_gain(dev, 4);
write_phy_ofdm(dev, 0x15, 0x40);
write_phy_ofdm(dev, 0x17, 0x40);
write_nic_dword(dev, 0x94, 0x10000000);
} else {
write_rtl8225(dev, 0x5, 0x1864);
write_nic_dword(dev, RF_PARA, 0x10044);
write_nic_dword(dev, RF_TIMING, 0xa8008);
write_phy_ofdm(dev, 0x0, 0x1);
write_phy_ofdm(dev, 0xa, 0x6);
write_phy_ofdm(dev, 0xb, 0x99);
write_phy_ofdm(dev, 0xf, 0x20);
write_phy_ofdm(dev, 0x11, 0x7);
rtl8225z2_set_gain(dev, 4);
write_phy_ofdm(dev, 0x15, 0x40);
write_phy_ofdm(dev, 0x17, 0x40);
write_nic_dword(dev, 0x94, 0x04000002);
}
}
void rtl8225z2_rf_init(struct net_device *dev)
{
struct r8180_priv *priv = ieee80211_priv(dev);
int i;
short channel = 1;
u16 brsr;
u32 data, addr;
priv->chan = channel;
rtl8225_host_pci_init(dev);
write_nic_dword(dev, RF_TIMING, 0x000a8008);
brsr = read_nic_word(dev, BRSR);
write_nic_word(dev, BRSR, 0xffff);
write_nic_dword(dev, RF_PARA, 0x100044);
rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
write_nic_byte(dev, CONFIG3, 0x44);
rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
rtl8185_rf_pins_enable(dev);
write_rtl8225(dev, 0x0, 0x2bf); mdelay(1);
write_rtl8225(dev, 0x1, 0xee0); mdelay(1);
write_rtl8225(dev, 0x2, 0x44d); mdelay(1);
write_rtl8225(dev, 0x3, 0x441); mdelay(1);
write_rtl8225(dev, 0x4, 0x8c3); mdelay(1);
write_rtl8225(dev, 0x5, 0xc72); mdelay(1);
write_rtl8225(dev, 0x6, 0xe6); mdelay(1);
write_rtl8225(dev, 0x7, rtl8225_chan[channel]); mdelay(1);
write_rtl8225(dev, 0x8, 0x3f); mdelay(1);
write_rtl8225(dev, 0x9, 0x335); mdelay(1);
write_rtl8225(dev, 0xa, 0x9d4); mdelay(1);
write_rtl8225(dev, 0xb, 0x7bb); mdelay(1);
write_rtl8225(dev, 0xc, 0x850); mdelay(1);
write_rtl8225(dev, 0xd, 0xcdf); mdelay(1);
write_rtl8225(dev, 0xe, 0x2b); mdelay(1);
write_rtl8225(dev, 0xf, 0x114);
mdelay(100);
write_rtl8225(dev, 0x0, 0x1b7);
for (i = 0; i < 95; i++) {
write_rtl8225(dev, 0x1, (u8)(i + 1));
write_rtl8225(dev, 0x2, rtl8225z2_rxgain[i]);
}
write_rtl8225(dev, 0x3, 0x80);
write_rtl8225(dev, 0x5, 0x4);
write_rtl8225(dev, 0x0, 0xb7);
write_rtl8225(dev, 0x2, 0xc4d);
/* FIXME!! rtl8187 we have to check if calibrarion
* is successful and eventually cal. again (repeat
* the two write on reg 2)
*/
data = read_rtl8225(dev, 6);
if (!(data & 0x00000080)) {
write_rtl8225(dev, 0x02, 0x0c4d);
force_pci_posting(dev); mdelay(200);
write_rtl8225(dev, 0x02, 0x044d);
force_pci_posting(dev); mdelay(100);
data = read_rtl8225(dev, 6);
if (!(data & 0x00000080))
DMESGW("RF Calibration Failed!!!!\n");
}
mdelay(200);
write_rtl8225(dev, 0x0, 0x2bf);
for (i = 0; i < 128; i++) {
data = rtl8225_agc[i];
addr = i + 0x80; /* enable writing AGC table */
write_phy_ofdm(dev, 0xb, data);
mdelay(1);
write_phy_ofdm(dev, 0xa, addr);
mdelay(1);
}
force_pci_posting(dev);
mdelay(1);
write_phy_ofdm(dev, 0x00, 0x01); mdelay(1);
write_phy_ofdm(dev, 0x01, 0x02); mdelay(1);
write_phy_ofdm(dev, 0x02, 0x62); mdelay(1);
write_phy_ofdm(dev, 0x03, 0x00); mdelay(1);
write_phy_ofdm(dev, 0x04, 0x00); mdelay(1);
write_phy_ofdm(dev, 0x05, 0x00); mdelay(1);
write_phy_ofdm(dev, 0x06, 0x40); mdelay(1);
write_phy_ofdm(dev, 0x07, 0x00); mdelay(1);
write_phy_ofdm(dev, 0x08, 0x40); mdelay(1);
write_phy_ofdm(dev, 0x09, 0xfe); mdelay(1);
write_phy_ofdm(dev, 0x0a, 0x08); mdelay(1);
write_phy_ofdm(dev, 0x0b, 0x80); mdelay(1);
write_phy_ofdm(dev, 0x0c, 0x01); mdelay(1);
write_phy_ofdm(dev, 0x0d, 0x43);
write_phy_ofdm(dev, 0x0e, 0xd3); mdelay(1);
write_phy_ofdm(dev, 0x0f, 0x38); mdelay(1);
write_phy_ofdm(dev, 0x10, 0x84); mdelay(1);
write_phy_ofdm(dev, 0x11, 0x07); mdelay(1);
write_phy_ofdm(dev, 0x12, 0x20); mdelay(1);
write_phy_ofdm(dev, 0x13, 0x20); mdelay(1);
write_phy_ofdm(dev, 0x14, 0x00); mdelay(1);
write_phy_ofdm(dev, 0x15, 0x40); mdelay(1);
write_phy_ofdm(dev, 0x16, 0x00); mdelay(1);
write_phy_ofdm(dev, 0x17, 0x40); mdelay(1);
write_phy_ofdm(dev, 0x18, 0xef); mdelay(1);
write_phy_ofdm(dev, 0x19, 0x19); mdelay(1);
write_phy_ofdm(dev, 0x1a, 0x20); mdelay(1);
write_phy_ofdm(dev, 0x1b, 0x15); mdelay(1);
write_phy_ofdm(dev, 0x1c, 0x04); mdelay(1);
write_phy_ofdm(dev, 0x1d, 0xc5); mdelay(1);
write_phy_ofdm(dev, 0x1e, 0x95); mdelay(1);
write_phy_ofdm(dev, 0x1f, 0x75); mdelay(1);
write_phy_ofdm(dev, 0x20, 0x1f); mdelay(1);
write_phy_ofdm(dev, 0x21, 0x17); mdelay(1);
write_phy_ofdm(dev, 0x22, 0x16); mdelay(1);
write_phy_ofdm(dev, 0x23, 0x80); mdelay(1); /* FIXME maybe not needed */
write_phy_ofdm(dev, 0x24, 0x46); mdelay(1);
write_phy_ofdm(dev, 0x25, 0x00); mdelay(1);
write_phy_ofdm(dev, 0x26, 0x90); mdelay(1);
write_phy_ofdm(dev, 0x27, 0x88); mdelay(1);
rtl8225z2_set_gain(dev, 4);
write_phy_cck(dev, 0x0, 0x98); mdelay(1);
write_phy_cck(dev, 0x3, 0x20); mdelay(1);
write_phy_cck(dev, 0x4, 0x7e); mdelay(1);
write_phy_cck(dev, 0x5, 0x12); mdelay(1);
write_phy_cck(dev, 0x6, 0xfc); mdelay(1);
write_phy_cck(dev, 0x7, 0x78); mdelay(1);
write_phy_cck(dev, 0x8, 0x2e); mdelay(1);
write_phy_cck(dev, 0x10, 0x93); mdelay(1);
write_phy_cck(dev, 0x11, 0x88); mdelay(1);
write_phy_cck(dev, 0x12, 0x47); mdelay(1);
write_phy_cck(dev, 0x13, 0xd0);
write_phy_cck(dev, 0x19, 0x00);
write_phy_cck(dev, 0x1a, 0xa0);
write_phy_cck(dev, 0x1b, 0x08);
write_phy_cck(dev, 0x40, 0x86); /* CCK Carrier Sense Threshold */
write_phy_cck(dev, 0x41, 0x8d); mdelay(1);
write_phy_cck(dev, 0x42, 0x15); mdelay(1);
write_phy_cck(dev, 0x43, 0x18); mdelay(1);
write_phy_cck(dev, 0x44, 0x36); mdelay(1);
write_phy_cck(dev, 0x45, 0x35); mdelay(1);
write_phy_cck(dev, 0x46, 0x2e); mdelay(1);
write_phy_cck(dev, 0x47, 0x25); mdelay(1);
write_phy_cck(dev, 0x48, 0x1c); mdelay(1);
write_phy_cck(dev, 0x49, 0x12); mdelay(1);
write_phy_cck(dev, 0x4a, 0x09); mdelay(1);
write_phy_cck(dev, 0x4b, 0x04); mdelay(1);
write_phy_cck(dev, 0x4c, 0x05); mdelay(1);
write_nic_byte(dev, 0x5b, 0x0d); mdelay(1);
rtl8225z2_SetTXPowerLevel(dev, channel);
/* RX antenna default to A */
write_phy_cck(dev, 0x11, 0x9b); mdelay(1); /* B: 0xDB */
write_phy_ofdm(dev, 0x26, 0x90); mdelay(1); /* B: 0x10 */
rtl8185_tx_antenna(dev, 0x03); /* B: 0x00 */
/* switch to high-speed 3-wire
* last digit. 2 for both cck and ofdm
*/
write_nic_dword(dev, 0x94, 0x15c00002);
rtl8185_rf_pins_enable(dev);
rtl8225_rf_set_chan(dev, priv->chan);
}
void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel)
{
struct r8192_priv *priv = ieee80211_priv(dev);
//Joseph TxPower for 8192 testing
#ifdef RTL8190P
u32 TxAGC1=0, TxAGC2=0, TxAGC2_tmp = 0;
u8 i, byteVal1[4], byteVal2[4], byteVal3[4];
if(priv->bDynamicTxHighPower == true) //Add by Jacken 2008/03/06
{
TxAGC1 |= ((powerlevel<<24)|(powerlevel<<16)|(powerlevel<<8)|powerlevel);
//for tx power track
TxAGC2_tmp = TxAGC1;
TxAGC1 += priv->MCSTxPowerLevelOriginalOffset[0];
TxAGC2 =0x03030303;
//for tx power track
TxAGC2_tmp += priv->MCSTxPowerLevelOriginalOffset[1];
}
else
{
TxAGC1 |= ((powerlevel<<24)|(powerlevel<<16)|(powerlevel<<8)|powerlevel);
TxAGC2 = TxAGC1;
TxAGC1 += priv->MCSTxPowerLevelOriginalOffset[0];
TxAGC2 += priv->MCSTxPowerLevelOriginalOffset[1];
TxAGC2_tmp = TxAGC2;
}
for(i=0; i<4; i++)
{
byteVal1[i] = (u8)( (TxAGC1 & (0xff<<(i*8))) >>(i*8) );
if(byteVal1[i] > 0x24)
byteVal1[i] = 0x24;
byteVal2[i] = (u8)( (TxAGC2 & (0xff<<(i*8))) >>(i*8) );
if(byteVal2[i] > 0x24)
byteVal2[i] = 0x24;
//for tx power track
byteVal3[i] = (u8)( (TxAGC2_tmp & (0xff<<(i*8))) >>(i*8) );
if(byteVal3[i] > 0x24)
byteVal3[i] = 0x24;
}
if(priv->rf_type == RF_2T4R) //Only 2T4R you have to care the Antenna Tx Power offset
{ // check antenna C over the max index 0x24
if(priv->RF_C_TxPwDiff > 0)
{
for(i=0; i<4; i++)
{
if( (byteVal1[i] + (u8)priv->RF_C_TxPwDiff) > 0x24)
byteVal1[i] = 0x24 - priv->RF_C_TxPwDiff;
if( (byteVal2[i] + (u8)priv->RF_C_TxPwDiff) > 0x24)
byteVal2[i] = 0x24 - priv->RF_C_TxPwDiff;
if( (byteVal3[i] + (u8)priv->RF_C_TxPwDiff) > 0x24)
byteVal3[i] = 0x24 - priv->RF_C_TxPwDiff;
}
}
}
TxAGC1 = (byteVal1[3]<<24) | (byteVal1[2]<<16) |(byteVal1[1]<<8) |byteVal1[0];
TxAGC2 = (byteVal2[3]<<24) | (byteVal2[2]<<16) |(byteVal2[1]<<8) |byteVal2[0];
//for tx power track
TxAGC2_tmp = (byteVal3[3]<<24) | (byteVal3[2]<<16) |(byteVal3[1]<<8) |byteVal3[0];
priv->Pwr_Track = TxAGC2_tmp;
//DbgPrint("TxAGC2_tmp = 0x%x\n", TxAGC2_tmp);
//DbgPrint("TxAGC1/TxAGC2 = 0x%x/0x%x\n", TxAGC1, TxAGC2);
write_nic_dword(dev, MCS_TXAGC, TxAGC1);
write_nic_dword(dev, MCS_TXAGC+4, TxAGC2);
#else
#ifdef RTL8192E
u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
u8 index = 0;
u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
u8 byte0, byte1, byte2, byte3;
powerBase0 = powerlevel + priv->LegacyHTTxPowerDiff; //OFDM rates
powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
powerBase1 = powerlevel; //MCS rates
powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
for(index=0; index<6; index++)
{
writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1);
byte0 = (u8)(writeVal & 0x7f);
byte1 = (u8)((writeVal & 0x7f00)>>8);
byte2 = (u8)((writeVal & 0x7f0000)>>16);
byte3 = (u8)((writeVal & 0x7f000000)>>24);
if(byte0 > 0x24) // Max power index = 0x24
byte0 = 0x24;
if(byte1 > 0x24)
byte1 = 0x24;
if(byte2 > 0x24)
byte2 = 0x24;
if(byte3 > 0x24)
byte3 = 0x24;
if(index == 3)
{
writeVal_tmp = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0;
priv->Pwr_Track = writeVal_tmp;
}
if(priv->bDynamicTxHighPower == true) //Add by Jacken 2008/03/06 //when DM implement, add this
{
writeVal = 0x03030303;
}
else
{
writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0;
}
rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
}
#endif
#endif
}
void rtl8225_rf_init(struct net_device *dev)
{
struct r8180_priv *priv = ieee80211_priv(dev);
int i;
short channel = 1;
u16 brsr;
priv->chan = channel;
rtl8180_set_anaparam(dev, RTL8225_ANAPARAM_ON);
if(priv->card_type == USB)
rtl8225_host_usb_init(dev);
else
rtl8225_host_pci_init(dev);
write_nic_dword(dev, RF_TIMING, 0x000a8008);
brsr = read_nic_word(dev, BRSR);
write_nic_word(dev, BRSR, 0xffff);
#if 0
if(priv->card_8185 == 1){/* version C or B */
if(priv->card_8185_Bversion) /* version B*/
write_nic_dword(dev, RF_PARA, 0x44);
else /* version C */
write_nic_dword(dev, RF_PARA, 0x100044);
}else{ /* version D */
if(priv->enable_gpio0)
write_nic_dword(dev, RF_PARA, 0x20100044);
else /* also USB */
write_nic_dword(dev, RF_PARA, 0x100044);
}
#endif
write_nic_dword(dev, RF_PARA, 0x100044);
#if 1 //0->1
rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
write_nic_byte(dev, CONFIG3, 0x44);
rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
#endif
if(priv->card_type == USB){
rtl8185_rf_pins_enable(dev);
mdelay(1000);
}
write_rtl8225(dev, 0x0, 0x67); mdelay(1);
write_rtl8225(dev, 0x1, 0xfe0); mdelay(1);
write_rtl8225(dev, 0x2, 0x44d); mdelay(1);
write_rtl8225(dev, 0x3, 0x441); mdelay(1);
if(priv->card_type == USB)
write_rtl8225(dev, 0x4, 0x486);
else
write_rtl8225(dev, 0x4, 0x8be);
mdelay(1);
#if 0
}else if(priv->phy_ver == 1){
u32 read_cam(struct net_device *dev, u8 addr)
{
write_nic_dword(dev, RWCAM, 0x80000000|(addr&0xff));
return read_nic_dword(dev, 0xa8);
}
void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType,
u8 *MacAddr, u8 DefaultKey, u32 *KeyContent)
{
u32 TargetCommand = 0;
u32 TargetContent = 0;
u16 usConfig = 0;
u8 i;
struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
enum rt_rf_power_state rtState;
rtState = priv->rtllib->eRFPowerState;
if (priv->rtllib->PowerSaveControl.bInactivePs) {
if (rtState == eRfOff) {
if (priv->rtllib->RfOffReason > RF_CHANGE_BY_IPS) {
RT_TRACE(COMP_ERR, "%s(): RF is OFF.\n",
__func__);
return ;
} else {
down(&priv->rtllib->ips_sem);
IPSLeave(dev);
up(&priv->rtllib->ips_sem);
}
}
}
priv->rtllib->is_set_key = true;
if (EntryNo >= TOTAL_CAM_ENTRY)
RT_TRACE(COMP_ERR, "cam entry exceeds in setKey()\n");
RT_TRACE(COMP_SEC, "====>to setKey(), dev:%p, EntryNo:%d, KeyIndex:%d,"
"KeyType:%d, MacAddr %pM\n", dev, EntryNo, KeyIndex,
KeyType, MacAddr);
if (DefaultKey)
usConfig |= BIT15 | (KeyType<<2);
else
usConfig |= BIT15 | (KeyType<<2) | KeyIndex;
for (i = 0; i < CAM_CONTENT_COUNT; i++) {
TargetCommand = i + CAM_CONTENT_COUNT * EntryNo;
TargetCommand |= BIT31|BIT16;
if (i == 0) {
TargetContent = (u32)(*(MacAddr+0)) << 16 |
(u32)(*(MacAddr+1)) << 24 |
(u32)usConfig;
write_nic_dword(dev, WCAMI, TargetContent);
write_nic_dword(dev, RWCAM, TargetCommand);
} else if (i == 1) {
TargetContent = (u32)(*(MacAddr+2)) |
(u32)(*(MacAddr+3)) << 8 |
(u32)(*(MacAddr+4)) << 16 |
(u32)(*(MacAddr+5)) << 24;
write_nic_dword(dev, WCAMI, TargetContent);
write_nic_dword(dev, RWCAM, TargetCommand);
} else {
if (KeyContent != NULL) {
write_nic_dword(dev, WCAMI,
(u32)(*(KeyContent+i-2)));
write_nic_dword(dev, RWCAM, TargetCommand);
udelay(100);
}
}
}
RT_TRACE(COMP_SEC, "=========>after set key, usconfig:%x\n", usConfig);
}
bool FirmwareCheckReady(struct net_device *dev, u8 LoadFWStatus)
{
struct r8192_priv *priv = ieee80211_priv(dev);
bool rtStatus = true;
rt_firmware *pFirmware = priv->pFirmware;
int PollingCnt = 1000;
u8 CPUStatus = 0;
u32 tmpU4b;
pFirmware->FWStatus = (FIRMWARE_8192S_STATUS)LoadFWStatus;
switch (LoadFWStatus) {
case FW_STATUS_LOAD_IMEM:
do { /* Polling IMEM code done. */
CPUStatus = read_nic_byte(dev, TCR);
if(CPUStatus& IMEM_CODE_DONE)
break;
udelay(5);
} while (PollingCnt--);
if (!(CPUStatus & IMEM_CHK_RPT) || PollingCnt <= 0) {
RT_TRACE(COMP_ERR, "FW_STATUS_LOAD_IMEM FAIL CPU, Status=%x\r\n", CPUStatus);
goto FirmwareCheckReadyFail;
}
break;
case FW_STATUS_LOAD_EMEM: /* Check Put Code OK and Turn On CPU */
do { /* Polling EMEM code done. */
CPUStatus = read_nic_byte(dev, TCR);
if(CPUStatus& EMEM_CODE_DONE)
break;
udelay(5);
} while (PollingCnt--);
if (!(CPUStatus & EMEM_CHK_RPT)) {
RT_TRACE(COMP_ERR, "FW_STATUS_LOAD_EMEM FAIL CPU, Status=%x\r\n", CPUStatus);
goto FirmwareCheckReadyFail;
}
/* Turn On CPU */
if (FirmwareEnableCPU(dev) != true) {
RT_TRACE(COMP_ERR, "%s(): failed to enable CPU",
__func__);
goto FirmwareCheckReadyFail;
}
break;
case FW_STATUS_LOAD_DMEM:
do { /* Polling DMEM code done */
CPUStatus = read_nic_byte(dev, TCR);
if(CPUStatus& DMEM_CODE_DONE)
break;
udelay(5);
} while (PollingCnt--);
if (!(CPUStatus & DMEM_CODE_DONE)) {
RT_TRACE(COMP_ERR, "Polling DMEM code done fail ! CPUStatus(%#x)\n", CPUStatus);
goto FirmwareCheckReadyFail;
}
RT_TRACE(COMP_FIRMWARE, "%s(): DMEM code download success, "
"CPUStatus(%#x)",
__func__, CPUStatus);
PollingCnt = 10000; /* Set polling cycle to 10ms. */
do { /* Polling Load Firmware ready */
CPUStatus = read_nic_byte(dev, TCR);
if(CPUStatus & FWRDY)
break;
udelay(100);
} while (PollingCnt--);
RT_TRACE(COMP_FIRMWARE, "%s(): polling load firmware ready, "
"CPUStatus(%x)",
__func__, CPUStatus);
if ((CPUStatus & LOAD_FW_READY) != LOAD_FW_READY) {
RT_TRACE(COMP_ERR, "Polling Load Firmware ready failed "
"CPUStatus(%x)\n", CPUStatus);
goto FirmwareCheckReadyFail;
}
/*
* USB interface will update
* reserved followings parameters later
*/
//
// <Roger_Notes> If right here, we can set TCR/RCR to desired value
// and config MAC lookback mode to normal mode. 2008.08.28.
//
tmpU4b = read_nic_dword(dev,TCR);
write_nic_dword(dev, TCR, (tmpU4b&(~TCR_ICV)));
tmpU4b = read_nic_dword(dev, RCR);
write_nic_dword(dev, RCR,
(tmpU4b|RCR_APPFCS|RCR_APP_ICV|RCR_APP_MIC));
RT_TRACE(COMP_FIRMWARE, "%s(): Current RCR settings(%#x)",
__func__, tmpU4b);
// Set to normal mode.
write_nic_byte(dev, LBKMD_SEL, LBK_NORMAL);
break;
default:
break;
}
RT_TRACE(COMP_FIRMWARE, "%s(): LoadFWStatus(%d), success",
__func__, LoadFWStatus);
return rtStatus;
FirmwareCheckReadyFail:
rtStatus = false;
RT_TRACE(COMP_FIRMWARE, "%s(): LoadFWStatus(%d), failed",
__func__, LoadFWStatus);
return rtStatus;
}
static void MgntDisconnectIBSS(struct r8192_priv *priv)
{
u8 i;
bool bFilterOutNonAssociatedBSSID = false;
priv->ieee80211->state = IEEE80211_NOLINK;
for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i]= 0x55;
priv->OpMode = RT_OP_MODE_NO_LINK;
write_nic_word(priv, BSSIDR, ((u16*)priv->ieee80211->current_network.bssid)[0]);
write_nic_dword(priv, BSSIDR+2, ((u32*)(priv->ieee80211->current_network.bssid+2))[0]);
{
RT_OP_MODE OpMode = priv->OpMode;
u8 btMsr = read_nic_byte(priv, MSR);
btMsr &= 0xfc;
switch(OpMode)
{
case RT_OP_MODE_INFRASTRUCTURE:
btMsr |= MSR_LINK_MANAGED;
break;
case RT_OP_MODE_IBSS:
btMsr |= MSR_LINK_ADHOC;
// led link set separate
break;
case RT_OP_MODE_AP:
btMsr |= MSR_LINK_MASTER;
break;
default:
btMsr |= MSR_LINK_NONE;
break;
}
write_nic_byte(priv, MSR, btMsr);
}
ieee80211_stop_send_beacons(priv->ieee80211);
// If disconnect, clear RCR CBSSID bit
bFilterOutNonAssociatedBSSID = false;
{
u32 RegRCR, Type;
Type = bFilterOutNonAssociatedBSSID;
RegRCR = read_nic_dword(priv, RCR);
priv->ReceiveConfig = RegRCR;
if (Type == true)
RegRCR |= (RCR_CBSSID);
else if (Type == false)
RegRCR &= (~RCR_CBSSID);
{
write_nic_dword(priv, RCR, RegRCR);
priv->ReceiveConfig = RegRCR;
}
}
notify_wx_assoc_event(priv->ieee80211);
}
bool FirmwareCheckReady(struct net_device *dev, u8 LoadFWStatus)
{
struct r8192_priv *priv = rtllib_priv(dev);
bool rtStatus = true;
rt_firmware *pFirmware = priv->pFirmware;
short PollingCnt = 1000;
u8 CPUStatus = 0;
u32 tmpU4b;
RT_TRACE(COMP_FIRMWARE, "--->%s(): LoadStaus(%d),", __FUNCTION__, LoadFWStatus);
pFirmware->FWStatus = (FIRMWARE_8192S_STATUS)LoadFWStatus;
switch (LoadFWStatus) {
case FW_STATUS_LOAD_IMEM:
do {
CPUStatus = read_nic_byte(dev, TCR);
if(CPUStatus& IMEM_CODE_DONE)
break;
udelay(5);
} while (PollingCnt--);
if (!(CPUStatus & IMEM_CHK_RPT) || (PollingCnt <= 0)) {
RT_TRACE(COMP_ERR, "FW_STATUS_LOAD_IMEM FAIL CPU, Status=%x\r\n", CPUStatus);
goto status_check_fail;
}
break;
case FW_STATUS_LOAD_EMEM:
do {
CPUStatus = read_nic_byte(dev, TCR);
if(CPUStatus& EMEM_CODE_DONE)
break;
udelay(5);
} while(PollingCnt--);
if (!(CPUStatus & EMEM_CHK_RPT) || (PollingCnt <= 0)) {
RT_TRACE(COMP_ERR, "FW_STATUS_LOAD_EMEM FAIL CPU, Status=%x\r\n", CPUStatus);
goto status_check_fail;
}
rtStatus = FirmwareEnableCPU(dev);
if (rtStatus != true) {
RT_TRACE(COMP_ERR, "Enable CPU fail ! \n" );
goto status_check_fail;
}
break;
case FW_STATUS_LOAD_DMEM:
do {
CPUStatus = read_nic_byte(dev, TCR);
if (CPUStatus& DMEM_CODE_DONE)
break;
udelay(5);
} while(PollingCnt--);
if (!(CPUStatus & DMEM_CODE_DONE) || (PollingCnt <= 0)) {
RT_TRACE(COMP_ERR, "Polling DMEM code done fail ! CPUStatus(%#x)\n", CPUStatus);
goto status_check_fail;
}
RT_TRACE(COMP_FIRMWARE, "DMEM code download success, CPUStatus(%#x)\n", CPUStatus);
PollingCnt = 2000;
do {
CPUStatus = read_nic_byte(dev, TCR);
if(CPUStatus & FWRDY)
break;
udelay(40);
} while(PollingCnt--);
RT_TRACE(COMP_FIRMWARE, "Polling Load Firmware ready, CPUStatus(%x)\n", CPUStatus);
if (((CPUStatus & LOAD_FW_READY) != LOAD_FW_READY) || (PollingCnt <= 0)) {
RT_TRACE(COMP_ERR, "Polling Load Firmware ready fail ! CPUStatus(%x)\n", CPUStatus);
goto status_check_fail;
}
#ifdef RTL8192SE
#endif
tmpU4b = read_nic_dword(dev,TCR);
write_nic_dword(dev, TCR, (tmpU4b&(~TCR_ICV)));
tmpU4b = read_nic_dword(dev, RCR);
write_nic_dword(dev, RCR,
(tmpU4b|RCR_APPFCS|RCR_APP_ICV|RCR_APP_MIC));
RT_TRACE(COMP_FIRMWARE, "FirmwareCheckReady(): Current RCR settings(%#x)\n", tmpU4b);
#if 0
priv->TransmitConfig = read_nic_dword_E(dev, TCR);
RT_TRACE(COMP_FIRMWARE, "FirmwareCheckReady(): Current TCR settings(%#x)\n", priv->TransmitConfig);
#endif
write_nic_byte(dev, LBKMD_SEL, LBK_NORMAL);
break;
default :
RT_TRACE(COMP_FIRMWARE, "Unknown status check!\n");
rtStatus = false;
break;
}
status_check_fail:
RT_TRACE(COMP_FIRMWARE, "<---%s: LoadFWStatus(%d), rtStatus(%x)\n", __FUNCTION__,
LoadFWStatus, rtStatus);
return rtStatus;
}
int rtl8192E_suspend (struct pci_dev *pdev, pm_message_t state)
{
struct net_device *dev = pci_get_drvdata(pdev);
struct r8192_priv *priv = ieee80211_priv(dev);
u8 ucRegRead;
u32 ulRegRead;
RT_TRACE(COMP_POWER, "============> r8192E suspend call.\n");
if (!netif_running(dev))
goto out_pci_suspend;
if (dev->netdev_ops->ndo_stop)
dev->netdev_ops->ndo_stop(dev);
#if 0
netif_carrier_off(dev);
ieee80211_softmac_stop_protocol(priv->ieee80211);
write_nic_byte(dev,MSR,(read_nic_byte(dev,MSR)&0xfc)|MSR_LINK_NONE);
if(!priv->ieee80211->bSupportRemoteWakeUp) {
write_nic_byte(dev, CMDR, 0);
}
write_nic_dword(dev,INTA_MASK,0);
priv->irq_enabled = 0;
write_nic_dword(dev,ISR,read_nic_dword(dev, ISR));
cancel_work_sync(&priv->reset_wq);
del_timer_sync(&priv->fsync_timer);
del_timer_sync(&priv->watch_dog_timer);
cancel_delayed_work(&priv->watch_dog_wq);
cancel_delayed_work(&priv->update_beacon_wq);
cancel_work_sync(&priv->qos_activate);
#endif
if(!priv->ieee80211->bSupportRemoteWakeUp) {
MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_INIT);
ulRegRead = read_nic_dword(dev, CPU_GEN);
ulRegRead|=CPU_GEN_SYSTEM_RESET;
write_nic_dword(dev, CPU_GEN, ulRegRead);
} else {
write_nic_dword(dev, WFCRC0, 0xffffffff);
write_nic_dword(dev, WFCRC1, 0xffffffff);
write_nic_dword(dev, WFCRC2, 0xffffffff);
#ifdef RTL8190P
ucRegRead = read_nic_byte(dev, GPO);
ucRegRead |= BIT0;
write_nic_byte(dev, GPO, ucRegRead);
#endif
write_nic_byte(dev, PMR, 0x5);
write_nic_byte(dev, MacBlkCtrl, 0xa);
}
out_pci_suspend:
RT_TRACE(COMP_POWER, "r8192E support WOL call??????????????????????\n");
if(priv->ieee80211->bSupportRemoteWakeUp) {
RT_TRACE(COMP_POWER, "r8192E support WOL call!!!!!!!!!!!!!!!!!!.\n");
}
netif_device_detach(dev);
pci_save_state(pdev);
pci_disable_device(pdev);
pci_enable_wake(pdev, pci_choose_state(pdev,state),\
priv->ieee80211->bSupportRemoteWakeUp?1:0);
pci_set_power_state(pdev,pci_choose_state(pdev,state));
return 0;
}
void write_cam(struct net_device *dev, u8 addr, u32 data)
{
write_nic_dword(dev, WCAMI, data);
write_nic_dword(dev, RWCAM, BIT31|BIT16|(addr&0xff));
}
static void
MgntDisconnectIBSS(
struct net_device* dev
)
{
struct r8192_priv *priv = ieee80211_priv(dev);
//RT_OP_MODE OpMode;
u8 i;
bool bFilterOutNonAssociatedBSSID = false;
//IEEE80211_DEBUG(IEEE80211_DL_TRACE, "XXXXXXXXXX MgntDisconnect IBSS\n");
priv->ieee80211->state = IEEE80211_NOLINK;
// PlatformZeroMemory( pMgntInfo->Bssid, 6 );
for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i]= 0x55;
priv->OpMode = RT_OP_MODE_NO_LINK;
write_nic_word(dev, BSSIDR, ((u16*)priv->ieee80211->current_network.bssid)[0]);
write_nic_dword(dev, BSSIDR+2, ((u32*)(priv->ieee80211->current_network.bssid+2))[0]);
{
RT_OP_MODE OpMode = priv->OpMode;
//LED_CTL_MODE LedAction = LED_CTL_NO_LINK;
u8 btMsr = read_nic_byte(dev, MSR);
btMsr &= 0xfc;
switch(OpMode)
{
case RT_OP_MODE_INFRASTRUCTURE:
btMsr |= MSR_LINK_MANAGED;
//LedAction = LED_CTL_LINK;
break;
case RT_OP_MODE_IBSS:
btMsr |= MSR_LINK_ADHOC;
// led link set seperate
break;
case RT_OP_MODE_AP:
btMsr |= MSR_LINK_MASTER;
//LedAction = LED_CTL_LINK;
break;
default:
btMsr |= MSR_LINK_NONE;
break;
}
write_nic_byte(dev, MSR, btMsr);
// LED control
//Adapter->HalFunc.LedControlHandler(Adapter, LedAction);
}
ieee80211_stop_send_beacons(priv->ieee80211);
// If disconnect, clear RCR CBSSID bit
bFilterOutNonAssociatedBSSID = false;
{
u32 RegRCR, Type;
Type = bFilterOutNonAssociatedBSSID;
RegRCR = read_nic_dword(dev,RCR);
priv->ReceiveConfig = RegRCR;
if (Type == true)
RegRCR |= (RCR_CBSSID);
else if (Type == false)
RegRCR &= (~RCR_CBSSID);
{
write_nic_dword(dev, RCR,RegRCR);
priv->ReceiveConfig = RegRCR;
}
}
//MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE );
notify_wx_assoc_event(priv->ieee80211);
}
bool
FirmwareCheckReady(struct net_device *dev, u8 LoadFWStatus)
{
struct r8192_priv *priv = ieee80211_priv(dev);
RT_STATUS rtStatus = RT_STATUS_SUCCESS;
rt_firmware *pFirmware = priv->pFirmware;
int PollingCnt = 1000;
//u8 tmpU1b, CPUStatus = 0;
u8 CPUStatus = 0;
u32 tmpU4b;
//bool bOrgIMREnable;
RT_TRACE(COMP_FIRMWARE, "--->FirmwareCheckReady(): LoadStaus(%d),", LoadFWStatus);
pFirmware->FWStatus = (FIRMWARE_8192S_STATUS)LoadFWStatus;
if( LoadFWStatus == FW_STATUS_LOAD_IMEM)
{
do
{//Polling IMEM code done.
CPUStatus = read_nic_byte(dev, TCR);
if(CPUStatus& IMEM_CODE_DONE)
break;
udelay(5);
}while(PollingCnt--);
if(!(CPUStatus & IMEM_CHK_RPT) || PollingCnt <= 0)
{
RT_TRACE(COMP_ERR, "FW_STATUS_LOAD_IMEM FAIL CPU, Status=%x\r\n", CPUStatus);
return false;
}
}
else if( LoadFWStatus == FW_STATUS_LOAD_EMEM)
{//Check Put Code OK and Turn On CPU
do
{//Polling EMEM code done.
CPUStatus = read_nic_byte(dev, TCR);
if(CPUStatus& EMEM_CODE_DONE)
break;
udelay(5);
}while(PollingCnt--);
if(!(CPUStatus & EMEM_CHK_RPT))
{
RT_TRACE(COMP_ERR, "FW_STATUS_LOAD_EMEM FAIL CPU, Status=%x\r\n", CPUStatus);
return false;
}
// Turn On CPU
rtStatus = FirmwareEnableCPU(dev);
if(rtStatus != RT_STATUS_SUCCESS)
{
RT_TRACE(COMP_ERR, "Enable CPU fail ! \n" );
return false;
}
}
else if( LoadFWStatus == FW_STATUS_LOAD_DMEM)
{
do
{//Polling DMEM code done
CPUStatus = read_nic_byte(dev, TCR);
if(CPUStatus& DMEM_CODE_DONE)
break;
udelay(5);
}while(PollingCnt--);
if(!(CPUStatus & DMEM_CODE_DONE))
{
RT_TRACE(COMP_ERR, "Polling DMEM code done fail ! CPUStatus(%#x)\n", CPUStatus);
return false;
}
RT_TRACE(COMP_FIRMWARE, "DMEM code download success, CPUStatus(%#x)\n", CPUStatus);
// PollingCnt = 100; // Set polling cycle to 10ms.
PollingCnt = 10000; // Set polling cycle to 10ms.
do
{//Polling Load Firmware ready
CPUStatus = read_nic_byte(dev, TCR);
if(CPUStatus & FWRDY)
break;
udelay(100);
}while(PollingCnt--);
RT_TRACE(COMP_FIRMWARE, "Polling Load Firmware ready, CPUStatus(%x)\n", CPUStatus);
//if(!(CPUStatus & LOAD_FW_READY))
//if((CPUStatus & LOAD_FW_READY) != 0xff)
if((CPUStatus & LOAD_FW_READY) != LOAD_FW_READY)
{
RT_TRACE(COMP_ERR, "Polling Load Firmware ready fail ! CPUStatus(%x)\n", CPUStatus);
return false;
}
//
// <Roger_Notes> USB interface will update reserved followings parameters later!!
// 2008.08.28.
//
//
// <Roger_Notes> If right here, we can set TCR/RCR to desired value
// and config MAC lookback mode to normal mode. 2008.08.28.
//
tmpU4b = read_nic_dword(dev,TCR);
write_nic_dword(dev, TCR, (tmpU4b&(~TCR_ICV)));
tmpU4b = read_nic_dword(dev, RCR);
write_nic_dword(dev, RCR,
(tmpU4b|RCR_APPFCS|RCR_APP_ICV|RCR_APP_MIC));
RT_TRACE(COMP_FIRMWARE, "FirmwareCheckReady(): Current RCR settings(%#x)\n", tmpU4b);
// Set to normal mode.
write_nic_byte(dev, LBKMD_SEL, LBK_NORMAL);
}
RT_TRACE(COMP_FIRMWARE, "<---FirmwareCheckReady(): LoadFWStatus(%d), rtStatus(%x)\n", LoadFWStatus, rtStatus);
return (rtStatus == RT_STATUS_SUCCESS) ? true:false;
}
static void
MlmeDisassociateRequest(
struct net_device* dev,
u8* asSta,
u8 asRsn
)
{
struct r8192_priv *priv = ieee80211_priv(dev);
u8 i;
RemovePeerTS(priv->ieee80211, asSta);
SendDisassociation( priv->ieee80211, asSta, asRsn );
if(memcpy(priv->ieee80211->current_network.bssid,asSta,6) == NULL)
{
//ShuChen TODO: change media status.
//ShuChen TODO: What to do when disassociate.
priv->ieee80211->state = IEEE80211_NOLINK;
//pMgntInfo->AsocTimestamp = 0;
for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i] = 0x22;
// pMgntInfo->mBrates.Length = 0;
// Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_BASIC_RATE, (pu1Byte)(&pMgntInfo->mBrates) );
priv->OpMode = RT_OP_MODE_NO_LINK;
{
RT_OP_MODE OpMode = priv->OpMode;
//LED_CTL_MODE LedAction = LED_CTL_NO_LINK;
u8 btMsr = read_nic_byte(dev, MSR);
btMsr &= 0xfc;
switch(OpMode)
{
case RT_OP_MODE_INFRASTRUCTURE:
btMsr |= MSR_LINK_MANAGED;
//LedAction = LED_CTL_LINK;
break;
case RT_OP_MODE_IBSS:
btMsr |= MSR_LINK_ADHOC;
// led link set seperate
break;
case RT_OP_MODE_AP:
btMsr |= MSR_LINK_MASTER;
//LedAction = LED_CTL_LINK;
break;
default:
btMsr |= MSR_LINK_NONE;
break;
}
write_nic_byte(dev, MSR, btMsr);
// LED control
//Adapter->HalFunc.LedControlHandler(Adapter, LedAction);
}
ieee80211_disassociate(priv->ieee80211);
write_nic_word(dev, BSSIDR, ((u16*)priv->ieee80211->current_network.bssid)[0]);
write_nic_dword(dev, BSSIDR+2, ((u32*)(priv->ieee80211->current_network.bssid+2))[0]);
}
}
void rtl8225z2_rf_init(struct net_device *dev)
{
struct r8180_priv *priv = ieee80211_priv(dev);
int i;
short channel = 1;
u16 brsr;
u32 data,addr;
priv->chan = channel;
rtl8180_set_anaparam(dev, RTL8225_ANAPARAM_ON);
if(priv->card_type == USB)
rtl8225_host_usb_init(dev);
else
rtl8225_host_pci_init(dev);
write_nic_dword(dev, RF_TIMING, 0x000a8008);
brsr = read_nic_word(dev, BRSR);
write_nic_word(dev, BRSR, 0xffff);
write_nic_dword(dev, RF_PARA, 0x100044);
#if 1 //0->1
rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
write_nic_byte(dev, CONFIG3, 0x44);
rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
#endif
rtl8185_rf_pins_enable(dev);
// mdelay(1000);
write_rtl8225(dev, 0x0, 0x2bf); mdelay(1);
write_rtl8225(dev, 0x1, 0xee0); mdelay(1);
write_rtl8225(dev, 0x2, 0x44d); mdelay(1);
write_rtl8225(dev, 0x3, 0x441); mdelay(1);
write_rtl8225(dev, 0x4, 0x8c3);mdelay(1);
write_rtl8225(dev, 0x5, 0xc72);mdelay(1);
// }
write_rtl8225(dev, 0x6, 0xe6); mdelay(1);
write_rtl8225(dev, 0x7, ((priv->card_type == USB)? 0x82a : rtl8225_chan[channel])); mdelay(1);
write_rtl8225(dev, 0x8, 0x3f); mdelay(1);
write_rtl8225(dev, 0x9, 0x335); mdelay(1);
write_rtl8225(dev, 0xa, 0x9d4); mdelay(1);
write_rtl8225(dev, 0xb, 0x7bb); mdelay(1);
write_rtl8225(dev, 0xc, 0x850); mdelay(1);
write_rtl8225(dev, 0xd, 0xcdf); mdelay(1);
write_rtl8225(dev, 0xe, 0x2b); mdelay(1);
write_rtl8225(dev, 0xf, 0x114);
mdelay(100);
//if(priv->card_type != USB) /* maybe not needed even for 8185 */
// write_rtl8225(dev, 0x7, rtl8225_chan[channel]);
write_rtl8225(dev, 0x0, 0x1b7);
for(i=0;i<95;i++){
write_rtl8225(dev, 0x1, (u8)(i+1));
#if 0
if(priv->phy_ver == 1)
/* version A */
write_rtl8225(dev, 0x2, rtl8225a_rxgain[i]);
else
#endif
/* version B & C & D*/
write_rtl8225(dev, 0x2, rtl8225z2_rxgain[i]);
}
write_rtl8225(dev, 0x3, 0x80);
write_rtl8225(dev, 0x5, 0x4);
write_rtl8225(dev, 0x0, 0xb7);
write_rtl8225(dev, 0x2, 0xc4d);
if(priv->card_type == USB){
// force_pci_posting(dev);
mdelay(200);
write_rtl8225(dev, 0x2, 0x44d);
// force_pci_posting(dev);
mdelay(100);
}//End of if(priv->card_type == USB)
/* FIXME!! rtl8187 we have to check if calibrarion
* is successful and eventually cal. again (repeat
* the two write on reg 2)
*/
// Check for calibration status, 2005.11.17,
data = read_rtl8225(dev, 6);
if (!(data&0x00000080))
{
write_rtl8225(dev, 0x02, 0x0c4d);
force_pci_posting(dev); mdelay(200);
write_rtl8225(dev, 0x02, 0x044d);
force_pci_posting(dev); mdelay(100);
data = read_rtl8225(dev, 6);
if (!(data&0x00000080))
{
DMESGW("RF Calibration Failed!!!!\n");
}
}
//force_pci_posting(dev);
mdelay(200); //200 for 8187
// //if(priv->card_type != USB){
// write_rtl8225(dev, 0x2, 0x44d);
// write_rtl8225(dev, 0x7, rtl8225_chan[channel]);
// write_rtl8225(dev, 0x2, 0x47d);
//
// force_pci_posting(dev);
// mdelay(100);
//
// write_rtl8225(dev, 0x2, 0x44d);
// //}
write_rtl8225(dev, 0x0, 0x2bf);
if(priv->card_type != USB)
rtl8185_rf_pins_enable(dev);
//set up ZEBRA AGC table, 2005.11.17,
for(i=0;i<128;i++){
data = rtl8225_agc[i];
addr = i + 0x80; //enable writing AGC table
write_phy_ofdm(dev, 0xb, data);
mdelay(1);
write_phy_ofdm(dev, 0xa, addr);
mdelay(1);
}
#if 0
for(i=0;i<128;i++){
write_phy_ofdm(dev, 0xb, rtl8225_agc[i]);
mdelay(1);
write_phy_ofdm(dev, 0xa, (u8)i+ 0x80);
mdelay(1);
}
#endif
force_pci_posting(dev);
mdelay(1);
write_phy_ofdm(dev, 0x0, 0x1); mdelay(1);
write_phy_ofdm(dev, 0x1, 0x2); mdelay(1);
write_phy_ofdm(dev, 0x2, ((priv->card_type == USB)? 0x42 : 0x62)); mdelay(1);
write_phy_ofdm(dev, 0x3, 0x0); mdelay(1);
write_phy_ofdm(dev, 0x4, 0x0); mdelay(1);
write_phy_ofdm(dev, 0x5, 0x0); mdelay(1);
write_phy_ofdm(dev, 0x6, 0x40); mdelay(1);
write_phy_ofdm(dev, 0x7, 0x0); mdelay(1);
write_phy_ofdm(dev, 0x8, 0x40); mdelay(1);
write_phy_ofdm(dev, 0x9, 0xfe); mdelay(1);
write_phy_ofdm(dev, 0xa, 0x8); mdelay(1);
//write_phy_ofdm(dev, 0x18, 0xef);
// }
//}
write_phy_ofdm(dev, 0xb, 0x80); mdelay(1);
write_phy_ofdm(dev, 0xc, 0x1);mdelay(1);
//if(priv->card_type != USB)
write_phy_ofdm(dev, 0xd, 0x43);
write_phy_ofdm(dev, 0xe, 0xd3);mdelay(1);
#if 0
if(priv->card_8185 == 1){
if(priv->card_8185_Bversion)
write_phy_ofdm(dev, 0xf, 0x20);/*ver B*/
else
write_phy_ofdm(dev, 0xf, 0x28);/*ver C*/
}else{
#endif
write_phy_ofdm(dev, 0xf, 0x38);mdelay(1);
/*ver D & 8187*/
// }
// if(priv->card_8185 == 1 && priv->card_8185_Bversion)
// write_phy_ofdm(dev, 0x10, 0x04);/*ver B*/
// else
write_phy_ofdm(dev, 0x10, 0x84);mdelay(1);
/*ver C & D & 8187*/
write_phy_ofdm(dev, 0x11, 0x07);mdelay(1);
/*agc resp time 700*/
// if(priv->card_8185 == 2){
/* Ver D & 8187*/
write_phy_ofdm(dev, 0x12, 0x20);mdelay(1);
write_phy_ofdm(dev, 0x13, 0x20);mdelay(1);
#if 0
}else{
int rtl8192E_suspend (struct pci_dev *pdev, pm_message_t state)
{
struct net_device *dev = pci_get_drvdata(pdev);
struct r8192_priv *priv = rtllib_priv(dev);
#ifdef _RTL8192_EXT_PATCH_
struct net_device *meshdev = priv->rtllib->meshdev;
#endif
#if !(defined RTL8192SE || defined RTL8192CE)
u32 ulRegRead;
#endif
RT_TRACE(COMP_POWER, "============> r8192E suspend call.\n");
printk("============> r8192E suspend call.\n");
#ifdef ENABLE_GPIO_RADIO_CTL
del_timer_sync(&priv->gpio_polling_timer);
cancel_delayed_work(&priv->gpio_change_rf_wq);
priv->polling_timer_on = 0;
#endif
#ifdef _RTL8192_EXT_PATCH_
if ((!netif_running(dev)) && (!netif_running(meshdev)))
#else
if (!netif_running(dev))
#endif
{
printk("RTL819XE:UI is open out of suspend function\n");
goto out_pci_suspend;
}
#ifdef HAVE_NET_DEVICE_OPS
if (!(priv->up)) {
priv->rtllib->wlan_up_before_suspend = 0;
} else {
priv->rtllib->wlan_up_before_suspend = 1;
printk("====>%s(2), stop wlan, wlan_up_before_suspend = %d\n", __func__, priv->rtllib->wlan_up_before_suspend);
if (dev->netdev_ops->ndo_stop)
dev->netdev_ops->ndo_stop(dev);
}
#ifdef _RTL8192_EXT_PATCH_
if (!(priv->mesh_up)) {
printk("====>%s(1), stop wlan, wlan_up_before_suspend = %d\n", __func__, priv->rtllib->wlan_up_before_suspend);
priv->rtllib->mesh_up_before_suspend = 0;
} else {
priv->rtllib->mesh_up_before_suspend = 1;
if (meshdev->netdev_ops->ndo_stop)
meshdev->netdev_ops->ndo_stop(meshdev);
}
#endif
#else
if (!(priv->up))
priv->rtllib->wlan_up_before_suspend = 0;
else {
priv->rtllib->wlan_up_before_suspend = 1;
dev->stop(dev);
}
#ifdef _RTL8192_EXT_PATCH_
if (!(priv->mesh_up))
priv->rtllib->mesh_up_before_suspend = 0;
else {
priv->rtllib->mesh_up_before_suspend = 1;
meshdev->stop(meshdev);
}
#endif
#endif
netif_device_detach(dev);
#if !(defined RTL8192SE || defined RTL8192CE)
if(!priv->rtllib->bSupportRemoteWakeUp) {
MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_INIT,true);
ulRegRead = read_nic_dword(dev, CPU_GEN);
ulRegRead|=CPU_GEN_SYSTEM_RESET;
write_nic_dword(dev, CPU_GEN, ulRegRead);
} else {
write_nic_dword(dev, WFCRC0, 0xffffffff);
write_nic_dword(dev, WFCRC1, 0xffffffff);
write_nic_dword(dev, WFCRC2, 0xffffffff);
#ifdef RTL8190P
{
u8 ucRegRead;
ucRegRead = read_nic_byte(dev, GPO);
ucRegRead |= BIT0;
write_nic_byte(dev, GPO, ucRegRead);
}
#endif
write_nic_byte(dev, PMR, 0x5);
write_nic_byte(dev, MacBlkCtrl, 0xa);
}
#endif
out_pci_suspend:
RT_TRACE(COMP_POWER, "r8192E support WOL call??????????????????????\n");
printk("r8192E support WOL call??????????????????????\n");
if(priv->rtllib->bSupportRemoteWakeUp) {
RT_TRACE(COMP_POWER, "r8192E support WOL call!!!!!!!!!!!!!!!!!!.\n");
}
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10))
pci_save_state(pdev,&(priv->pci_state));
pci_disable_device(pdev);
pci_enable_wake(pdev, state,\
priv->rtllib->bSupportRemoteWakeUp?1:0);
pci_set_power_state(pdev,state);
#else
pci_save_state(pdev);
pci_disable_device(pdev);
pci_enable_wake(pdev, pci_choose_state(pdev,state),\
priv->rtllib->bSupportRemoteWakeUp?1:0);
pci_set_power_state(pdev,pci_choose_state(pdev,state));
#endif
mdelay(20);
return 0;
}
