/* initialises MSRs required to setup sysenter and sysexit */
BOOT_CODE void
init_sysenter_msrs(void)
{
x86_wrmsr(IA32_SYSENTER_CS_MSR, (uint64_t)(word_t)SEL_CS_0);
x86_wrmsr(IA32_SYSENTER_EIP_MSR, (uint64_t)(word_t)&handle_syscall);
/* manually add 4 bytes to x86KStss so that it is valid for both
* 32-bit and 64-bit */
x86_wrmsr(IA32_SYSENTER_ESP_MSR, (uint64_t)(word_t)((char *)&x86KStss.tss.words[0] + 4));
}
/* Disables as many prefetchers as possible */
BOOT_CODE bool_t
disablePrefetchers()
{
x86_cpu_identity_t *model_info;
uint32_t low, high;
word_t i;
uint32_t valid_models[] = { BROADWELL_1_MODEL_ID, BROADWELL_2_MODEL_ID,
BROADWELL_3_MODEL_ID, BROADWELL_4_MODEL_ID,
BROADWELL_5_MODEL_ID,
HASWELL_1_MODEL_ID, HASWELL_2_MODEL_ID,
HASWELL_3_MODEL_ID, HASWELL_4_MODEL_ID,
IVY_BRIDGE_1_MODEL_ID, IVY_BRIDGE_2_MODEL_ID,
IVY_BRIDGE_3_MODEL_ID,
SANDY_BRIDGE_1_MODEL_ID, SANDY_BRIDGE_2_MODEL_ID, WESTMERE_1_MODEL_ID, WESTMERE_2_MODEL_ID,
WESTMERE_3_MODEL_ID, NEHALEM_1_MODEL_ID, NEHALEM_2_MODEL_ID, NEHALEM_3_MODEL_ID
};
model_info = x86_cpuid_get_model_info();
for (i = 0; i < ARRAY_SIZE(valid_models); i++) {
/* The model ID is only useful when hashed together with the family ID.
* They are both meant to be combined to form a unique identifier.
*
* As far as I can tell though, we might be able to actually just
* disable prefetching on anything that matches family_ID==0x6, and
* there is no need to also look at the model_ID.
*/
if (model_info->family == IA32_PREFETCHER_COMPATIBLE_FAMILIES_ID
&& model_info->model == valid_models[i]) {
low = x86_rdmsr_low(IA32_PREFETCHER_MSR);
high = x86_rdmsr_high(IA32_PREFETCHER_MSR);
low |= IA32_PREFETCHER_MSR_L2;
low |= IA32_PREFETCHER_MSR_L2_ADJACENT;
low |= IA32_PREFETCHER_MSR_DCU;
low |= IA32_PREFETCHER_MSR_DCU_IP;
x86_wrmsr(IA32_PREFETCHER_MSR, ((uint64_t)high) << 32 | low);
return true;
}
}
printf("Disabling prefetchers not implemented for CPU fam %x model %x\n",
model_info->family, model_info->model);
return false;
}
/*
* Initialise the FPU for this machine.
*/
BOOT_CODE bool_t
Arch_initFpu(void)
{
/* Enable FPU / SSE / SSE2 / SSE3 / SSSE3 / SSE4 Extensions. */
write_cr4(read_cr4() | CR4_OSFXSR);
/* Enable the FPU in general. */
write_cr0((read_cr0() & ~CR0_EMULATION) | CR0_MONITOR_COPROC | CR0_NUMERIC_ERROR);
enableFpu();
/* Initialize the fpu state */
finit();
if (config_set(CONFIG_XSAVE)) {
uint64_t xsave_features;
uint32_t xsave_instruction;
uint64_t desired_features = config_ternary(CONFIG_XSAVE, CONFIG_XSAVE_FEATURE_SET, 1);
xsave_state_t *nullFpuState = (xsave_state_t *) &x86KSnullFpuState;
/* create NULL state for FPU to be used by XSAVE variants */
memzero(&x86KSnullFpuState, sizeof(x86KSnullFpuState));
/* check for XSAVE support */
if (!(x86_cpuid_ecx(1, 0) & BIT(26))) {
printf("XSAVE not supported\n");
return false;
}
/* enable XSAVE support */
write_cr4(read_cr4() | CR4_OSXSAVE);
/* check feature mask */
xsave_features = ((uint64_t)x86_cpuid_edx(0x0d, 0x0) << 32) | x86_cpuid_eax(0x0d, 0x0);
if ((xsave_features & desired_features) != desired_features) {
printf("Requested feature mask is 0x%llx, but only 0x%llx supported\n", desired_features, (long long)xsave_features);
return false;
}
/* enable feature mask */
write_xcr0(desired_features);
/* validate the xsave buffer size and instruction */
if (x86_cpuid_ebx(0x0d, 0x0) > CONFIG_XSAVE_SIZE) {
printf("XSAVE buffer set set to %d, but needs to be at least %d\n", CONFIG_XSAVE_SIZE, x86_cpuid_ebx(0x0d, 0x0));
return false;
}
if (x86_cpuid_ebx(0x0d, 0x0) < CONFIG_XSAVE_SIZE) {
printf("XSAVE buffer set set to %d, but only needs to be %d.\n"
"Warning: Memory may be wasted with larger than needed TCBs.\n",
CONFIG_XSAVE_SIZE, x86_cpuid_ebx(0x0d, 0x0));
}
/* check if a specialized XSAVE instruction was requested */
xsave_instruction = x86_cpuid_eax(0x0d, 0x1);
if (config_set(CONFIG_XSAVE_XSAVEOPT)) {
if (!(xsave_instruction & BIT(0))) {
printf("XSAVEOPT requested, but not supported\n");
return false;
}
} else if (config_set(CONFIG_XSAVE_XSAVEC)) {
if (!(xsave_instruction & BIT(1))) {
printf("XSAVEC requested, but not supported\n");
return false;
}
} else if (config_set(CONFIG_XSAVE_XSAVES)) {
if (!(xsave_instruction & BIT(3))) {
printf("XSAVES requested, but not supported\n");
return false;
}
/* AVX state from extended region should be in compacted format */
nullFpuState->header.xcomp_bv = XCOMP_BV_COMPACTED_FORMAT;
/* initialize the XSS MSR */
x86_wrmsr(IA32_XSS_MSR, desired_features);
}
/* copy i387 FPU initial state from FPU */
saveFpuState(&x86KSnullFpuState);
nullFpuState->i387.mxcsr = MXCSR_INIT_VALUE;
} else {
/* Store the null fpu state */
saveFpuState(&x86KSnullFpuState);
}
/* Set the FPU to lazy switch mode */
disableFpu();
return true;
}
/*
* Initialise the FPU for this machine.
*/
BOOT_CODE bool_t
Arch_initFpu(void)
{
/* Enable FPU / SSE / SSE2 / SSE3 / SSSE3 / SSE4 Extensions. */
write_cr4(read_cr4() | CR4_OSFXSR);
/* Enable the FPU in general. */
write_cr0((read_cr0() & ~CR0_EMULATION) | CR0_MONITOR_COPROC | CR0_NUMERIC_ERROR);
enableFpu();
/* Initialize the fpu state */
finit();
if (config_set(CONFIG_XSAVE)) {
uint64_t xsave_features;
uint32_t xsave_instruction;
uint64_t desired_features = config_default(CONFIG_XSAVE_FEATURE_SET, 1);
/* check for XSAVE support */
if (!(x86_cpuid_ecx(1, 0) & BIT(26))) {
printf("XSAVE not supported\n");
return false;
}
/* enable XSAVE support */
write_cr4(read_cr4() | CR4_OSXSAVE);
/* check feature mask */
xsave_features = ((uint64_t)x86_cpuid_edx(0x0d, 0x0) << 32) | x86_cpuid_eax(0x0d, 0x0);
if ((xsave_features & desired_features) != desired_features) {
printf("Requested feature mask is 0x%llx, but only 0x%llx supported\n", desired_features, (long long)xsave_features);
return false;
}
/* enable feature mask */
write_xcr0(desired_features);
/* validate the xsave buffer size and instruction */
if (x86_cpuid_ebx(0x0d, 0x0) != CONFIG_XSAVE_SIZE) {
printf("XSAVE buffer set set to %d, but should be %d\n", CONFIG_XSAVE_SIZE, x86_cpuid_ecx(0x0d, 0x0));
return false;
}
/* check if a specialized XSAVE instruction was requested */
xsave_instruction = x86_cpuid_eax(0x0d, 0x1);
if (config_set(CONFIG_XSAVE_XSAVEOPT)) {
if (!(xsave_instruction & BIT(0))) {
printf("XSAVEOPT requested, but not supported\n");
return false;
}
} else if (config_set(CONFIG_XSAVE_XSAVEC)) {
if (!(xsave_instruction & BIT(1))) {
printf("XSAVEC requested, but not supported\n");
return false;
}
} else if (config_set(CONFIG_XSAVE_XSAVES)) {
if (!(xsave_instruction & BIT(3))) {
printf("XSAVES requested, but not supported\n");
return false;
}
/* initialize the XSS MSR */
x86_wrmsr(IA32_XSS_MSR, desired_features);
}
/* Load a NULL fpu state so that the idle thread ends up
* with a sensible FPU state and we can optimize our
* switch of it */
memzero(&x86KSnullFpuState, sizeof(x86KSnullFpuState));
loadFpuState(&x86KSnullFpuState);
} else {
/* Store the null fpu state */
saveFpuState(&x86KSnullFpuState);
}
/* Set the FPU to lazy switch mode */
disableFpu();
return true;
}
