static void xilinx_spips_reset(DeviceState *d)
{
XilinxSPIPS *s = XILINX_SPIPS(d);
memset(s->regs, 0, sizeof(s->regs));
fifo8_reset(&s->rx_fifo);
fifo8_reset(&s->rx_fifo);
/* non zero resets */
s->regs[R_CONFIG] |= MODEFAIL_GEN_EN;
s->regs[R_SLAVE_IDLE_COUNT] = 0xFF;
s->regs[R_TX_THRES] = 1;
s->regs[R_RX_THRES] = 1;
/* FIXME: move magic number definition somewhere sensible */
s->regs[R_MOD_ID] = 0x01090106;
s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET;
s->link_state = 1;
s->link_state_next = 1;
s->link_state_next_when = 0;
s->snoop_state = SNOOP_CHECKING;
s->cmd_dummies = 0;
s->man_start_com = false;
xilinx_spips_update_ixr(s);
xilinx_spips_update_cs_lines(s);
}
static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
{
for (;;) {
int i;
uint8_t rx;
uint8_t tx = 0;
for (i = 0; i < num_effective_busses(s); ++i) {
if (!i || s->snoop_state == SNOOP_STRIPING) {
if (fifo8_is_empty(&s->tx_fifo)) {
s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
xilinx_spips_update_ixr(s);
return;
} else {
tx = fifo8_pop(&s->tx_fifo);
}
}
rx = ssi_transfer(s->spi[i], (uint32_t)tx);
DB_PRINT("tx = %02x rx = %02x\n", tx, rx);
if (!i || s->snoop_state == SNOOP_STRIPING) {
if (fifo8_is_full(&s->rx_fifo)) {
s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW;
DB_PRINT("rx FIFO overflow");
} else {
fifo8_push(&s->rx_fifo, (uint8_t)rx);
}
}
}
switch (s->snoop_state) {
case (SNOOP_CHECKING):
switch (tx) { /* new instruction code */
case READ: /* 3 address bytes, no dummy bytes/cycles */
case PP:
case DPP:
case QPP:
s->snoop_state = 3;
break;
case FAST_READ: /* 3 address bytes, 1 dummy byte */
case DOR:
case QOR:
case DIOR: /* FIXME: these vary between vendor - set to spansion */
s->snoop_state = 4;
break;
case QIOR: /* 3 address bytes, 2 dummy bytes */
s->snoop_state = 6;
break;
default:
s->snoop_state = SNOOP_NONE;
}
break;
case (SNOOP_STRIPING):
case (SNOOP_NONE):
break;
default:
s->snoop_state--;
}
}
}
static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
unsigned size)
{
XilinxSPIPS *s = opaque;
uint32_t mask = ~0;
uint32_t ret;
uint8_t rx_buf[4];
addr >>= 2;
switch (addr) {
case R_CONFIG:
mask = ~(R_CONFIG_RSVD | MAN_START_COM);
break;
case R_INTR_STATUS:
ret = s->regs[addr] & IXR_ALL;
s->regs[addr] = 0;
DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
return ret;
case R_INTR_MASK:
mask = IXR_ALL;
break;
case R_EN:
mask = 0x1;
break;
case R_SLAVE_IDLE_COUNT:
mask = 0xFF;
break;
case R_MOD_ID:
mask = 0x01FFFFFF;
break;
case R_INTR_EN:
case R_INTR_DIS:
case R_TX_DATA:
mask = 0;
break;
case R_RX_DATA:
memset(rx_buf, 0, sizeof(rx_buf));
rx_data_bytes(s, rx_buf, s->num_txrx_bytes);
ret = s->regs[R_CONFIG] & ENDIAN ? cpu_to_be32(*(uint32_t *)rx_buf)
: cpu_to_le32(*(uint32_t *)rx_buf);
DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
xilinx_spips_update_ixr(s);
return ret;
}
DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4,
s->regs[addr] & mask);
return s->regs[addr] & mask;
}
static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
unsigned size)
{
XilinxSPIPS *s = opaque;
uint32_t mask = ~0;
uint32_t ret;
addr >>= 2;
switch (addr) {
case R_CONFIG:
mask = 0x0002FFFF;
break;
case R_INTR_STATUS:
case R_INTR_MASK:
mask = IXR_ALL;
break;
case R_EN:
mask = 0x1;
break;
case R_SLAVE_IDLE_COUNT:
mask = 0xFF;
break;
case R_MOD_ID:
mask = 0x01FFFFFF;
break;
case R_INTR_EN:
case R_INTR_DIS:
case R_TX_DATA:
mask = 0;
break;
case R_RX_DATA:
rx_data_bytes(s, &ret, s->num_txrx_bytes);
DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
xilinx_spips_update_ixr(s);
return ret;
}
DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, s->regs[addr] & mask);
return s->regs[addr] & mask;
}
static void xilinx_spips_reset(DeviceState *d)
{
XilinxSPIPS *s = XILINX_SPIPS(d);
int i;
for (i = 0; i < R_MAX; i++) {
s->regs[i] = 0;
}
fifo8_reset(&s->rx_fifo);
fifo8_reset(&s->rx_fifo);
/* non zero resets */
s->regs[R_CONFIG] |= MODEFAIL_GEN_EN;
s->regs[R_SLAVE_IDLE_COUNT] = 0xFF;
s->regs[R_TX_THRES] = 1;
s->regs[R_RX_THRES] = 1;
/* FIXME: move magic number definition somewhere sensible */
s->regs[R_MOD_ID] = 0x01090106;
s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET;
s->snoop_state = SNOOP_CHECKING;
xilinx_spips_update_ixr(s);
xilinx_spips_update_cs_lines(s);
}
static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
{
int debug_level = 0;
for (;;) {
int i;
uint8_t tx = 0;
uint8_t tx_rx[num_effective_busses(s)];
if (fifo8_is_empty(&s->tx_fifo)) {
if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) {
s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
}
xilinx_spips_update_ixr(s);
return;
} else if (s->snoop_state == SNOOP_STRIPING) {
for (i = 0; i < num_effective_busses(s); ++i) {
tx_rx[i] = fifo8_pop(&s->tx_fifo);
}
stripe8(tx_rx, num_effective_busses(s), false);
} else {
tx = fifo8_pop(&s->tx_fifo);
for (i = 0; i < num_effective_busses(s); ++i) {
tx_rx[i] = tx;
}
}
for (i = 0; i < num_effective_busses(s); ++i) {
DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]);
tx_rx[i] = ssi_transfer(s->spi[i], (uint32_t)tx_rx[i]);
DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]);
}
if (fifo8_is_full(&s->rx_fifo)) {
s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW;
DB_PRINT_L(0, "rx FIFO overflow");
} else if (s->snoop_state == SNOOP_STRIPING) {
stripe8(tx_rx, num_effective_busses(s), true);
for (i = 0; i < num_effective_busses(s); ++i) {
fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]);
}
} else {
fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]);
}
DB_PRINT_L(debug_level, "initial snoop state: %x\n",
(unsigned)s->snoop_state);
switch (s->snoop_state) {
case (SNOOP_CHECKING):
switch (tx) { /* new instruction code */
case READ: /* 3 address bytes, no dummy bytes/cycles */
case PP:
case DPP:
case QPP:
s->snoop_state = 3;
break;
case FAST_READ: /* 3 address bytes, 1 dummy byte */
case DOR:
case QOR:
case DIOR: /* FIXME: these vary between vendor - set to spansion */
s->snoop_state = 4;
break;
case QIOR: /* 3 address bytes, 2 dummy bytes */
s->snoop_state = 6;
break;
default:
s->snoop_state = SNOOP_NONE;
}
break;
case (SNOOP_STRIPING):
case (SNOOP_NONE):
/* Once we hit the boring stuff - squelch debug noise */
if (!debug_level) {
DB_PRINT_L(0, "squelching debug info ....\n");
debug_level = 1;
}
break;
default:
s->snoop_state--;
}
DB_PRINT_L(debug_level, "final snoop state: %x\n",
(unsigned)s->snoop_state);
}
}
static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
{
int debug_level = 0;
XilinxQSPIPS *q = (XilinxQSPIPS *) object_dynamic_cast(OBJECT(s),
TYPE_XILINX_QSPIPS);
for (;;) {
int i;
uint8_t tx = 0;
uint8_t tx_rx[MAX_NUM_BUSSES] = { 0 };
uint8_t dummy_cycles = 0;
uint8_t addr_length;
if (fifo8_is_empty(&s->tx_fifo)) {
xilinx_spips_update_ixr(s);
return;
} else if (s->snoop_state == SNOOP_STRIPING) {
for (i = 0; i < num_effective_busses(s); ++i) {
tx_rx[i] = fifo8_pop(&s->tx_fifo);
}
stripe8(tx_rx, num_effective_busses(s), false);
} else if (s->snoop_state >= SNOOP_ADDR) {
tx = fifo8_pop(&s->tx_fifo);
for (i = 0; i < num_effective_busses(s); ++i) {
tx_rx[i] = tx;
}
} else {
/* Extract a dummy byte and generate dummy cycles according to the
* link state */
tx = fifo8_pop(&s->tx_fifo);
dummy_cycles = 8 / s->link_state;
}
for (i = 0; i < num_effective_busses(s); ++i) {
int bus = num_effective_busses(s) - 1 - i;
if (dummy_cycles) {
int d;
for (d = 0; d < dummy_cycles; ++d) {
tx_rx[0] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[0]);
}
} else {
DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]);
tx_rx[i] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]);
DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]);
}
}
if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) {
DB_PRINT_L(debug_level, "dircarding drained rx byte\n");
/* Do nothing */
} else if (s->rx_discard) {
DB_PRINT_L(debug_level, "dircarding discarded rx byte\n");
s->rx_discard -= 8 / s->link_state;
} else if (fifo8_is_full(&s->rx_fifo)) {
s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW;
DB_PRINT_L(0, "rx FIFO overflow");
} else if (s->snoop_state == SNOOP_STRIPING) {
stripe8(tx_rx, num_effective_busses(s), true);
for (i = 0; i < num_effective_busses(s); ++i) {
fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]);
DB_PRINT_L(debug_level, "pushing striped rx byte\n");
}
} else {
DB_PRINT_L(debug_level, "pushing unstriped rx byte\n");
fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]);
}
if (s->link_state_next_when) {
s->link_state_next_when--;
if (!s->link_state_next_when) {
s->link_state = s->link_state_next;
}
}
DB_PRINT_L(debug_level, "initial snoop state: %x\n",
(unsigned)s->snoop_state);
switch (s->snoop_state) {
case (SNOOP_CHECKING):
/* Store the count of dummy bytes in the txfifo */
s->cmd_dummies = xilinx_spips_num_dummies(q, tx);
addr_length = get_addr_length(s, tx);
if (s->cmd_dummies < 0) {
s->snoop_state = SNOOP_NONE;
} else {
s->snoop_state = SNOOP_ADDR + addr_length - 1;
}
switch (tx) {
case DPP:
case DOR:
case DOR_4:
s->link_state_next = 2;
s->link_state_next_when = addr_length + s->cmd_dummies;
break;
case QPP:
case QPP_4:
case QOR:
case QOR_4:
s->link_state_next = 4;
s->link_state_next_when = addr_length + s->cmd_dummies;
break;
case DIOR:
case DIOR_4:
s->link_state = 2;
break;
case QIOR:
case QIOR_4:
s->link_state = 4;
break;
}
break;
case (SNOOP_ADDR):
/* Address has been transmitted, transmit dummy cycles now if
* needed */
if (s->cmd_dummies < 0) {
s->snoop_state = SNOOP_NONE;
} else {
s->snoop_state = s->cmd_dummies;
}
break;
case (SNOOP_STRIPING):
case (SNOOP_NONE):
/* Once we hit the boring stuff - squelch debug noise */
if (!debug_level) {
DB_PRINT_L(0, "squelching debug info ....\n");
debug_level = 1;
}
break;
default:
s->snoop_state--;
}
DB_PRINT_L(debug_level, "final snoop state: %x\n",
(unsigned)s->snoop_state);
}
}
