static int uw2453_init_mode(struct zd_chip *chip) { static const u32 rv[] = { UW2453_REGWRITE(0, 0x25f98), /* enter IDLE mode */ UW2453_REGWRITE(0, 0x25f9a), /* enter CAL_VCO mode */ UW2453_REGWRITE(0, 0x25f94), /* enter RX/TX mode */ UW2453_REGWRITE(0, 0x27fd4), /* power down RSSI circuit */ }; return zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS); }
static int zd1211_al2230_set_channel(struct zd_rf *rf, u8 channel) { int r; const u32 *rv = zd1211_al2230_table[channel-1]; struct zd_chip *chip = zd_rf_to_chip(rf); static const struct zd_ioreq16 ioreqs[] = { { CR138, 0x28 }, { CR203, 0x06 }, }; r = zd_rfwritev_locked(chip, rv, 3, RF_RV_BITS); if (r) return r; return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); }
static int rf2959_init_hw(struct zd_rf *rf) { int r; struct zd_chip *chip = zd_rf_to_chip(rf); static const struct zd_ioreq16 ioreqs[] = { { ZD_CR2, 0x1E }, { ZD_CR9, 0x20 }, { ZD_CR10, 0x89 }, { ZD_CR11, 0x00 }, { ZD_CR15, 0xD0 }, { ZD_CR17, 0x68 }, { ZD_CR19, 0x4a }, { ZD_CR20, 0x0c }, { ZD_CR21, 0x0E }, { ZD_CR23, 0x48 }, /* normal size for cca threshold */ { ZD_CR24, 0x14 }, /* { ZD_CR24, 0x20 }, */ { ZD_CR26, 0x90 }, { ZD_CR27, 0x30 }, { ZD_CR29, 0x20 }, { ZD_CR31, 0xb2 }, { ZD_CR32, 0x43 }, { ZD_CR33, 0x28 }, { ZD_CR38, 0x30 }, { ZD_CR34, 0x0f }, { ZD_CR35, 0xF0 }, { ZD_CR41, 0x2a }, { ZD_CR46, 0x7F }, { ZD_CR47, 0x1E }, { ZD_CR51, 0xc5 }, { ZD_CR52, 0xc5 }, { ZD_CR53, 0xc5 }, { ZD_CR79, 0x58 }, { ZD_CR80, 0x30 }, { ZD_CR81, 0x30 }, { ZD_CR82, 0x00 }, { ZD_CR83, 0x24 }, { ZD_CR84, 0x04 }, { ZD_CR85, 0x00 }, { ZD_CR86, 0x10 }, { ZD_CR87, 0x2A }, { ZD_CR88, 0x10 }, { ZD_CR89, 0x24 }, { ZD_CR90, 0x18 }, /* { ZD_CR91, 0x18 }, */ /* should solve continuous CTS frame problems */ { ZD_CR91, 0x00 }, { ZD_CR92, 0x0a }, { ZD_CR93, 0x00 }, { ZD_CR94, 0x01 }, { ZD_CR95, 0x00 }, { ZD_CR96, 0x40 }, { ZD_CR97, 0x37 }, { ZD_CR98, 0x05 }, { ZD_CR99, 0x28 }, { ZD_CR100, 0x00 }, { ZD_CR101, 0x13 }, { ZD_CR102, 0x27 }, { ZD_CR103, 0x27 }, { ZD_CR104, 0x18 }, { ZD_CR105, 0x12 }, /* normal size */ { ZD_CR106, 0x1a }, /* { ZD_CR106, 0x22 }, */ { ZD_CR107, 0x24 }, { ZD_CR108, 0x0a }, { ZD_CR109, 0x13 }, { ZD_CR110, 0x2F }, { ZD_CR111, 0x27 }, { ZD_CR112, 0x27 }, { ZD_CR113, 0x27 }, { ZD_CR114, 0x27 }, { ZD_CR115, 0x40 }, { ZD_CR116, 0x40 }, { ZD_CR117, 0xF0 }, { ZD_CR118, 0xF0 }, { ZD_CR119, 0x16 }, /* no TX continuation */ { ZD_CR122, 0x00 }, /* { ZD_CR122, 0xff }, */ { ZD_CR127, 0x03 }, { ZD_CR131, 0x08 }, { ZD_CR138, 0x28 }, { ZD_CR148, 0x44 }, { ZD_CR150, 0x10 }, { ZD_CR169, 0xBB }, { ZD_CR170, 0xBB }, }; static const u32 rv[] = { 0x000007, /* REG0(CFG1) */ 0x07dd43, /* REG1(IFPLL1) */ 0x080959, /* REG2(IFPLL2) */ 0x0e6666, 0x116a57, /* REG4 */ 0x17dd43, /* REG5 */ 0x1819f9, /* REG6 */ 0x1e6666, 0x214554, 0x25e7fa, 0x27fffa, /* The Zydas driver somehow forgets to set this value. It's * only set for Japan. We are using internal power control * for now. */ 0x294128, /* internal power */ /* 0x28252c, */ /* External control TX power */ /* ZD_CR31_CCK, ZD_CR51_6-36M, ZD_CR52_48M, ZD_CR53_54M */ 0x2c0000, 0x300000, 0x340000, /* REG13(0xD) */ 0x381e0f, /* REG14(0xE) */ /* Bogus, RF2959's data sheet doesn't know register 27, which is * actually referenced here. The commented 0x11 is 17. */ 0x6c180f, /* REG27(0x11) */ }; r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); if (r) return r; return zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS); }
static int zd1211_al2230_init_hw(struct zd_rf *rf) { int r; struct zd_chip *chip = zd_rf_to_chip(rf); static const struct zd_ioreq16 ioreqs[] = { { CR15, 0x20 }, { CR23, 0x40 }, { CR24, 0x20 }, { CR26, 0x11 }, { CR28, 0x3e }, { CR29, 0x00 }, { CR44, 0x33 }, { CR106, 0x2a }, { CR107, 0x1a }, { CR109, 0x09 }, { CR110, 0x27 }, { CR111, 0x2b }, { CR112, 0x2b }, { CR119, 0x0a }, { CR10, 0x89 }, /* for newest (3rd cut) AL2300 */ { CR17, 0x28 }, { CR26, 0x93 }, { CR34, 0x30 }, /* for newest (3rd cut) AL2300 */ { CR35, 0x3e }, { CR41, 0x24 }, { CR44, 0x32 }, /* for newest (3rd cut) AL2300 */ { CR46, 0x96 }, { CR47, 0x1e }, { CR79, 0x58 }, { CR80, 0x30 }, { CR81, 0x30 }, { CR87, 0x0a }, { CR89, 0x04 }, { CR92, 0x0a }, { CR99, 0x28 }, { CR100, 0x00 }, { CR101, 0x13 }, { CR102, 0x27 }, { CR106, 0x24 }, { CR107, 0x2a }, { CR109, 0x09 }, { CR110, 0x13 }, { CR111, 0x1f }, { CR112, 0x1f }, { CR113, 0x27 }, { CR114, 0x27 }, /* for newest (3rd cut) AL2300 */ { CR115, 0x24 }, { CR116, 0x24 }, { CR117, 0xf4 }, { CR118, 0xfc }, { CR119, 0x10 }, { CR120, 0x4f }, { CR121, 0x77 }, { CR122, 0xe0 }, { CR137, 0x88 }, { CR252, 0xff }, { CR253, 0xff }, /* These following happen separately in the vendor driver */ { }, /* shdnb(PLL_ON)=0 */ { CR251, 0x2f }, /* shdnb(PLL_ON)=1 */ { CR251, 0x3f }, { CR138, 0x28 }, { CR203, 0x06 }, }; static const u32 rv[] = { /* Channel 1 */ 0x03f790, 0x033331, 0x00000d, 0x0b3331, 0x03b812, 0x00fff3, 0x000da4, 0x0f4dc5, /* fix freq shift, 0x04edc5 */ 0x0805b6, 0x011687, 0x000688, 0x0403b9, /* external control TX power (CR31) */ 0x00dbba, 0x00099b, 0x0bdffc, 0x00000d, 0x00500f, /* These writes happen separately in the vendor driver */ 0x00d00f, 0x004c0f, 0x00540f, 0x00700f, 0x00500f, }; r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); if (r) return r; r = zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS); if (r) return r; return 0; }
static int zd1211_al2230_init_hw(struct zd_rf *rf) { int r; struct zd_chip *chip = zd_rf_to_chip(rf); static const struct zd_ioreq16 ioreqs_init[] = { { ZD_CR15, 0x20 }, { ZD_CR23, 0x40 }, { ZD_CR24, 0x20 }, { ZD_CR26, 0x11 }, { ZD_CR28, 0x3e }, { ZD_CR29, 0x00 }, { ZD_CR44, 0x33 }, { ZD_CR106, 0x2a }, { ZD_CR107, 0x1a }, { ZD_CR109, 0x09 }, { ZD_CR110, 0x27 }, { ZD_CR111, 0x2b }, { ZD_CR112, 0x2b }, { ZD_CR119, 0x0a }, { ZD_CR10, 0x89 }, /* for newest (3rd cut) AL2300 */ { ZD_CR17, 0x28 }, { ZD_CR26, 0x93 }, { ZD_CR34, 0x30 }, /* for newest (3rd cut) AL2300 */ { ZD_CR35, 0x3e }, { ZD_CR41, 0x24 }, { ZD_CR44, 0x32 }, /* for newest (3rd cut) AL2300 */ { ZD_CR46, 0x96 }, { ZD_CR47, 0x1e }, { ZD_CR79, 0x58 }, { ZD_CR80, 0x30 }, { ZD_CR81, 0x30 }, { ZD_CR87, 0x0a }, { ZD_CR89, 0x04 }, { ZD_CR92, 0x0a }, { ZD_CR99, 0x28 }, { ZD_CR100, 0x00 }, { ZD_CR101, 0x13 }, { ZD_CR102, 0x27 }, { ZD_CR106, 0x24 }, { ZD_CR107, 0x2a }, { ZD_CR109, 0x09 }, { ZD_CR110, 0x13 }, { ZD_CR111, 0x1f }, { ZD_CR112, 0x1f }, { ZD_CR113, 0x27 }, { ZD_CR114, 0x27 }, /* for newest (3rd cut) AL2300 */ { ZD_CR115, 0x24 }, { ZD_CR116, 0x24 }, { ZD_CR117, 0xf4 }, { ZD_CR118, 0xfc }, { ZD_CR119, 0x10 }, { ZD_CR120, 0x4f }, { ZD_CR121, 0x77 }, { ZD_CR122, 0xe0 }, { ZD_CR137, 0x88 }, { ZD_CR252, 0xff }, { ZD_CR253, 0xff }, }; static const struct zd_ioreq16 ioreqs_pll[] = { /* shdnb(PLL_ON)=0 */ { ZD_CR251, 0x2f }, /* shdnb(PLL_ON)=1 */ { ZD_CR251, 0x3f }, { ZD_CR138, 0x28 }, { ZD_CR203, 0x06 }, }; static const u32 rv1[] = { /* Channel 1 */ 0x03f790, 0x033331, 0x00000d, 0x0b3331, 0x03b812, 0x00fff3, }; static const u32 rv2[] = { 0x000da4, 0x0f4dc5, /* fix freq shift, 0x04edc5 */ 0x0805b6, 0x011687, 0x000688, 0x0403b9, /* external control TX power (ZD_CR31) */ 0x00dbba, 0x00099b, 0x0bdffc, 0x00000d, 0x00500f, }; static const u32 rv3[] = { 0x00d00f, 0x004c0f, 0x00540f, 0x00700f, 0x00500f, }; r = zd_iowrite16a_locked(chip, ioreqs_init, ARRAY_SIZE(ioreqs_init)); if (r) return r; if (IS_AL2230S(chip)) { r = zd_iowrite16a_locked(chip, ioreqs_init_al2230s, ARRAY_SIZE(ioreqs_init_al2230s)); if (r) return r; } r = zd_rfwritev_locked(chip, rv1, ARRAY_SIZE(rv1), RF_RV_BITS); if (r) return r; /* improve band edge for AL2230S */ if (IS_AL2230S(chip)) r = zd_rfwrite_locked(chip, 0x000824, RF_RV_BITS); else r = zd_rfwrite_locked(chip, 0x0005a4, RF_RV_BITS); if (r) return r; r = zd_rfwritev_locked(chip, rv2, ARRAY_SIZE(rv2), RF_RV_BITS); if (r) return r; r = zd_iowrite16a_locked(chip, ioreqs_pll, ARRAY_SIZE(ioreqs_pll)); if (r) return r; r = zd_rfwritev_locked(chip, rv3, ARRAY_SIZE(rv3), RF_RV_BITS); if (r) return r; return 0; }
static int uw2453_init_hw(struct zd_rf *rf) { int i, r; int found_config = -1; u16 intr_status; struct zd_chip *chip = zd_rf_to_chip(rf); static const struct zd_ioreq16 ioreqs[] = { { CR10, 0x89 }, { CR15, 0x20 }, { CR17, 0x28 }, /* 6112 no change */ { CR23, 0x38 }, { CR24, 0x20 }, { CR26, 0x93 }, { CR27, 0x15 }, { CR28, 0x3e }, { CR29, 0x00 }, { CR33, 0x28 }, { CR34, 0x30 }, { CR35, 0x43 }, /* 6112 3e->43 */ { CR41, 0x24 }, { CR44, 0x32 }, { CR46, 0x92 }, /* 6112 96->92 */ { CR47, 0x1e }, { CR48, 0x04 }, /* 5602 Roger */ { CR49, 0xfa }, { CR79, 0x58 }, { CR80, 0x30 }, { CR81, 0x30 }, { CR87, 0x0a }, { CR89, 0x04 }, { CR91, 0x00 }, { CR92, 0x0a }, { CR98, 0x8d }, { CR99, 0x28 }, { CR100, 0x02 }, { CR101, 0x09 }, /* 6112 13->1f 6220 1f->13 6407 13->9 */ { CR102, 0x27 }, { CR106, 0x1c }, /* 5d07 5112 1f->1c 6220 1c->1f 6221 1f->1c */ { CR107, 0x1c }, /* 6220 1c->1a 5221 1a->1c */ { CR109, 0x13 }, { CR110, 0x1f }, /* 6112 13->1f 6221 1f->13 6407 13->0x09 */ { CR111, 0x13 }, { CR112, 0x1f }, { CR113, 0x27 }, { CR114, 0x23 }, /* 6221 27->23 */ { CR115, 0x24 }, /* 6112 24->1c 6220 1c->24 */ { CR116, 0x24 }, /* 6220 1c->24 */ { CR117, 0xfa }, /* 6112 fa->f8 6220 f8->f4 6220 f4->fa */ { CR118, 0xf0 }, /* 5d07 6112 f0->f2 6220 f2->f0 */ { CR119, 0x1a }, /* 6112 1a->10 6220 10->14 6220 14->1a */ { CR120, 0x4f }, { CR121, 0x1f }, /* 6220 4f->1f */ { CR122, 0xf0 }, { CR123, 0x57 }, { CR125, 0xad }, { CR126, 0x6c }, { CR127, 0x03 }, { CR128, 0x14 }, /* 6302 12->11 */ { CR129, 0x12 }, /* 6301 10->0f */ { CR130, 0x10 }, { CR137, 0x50 }, { CR138, 0xa8 }, { CR144, 0xac }, { CR146, 0x20 }, { CR252, 0xff }, { CR253, 0xff }, }; static const u32 rv[] = { UW2453_REGWRITE(4, 0x2b), /* configure reciever gain */ UW2453_REGWRITE(5, 0x19e4f), /* configure transmitter gain */ UW2453_REGWRITE(6, 0xf81ad), /* enable RX/TX filter tuning */ UW2453_REGWRITE(7, 0x3fffe), /* disable TX gain in test mode */ /* enter CAL_FIL mode, TX gain set by registers, RX gain set by pins, * RSSI circuit powered down, reduced RSSI range */ UW2453_REGWRITE(0, 0x25f9c), /* 5d01 cal_fil */ /* synthesizer configuration for channel 1 */ UW2453_REGWRITE(1, 0x47), UW2453_REGWRITE(2, 0x999), /* disable manual VCO band selection */ UW2453_REGWRITE(3, 0x7602), /* enable manual VCO band selection, configure current level */ UW2453_REGWRITE(3, 0x46063), }; r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); if (r) return r; r = zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS); if (r) return r; r = uw2453_init_mode(chip); if (r) return r; /* Try all standard VCO configuration settings on channel 1 */ for (i = 0; i < ARRAY_SIZE(uw2453_std_vco_cfg) - 1; i++) { /* Configure synthesizer for channel 1 */ r = uw2453_synth_set_channel(chip, 1, false); if (r) return r; /* Write VCO config */ r = uw2453_write_vco_cfg(chip, uw2453_std_vco_cfg[i][0]); if (r) return r; /* ack interrupt event */ r = zd_iowrite16_locked(chip, 0x0f, UW2453_INTR_REG); if (r) return r; /* check interrupt status */ r = zd_ioread16_locked(chip, &intr_status, UW2453_INTR_REG); if (r) return r; if (!(intr_status & 0xf)) { dev_dbg_f(zd_chip_dev(chip), "PLL locked on configuration %d\n", i); found_config = i; break; } } if (found_config == -1) { /* autocal */ dev_dbg_f(zd_chip_dev(chip), "PLL did not lock, using autocal\n"); r = uw2453_synth_set_channel(chip, 1, true); if (r) return r; r = uw2453_write_vco_cfg(chip, UW2453_AUTOCAL_VCO_CFG); if (r) return r; } /* To match the vendor driver behaviour, we use the configuration after * the one that produced a lock. */ UW2453_PRIV(rf)->config = found_config + 1; return zd_iowrite16_locked(chip, 0x06, CR203); }
static int zd1211b_al2230_init_hw(struct zd_rf *rf) { int r; struct zd_chip *chip = zd_rf_to_chip(rf); static const struct zd_ioreq16 ioreqs1[] = { { CR10, 0x89 }, { CR15, 0x20 }, { CR17, 0x2B }, /* for newest(3rd cut) AL2230 */ { CR23, 0x40 }, { CR24, 0x20 }, { CR26, 0x93 }, { CR28, 0x3e }, { CR29, 0x00 }, { CR33, 0x28 }, /* 5621 */ { CR34, 0x30 }, { CR35, 0x3e }, /* for newest(3rd cut) AL2230 */ { CR41, 0x24 }, { CR44, 0x32 }, { CR46, 0x99 }, /* for newest(3rd cut) AL2230 */ { CR47, 0x1e }, /* ZD1211B 05.06.10 */ { CR48, 0x00 }, { CR49, 0x00 }, { CR51, 0x01 }, { CR52, 0x80 }, { CR53, 0x7e }, { CR65, 0x00 }, { CR66, 0x00 }, { CR67, 0x00 }, { CR68, 0x00 }, { CR69, 0x28 }, { CR79, 0x58 }, { CR80, 0x30 }, { CR81, 0x30 }, { CR87, 0x0a }, { CR89, 0x04 }, { CR91, 0x00 }, /* 5621 */ { CR92, 0x0a }, { CR98, 0x8d }, /* 4804, for 1212 new algorithm */ { CR99, 0x00 }, /* 5621 */ { CR101, 0x13 }, { CR102, 0x27 }, { CR106, 0x24 }, /* for newest(3rd cut) AL2230 */ { CR107, 0x2a }, { CR109, 0x13 }, /* 4804, for 1212 new algorithm */ { CR110, 0x1f }, /* 4804, for 1212 new algorithm */ { CR111, 0x1f }, { CR112, 0x1f }, { CR113, 0x27 }, { CR114, 0x27 }, { CR115, 0x26 }, /* 24->26 at 4902 for newest(3rd cut) AL2230 */ { CR116, 0x24 }, { CR117, 0xfa }, /* for 1211b */ { CR118, 0xfa }, /* for 1211b */ { CR119, 0x10 }, { CR120, 0x4f }, { CR121, 0x6c }, /* for 1211b */ { CR122, 0xfc }, /* E0->FC at 4902 */ { CR123, 0x57 }, /* 5623 */ { CR125, 0xad }, /* 4804, for 1212 new algorithm */ { CR126, 0x6c }, /* 5614 */ { CR127, 0x03 }, /* 4804, for 1212 new algorithm */ { CR137, 0x50 }, /* 5614 */ { CR138, 0xa8 }, { CR144, 0xac }, /* 5621 */ { CR150, 0x0d }, { CR252, 0x00 }, { CR253, 0x00 }, }; static const u32 rv1[] = { /* channel 1 */ 0x03f790, 0x033331, 0x00000d, 0x0b3331, 0x03b812, 0x00fff3, 0x0005a4, 0x0f4dc5, /* fix freq shift 0x044dc5 */ 0x0805b6, 0x0146c7, 0x000688, 0x0403b9, /* External control TX power (CR31) */ 0x00dbba, 0x00099b, 0x0bdffc, 0x00000d, 0x00580f, }; static const struct zd_ioreq16 ioreqs2[] = { { CR47, 0x1e }, { CR_RFCFG, 0x03 }, }; static const u32 rv2[] = { 0x00880f, 0x00080f, }; static const struct zd_ioreq16 ioreqs3[] = { { CR_RFCFG, 0x00 }, { CR47, 0x1e }, { CR251, 0x7f }, }; static const u32 rv3[] = { 0x00d80f, 0x00780f, 0x00580f, }; static const struct zd_ioreq16 ioreqs4[] = { { CR138, 0x28 }, { CR203, 0x06 }, }; r = zd_iowrite16a_locked(chip, ioreqs1, ARRAY_SIZE(ioreqs1)); if (r) return r; r = zd_rfwritev_locked(chip, rv1, ARRAY_SIZE(rv1), RF_RV_BITS); if (r) return r; r = zd_iowrite16a_locked(chip, ioreqs2, ARRAY_SIZE(ioreqs2)); if (r) return r; r = zd_rfwritev_locked(chip, rv2, ARRAY_SIZE(rv2), RF_RV_BITS); if (r) return r; r = zd_iowrite16a_locked(chip, ioreqs3, ARRAY_SIZE(ioreqs3)); if (r) return r; r = zd_rfwritev_locked(chip, rv3, ARRAY_SIZE(rv3), RF_RV_BITS); if (r) return r; return zd_iowrite16a_locked(chip, ioreqs4, ARRAY_SIZE(ioreqs4)); }