int32_t CenMbaTdCtlrCommon::cleanupPrevCmd() { #define PRDF_FUNC "[CenMbaTdCtlrCommon::cleanupPrevCmd] " int32_t o_rc = SUCCESS; // Clean up the current maintenance command. This must be done whenever // maintenance command will no longer be executed. if ( NULL != iv_mssCmd ) { o_rc = iv_mssCmd->cleanupCmd(); if ( SUCCESS != o_rc ) PRDF_ERR( PRDF_FUNC "cleanupCmd() failed" ); delete iv_mssCmd; iv_mssCmd = NULL; } // Clear the command complete attention. This must be done before starting // the next maintenance command. SCAN_COMM_REGISTER_CLASS * firand = iv_mbaChip->getRegister("MBASPA_AND"); firand->setAllBits(); firand->ClearBit(0); // Maintenance command complete firand->ClearBit(8); // Maintenance command complete (DD1.0 workaround) if ( SUCCESS != firand->Write() ) { PRDF_ERR( PRDF_FUNC "Write() failed on MBASPA_AND" ); o_rc = FAIL; } return o_rc; #undef PRDF_FUNC }
int32_t CenMbaTdCtlrCommon::chipMarkCleanup() { #define PRDF_FUNC "[CenMbaTdCtlrCommon::chipMarkCleanup] " int32_t o_rc = SUCCESS; do { SCAN_COMM_REGISTER_CLASS * ddrPhyAndFir = iv_mbaChip->getRegister( "MBADDRPHYFIR_AND" ); ddrPhyAndFir->setAllBits(); ddrPhyAndFir->ClearBit(50); // Calibration Error RE 0 ddrPhyAndFir->ClearBit(58); // Calibration Error RE 1 o_rc = ddrPhyAndFir->Write(); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "Write() failed on MBADDRPHYFIR_AND" ); break; } } while(0); return o_rc; #undef PRDF_FUNC }
/** * @brief Captures trapped address for L4 cache ECC errors. * @param i_mbChip Centaur chip * @param i_sc Step code data struct * @returns SUCCESS always * @note This function also reset ECC trapped address regsiters so that HW * can capture address for next L4 ecc error. */ int32_t CaptureL4CacheErr( ExtensibleChip * i_mbChip, STEP_CODE_DATA_STRUCT & i_sc ) { #define PRDF_FUNC "[CaptureL4CacheErr] " do { i_mbChip->CaptureErrorData( i_sc.service_data->GetCaptureData(), Util::hashString( "L4CacheErr" ) ); // NOTE: FW should write on MBCELOG so that HW can capture // address for next L4 CE error. SCAN_COMM_REGISTER_CLASS * mbcelogReg = i_mbChip->getRegister("MBCELOG"); mbcelogReg->clearAllBits(); if ( SUCCESS != mbcelogReg->Write() ) { PRDF_ERR( PRDF_FUNC"MBCELOG write failed for 0x%08x", i_mbChip->GetId()); break; } }while( 0 ); return SUCCESS; }
/** * @fn MaskMbaCalSecondaryBits * @brief Mask MBACAL secondary Fir bits which may come up because of L4 UE. * @param i_chip The Centaur chip. * @param i_sc ServiceDataColector. * @return SUCCESS. */ int32_t MaskMbaCalSecondaryBits( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & i_sc ) { #define PRDF_FUNC "[MaskMbaCalSecondaryBits ] " int32_t l_rc = SUCCESS; do { CenMembufDataBundle * membdb = getMembufDataBundle( i_chip ); for( uint32_t i = 0; i < MAX_MBA_PER_MEMBUF; i++ ) { ExtensibleChip * mbaChip = membdb->getMbaChip(i); if ( NULL == mbaChip ) continue; SCAN_COMM_REGISTER_CLASS * mbaCalFirMaskOr = mbaChip->getRegister("MBACALFIR_MASK_OR"); mbaCalFirMaskOr->SetBit(9); mbaCalFirMaskOr->SetBit(15); l_rc = mbaCalFirMaskOr->Write(); if ( SUCCESS != l_rc ) { // Do not break. Just print error trace and look for // other MBA. PRDF_ERR( PRDF_FUNC"MBACALFIR_MASK_OR write failed" "for 0x%08x", mbaChip->GetId()); } } }while( 0 ); return SUCCESS; #undef PRDF_FUNC } PRDF_PLUGIN_DEFINE( Membuf, MaskMbaCalSecondaryBits );
/** * @fn MaskMbsSecondaryBits * @brief Mask MBS secondary Fir bits which may come up because of L4 UE. * @param i_chip The Centaur chip. * @param i_sc ServiceDataColector. * @return SUCCESS. */ int32_t MaskMbsSecondaryBits( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & i_sc ) { #define PRDF_FUNC "[MaskMbsSecondaryBits] " int32_t l_rc = SUCCESS; do { SCAN_COMM_REGISTER_CLASS * mbsFirMaskOr = i_chip->getRegister("MBSFIR_MASK_OR"); mbsFirMaskOr->SetBit(27); l_rc = mbsFirMaskOr->Write(); if ( SUCCESS != l_rc ) { PRDF_ERR( PRDF_FUNC"MBSFIR_MASK_OR write failed" "for 0x%08x", i_chip->GetId()); break; } }while( 0 ); return SUCCESS; #undef PRDF_FUNC } PRDF_PLUGIN_DEFINE( Membuf, MaskMbsSecondaryBits );
int32_t CenMbaTdCtlrCommon::setRtEteThresholds() { #define PRDF_FUNC "[CenMbaTdCtlrCommon::setRtEteThresholds] " int32_t o_rc = SUCCESS; do { const char * reg_str = (0 == iv_mbaPos) ? "MBA0_MBSTR" : "MBA1_MBSTR"; SCAN_COMM_REGISTER_CLASS * mbstr = iv_membChip->getRegister( reg_str ); // MBSTR's content could be modified from cleanupCmd() // so we need to refresh o_rc = mbstr->ForceRead(); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "ForceRead() failed on %s", reg_str ); break; } uint16_t softIntCe = 0; o_rc = getScrubCeThreshold( iv_mbaChip, iv_rank, softIntCe ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "getScrubCeThreshold() failed." ); break; } // Only care about retry CEs if there are a lot of them. So the // threshold will be high in the field. However, in MNFG the retry CEs // will be handled differently by putting every occurrence in the RCE // table and doing targeted diagnostics when needed. uint16_t retryCe = mfgMode() ? 1 : 2047; uint16_t hardCe = 1; // Always stop on first occurrence. mbstr->SetBitFieldJustified( 4, 12, softIntCe ); mbstr->SetBitFieldJustified( 16, 12, softIntCe ); mbstr->SetBitFieldJustified( 28, 12, hardCe ); mbstr->SetBitFieldJustified( 40, 12, retryCe ); // Set the per symbol counters to count hard CEs only. This is so that // when the scrub stops on the first hard CE, we can use the per symbol // counters to tell us which symbol reported the hard CE. mbstr->SetBitFieldJustified( 55, 3, 0x1 ); o_rc = mbstr->Write(); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "Write() failed on %s", reg_str ); break; } } while(0); return o_rc; #undef PRDF_FUNC }
/** * @brief Plugin to mask the side effects of an RCD parity error * @param i_mbaChip A Centaur MBA chip. * @param i_sc The step code data struct. * @return SUCCESS */ int32_t maskRcdParitySideEffects( ExtensibleChip * i_mbaChip, STEP_CODE_DATA_STRUCT & i_sc ) { #define PRDF_FUNC "[maskRcdParitySideEffects] " int32_t l_rc = SUCCESS; do { //use a data bundle to get the membuf chip CenMbaDataBundle * mbadb = getMbaDataBundle( i_mbaChip ); ExtensibleChip * membChip = mbadb->getMembChip(); if (NULL == membChip) { PRDF_ERR(PRDF_FUNC "getMembChip() failed"); break; } //get the masks for each FIR SCAN_COMM_REGISTER_CLASS * mbsFirMaskOr = membChip->getRegister("MBSFIR_MASK_OR"); SCAN_COMM_REGISTER_CLASS * mbaCalMaskOr = i_mbaChip->getRegister("MBACALFIR_MASK_OR"); SCAN_COMM_REGISTER_CLASS * mbaFirMaskOr = i_mbaChip->getRegister("MBAFIR_MASK_OR"); mbaFirMaskOr->SetBit(2); mbaCalMaskOr->SetBit(2); mbaCalMaskOr->SetBit(17); mbsFirMaskOr->SetBit(4); l_rc = mbaFirMaskOr->Write(); l_rc |= mbaCalMaskOr->Write(); l_rc |= mbsFirMaskOr->Write(); if (SUCCESS != l_rc) { PRDF_ERR(PRDF_FUNC "MBAFIR_MASK_OR/MBACALFIR_MASK_OR/MBSFIR_MASK_OR" " write failed for 0x%08x", i_mbaChip->GetId()); break; } }while(0); return SUCCESS; #undef PRDF_FUNC }
// Do the setup for mnfg IPL CE int32_t CenMbaTdCtlr::mnfgCeSetup() { #define PRDF_FUNC "[CenMbaTdCtlr::mnfgCeSetup] " int32_t o_rc = SUCCESS; do { const char * reg_str = (0 == iv_mbaPos) ? "MBA0_MBSTR" : "MBA1_MBSTR"; SCAN_COMM_REGISTER_CLASS * mbstr = iv_membChip->getRegister( reg_str ); // MBSTR's content could be modified from cleanupCmd() // so we need to refresh o_rc = mbstr->ForceRead(); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC"Read() failed on %s", reg_str ); break; } if ( TPS_PHASE_1 == iv_tdState ) { // Enable per-symbol error counters to count soft CEs mbstr->SetBit(55); mbstr->SetBit(56); // Disable per-symbol error counters to count hard CEs mbstr->ClearBit(57); } else if ( TPS_PHASE_2 == iv_tdState ) { // Disable per-symbol error counters to count soft CEs mbstr->ClearBit(55); mbstr->ClearBit(56); // Enable per-symbol error counters to count hard CEs mbstr->SetBit(57); } else { PRDF_ERR( PRDF_FUNC"Inavlid State:%u", iv_tdState ); o_rc = FAIL; break; } o_rc = mbstr->Write(); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC"Write() failed on %s", reg_str ); break; } } while(0); return o_rc; #undef PRDF_FUNC }
int32_t clearPerSymbolCounters( ExtensibleChip * i_membChip, uint32_t i_mbaPos ) { #define PRDF_FUNC "[MemUtils::clearPerSymbolCounters] " int32_t o_rc = SUCCESS; do { if ( MAX_MBA_PER_MEMBUF <= i_mbaPos ) { PRDF_ERR( PRDF_FUNC "i_mbaPos %d is invalid", i_mbaPos ); o_rc = FAIL; break; } const char * reg_str = NULL; SCAN_COMM_REGISTER_CLASS * reg = NULL; for ( uint8_t regIdx = 0; regIdx < CE_REGS_PER_MBA; regIdx++ ) { reg_str = mbsCeStatReg[i_mbaPos][regIdx]; reg = i_membChip->getRegister( reg_str ); reg->clearAllBits(); o_rc = reg->Write(); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "Write() failed on %s", reg_str ); break; } } if ( SUCCESS != o_rc ) break; } while(0); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "Failed. i_membChip=0x%08x i_mbaPos=%d", i_membChip->GetId(), i_mbaPos ); } return o_rc; #undef PRDF_FUNC }
int32_t chnlCsCleanup( ExtensibleChip *i_mbChip, STEP_CODE_DATA_STRUCT & i_sc ) { #define PRDF_FUNC "[MemUtils::chnlCsCleanup] " int32_t o_rc = SUCCESS; do { if( ( NULL == i_mbChip ) || ( TYPE_MEMBUF != getTargetType( i_mbChip->GetChipHandle() ))) { PRDF_ERR( PRDF_FUNC "Invalid parameters" ); o_rc = FAIL; break; } if (( ! i_sc.service_data->IsUnitCS() ) || (CHECK_STOP == i_sc.service_data->getPrimaryAttnType()) ) break; CenMembufDataBundle * mbdb = getMembufDataBundle( i_mbChip ); if ( !mbdb->iv_doChnlFailCleanup ) break; // Cleanup has already been done. // Set it as SUE generation point. i_sc.service_data->SetFlag( ServiceDataCollector::UERE ); ExtensibleChip * mcsChip = mbdb->getMcsChip(); if ( NULL == mcsChip ) { PRDF_ERR( PRDF_FUNC "MCS chip is NULL for Membuf:0x%08X", i_mbChip->GetId() ); o_rc = FAIL; break; } TargetHandle_t mcs = mcsChip->GetChipHandle(); ExtensibleChip * procChip = NULL; uint8_t pos = getTargetPosition( mcs ); TargetHandle_t proc = getParentChip ( mcs ); if ( NULL == proc ) { PRDF_ERR( PRDF_FUNC "Proc is NULL for Mcs:0x%08X", getHuid( mcs ) ); o_rc = FAIL; break; } procChip = (ExtensibleChip *)systemPtr->GetChip( proc ); if( NULL == procChip ) { PRDF_ERR( PRDF_FUNC "Can not find Proc chip for HUID:0x%08X", getHuid( proc) ); o_rc = FAIL; break; } // This is a cleanup function. If we get any error from scom // operations, we will still continue with cleanup. SCAN_COMM_REGISTER_CLASS * l_tpMask = procChip->getRegister("TP_CHIPLET_FIR_MASK"); o_rc |= l_tpMask->Read(); if ( SUCCESS == o_rc ) { // Bits 5-12 maps to attentions from MCS0-MCS7. l_tpMask->SetBit( 5 + pos ); o_rc |= l_tpMask->Write(); } // Mask attentions from the Centaur const char *iomcFirMask = ( pos < 4 )? "IOMCFIR_0_MASK_OR":"IOMCFIR_1_MASK_OR"; SCAN_COMM_REGISTER_CLASS * iomcMask = procChip->getRegister( iomcFirMask); if ( pos >= 4 ) pos -= 4; // 8 bits are reserved for each Centaur in IOMCFIR. // There are total 4 ( for P system ) centaur supported // in MCS. Bits for first centaur starts from bit 8. iomcMask->SetBitFieldJustified( 8+ ( pos*8 ), 8, 0xff); o_rc |= iomcMask->Write(); SCAN_COMM_REGISTER_CLASS * l_tpfirmask = NULL; SCAN_COMM_REGISTER_CLASS * l_nestfirmask = NULL; SCAN_COMM_REGISTER_CLASS * l_memfirmask = NULL; SCAN_COMM_REGISTER_CLASS * l_memspamask = NULL; l_tpfirmask = i_mbChip->getRegister("TP_CHIPLET_FIR_MASK"); l_nestfirmask = i_mbChip->getRegister("NEST_CHIPLET_FIR_MASK"); l_memfirmask = i_mbChip->getRegister("MEM_CHIPLET_FIR_MASK"); l_memspamask = i_mbChip->getRegister("MEM_CHIPLET_SPA_MASK"); l_tpfirmask->setAllBits(); o_rc |= l_tpfirmask->Write(); l_nestfirmask->setAllBits(); o_rc |= l_nestfirmask->Write(); l_memfirmask->setAllBits(); o_rc |= l_memfirmask->Write(); l_memspamask->setAllBits(); o_rc |= l_memspamask->Write(); for ( uint32_t i = 0; i < MAX_MBA_PER_MEMBUF; i++ ) { ExtensibleChip * mbaChip = mbdb->getMbaChip( i ); if( NULL != mbaChip ) { TargetHandle_t mba = mbaChip->GetChipHandle(); if ( NULL != mba ) { #if defined(__HOSTBOOT_MODULE) && \ !defined(__HOSTBOOT_RUNTIME) // This is very small platform specific code. So not // creating a separate file for this. int32_t l_rc = mdiaSendEventMsg( mba, MDIA::SKIP_MBA ); if ( SUCCESS != l_rc ) { PRDF_ERR( PRDF_FUNC "mdiaSendEventMsg(0x%08x, SKIP_MBA) " "failed", getHuid( mba ) ); o_rc |= l_rc; } #else int32_t l_rc = DEALLOC::mbaGard( mbaChip ); if ( SUCCESS != l_rc ) { PRDF_ERR( PRDF_FUNC "mbaGard failed. HUID: 0x%08x", getHuid( mba ) ); o_rc |= l_rc; } #endif // __HOSTBOOT_MODULE } } } // Clean up complete an is no longer required. mbdb->iv_doChnlFailCleanup = false; } while(0); return o_rc; #undef PRDF_FUNC }
int32_t CenMbaTdCtlrCommon::prepareNextCmd( bool i_clearStats ) { #define PRDF_FUNC "[CenMbaTdCtlrCommon::prepareNextCmd] " int32_t o_rc = SUCCESS; do { //---------------------------------------------------------------------- // Clean up previous command //---------------------------------------------------------------------- o_rc = cleanupPrevCmd(); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "cleanupPrevCmd() failed" ); break; } //---------------------------------------------------------------------- // Clear ECC counters //---------------------------------------------------------------------- const char * reg_str = NULL; if ( i_clearStats ) { reg_str = (0 == iv_mbaPos) ? "MBA0_MBSTR" : "MBA1_MBSTR"; SCAN_COMM_REGISTER_CLASS * mbstr = iv_membChip->getRegister( reg_str ); // MBSTR's content could be modified from cleanupCmd() // so we need to refresh o_rc = mbstr->ForceRead(); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "ForceRead() failed on %s", reg_str ); break; } mbstr->SetBit(53); // Setting this bit clears all counters. o_rc = mbstr->Write(); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "Write() failed on %s", reg_str ); break; } // Hardware automatically clears bit 53, so flush this register out // of the register cache to avoid clearing the counters again with // a write from the out-of-date cached copy. RegDataCache & cache = RegDataCache::getCachedRegisters(); cache.flush( iv_membChip, mbstr ); } //---------------------------------------------------------------------- // Clear ECC FIRs //---------------------------------------------------------------------- reg_str = (0 == iv_mbaPos) ? "MBA0_MBSECCFIR_AND" : "MBA1_MBSECCFIR_AND"; SCAN_COMM_REGISTER_CLASS * firand = iv_membChip->getRegister( reg_str ); firand->setAllBits(); // Clear all scrub MPE bits. // This will need to be done when starting a TD procedure or background // scrubbing. iv_rank may not be set when starting background scrubbing // and technically there should only be one of these MPE bits on at a // time so we should not have to worry about losing an attention by // clearing them all. firand->SetBitFieldJustified( 20, 8, 0 ); // Clear scrub NCE, SCE, MCE, RCE, SUE, UE bits (36-41) firand->SetBitFieldJustified( 36, 6, 0 ); o_rc = firand->Write(); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "Write() failed on %s", reg_str ); break; } SCAN_COMM_REGISTER_CLASS * spaAnd = iv_mbaChip->getRegister("MBASPA_AND"); spaAnd->setAllBits(); // Clear threshold exceeded attentions spaAnd->SetBitFieldJustified( 1, 4, 0 ); o_rc = spaAnd->Write(); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "Write() failed on MBASPA_AND" ); break; } } while (0); return o_rc; #undef PRDF_FUNC }
/** * @brief Mask the PLL error for P8 Plugin * @param i_chip P8 chip * @param i_sc The step code data struct * @param i_oscPos active osc position * @returns Failure or Success of query. * @note */ int32_t MaskPllIo( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & i_sc, uint32_t i_oscPos ) { #define PRDF_FUNC "[Proc::MaskPllIo] " int32_t rc = SUCCESS; do { if (CHECK_STOP == i_sc.service_data->getPrimaryAttnType()) { break; } if ( i_oscPos >= MAX_PCIE_OSC_PER_NODE ) { PRDF_ERR(PRDF_FUNC "invalid oscPos: %d for chip: " "0x%08x", i_oscPos, i_chip->GetId()); rc = FAIL; break; } uint32_t oscPos = getIoOscPos( i_chip, i_sc ); if ( oscPos != i_oscPos ) { PRDF_DTRAC(PRDF_FUNC "skip masking for chip: 0x%08x, " "oscPos: %d, i_oscPos: %d", i_chip->GetId(), oscPos, i_oscPos); break; } // fence off pci osc error reg bit SCAN_COMM_REGISTER_CLASS * pciConfigReg = i_chip->getRegister("PCI_CONFIG_REG"); rc = pciConfigReg->Read(); if (rc != SUCCESS) { PRDF_ERR(PRDF_FUNC "PCI_CONFIG_REG read failed" "for 0x%08x", i_chip->GetId()); break; } if(!pciConfigReg->IsBitSet(PLL_ERROR_MASK)) { pciConfigReg->SetBit(PLL_ERROR_MASK); rc = pciConfigReg->Write(); if (rc != SUCCESS) { PRDF_ERR(PRDF_FUNC "PCI_CONFIG_REG write failed" "for chip: 0x%08x", i_chip->GetId()); } } // Since TP_LFIR bit is the collection of all of the // pll error reg bits, we can't mask it or we will not // see any PLL errors reported from the error regs } while(0); return rc; #undef PRDF_FUNC }
/** * @brief Clear the PLL error for P8 Plugin * @param i_chip P8 chip * @param i_sc The step code data struct * @returns Failure or Success of query. */ int32_t ClearPllIo( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & i_sc) { #define PRDF_FUNC "[Proc::ClearPllIo] " int32_t rc = SUCCESS; if (CHECK_STOP != i_sc.service_data->getPrimaryAttnType()) { // Clear pci osc error reg bit int32_t tmpRC = SUCCESS; SCAN_COMM_REGISTER_CLASS * pciErrReg = i_chip->getRegister("PCI_ERROR_REG"); tmpRC = pciErrReg->Read(); if (tmpRC != SUCCESS) { PRDF_ERR(PRDF_FUNC "PCI_ERROR_REG read failed" "for chip: 0x%08x", i_chip->GetId()); rc |= tmpRC; } if( pciErrReg->IsBitSet( PLL_ERROR_BIT ) ) { pciErrReg->clearAllBits(); pciErrReg->SetBit(PLL_ERROR_BIT); tmpRC = pciErrReg->Write(); if ( SUCCESS != tmpRC ) { PRDF_ERR( PRDF_FUNC "Write() failed on PCI Error register: " "proc=0x%08x", i_chip->GetId() ); rc |= tmpRC; } } // Clear TP_LFIR SCAN_COMM_REGISTER_CLASS * TP_LFIRand = i_chip->getRegister("TP_LFIR_AND"); TP_LFIRand->setAllBits(); TP_LFIRand->ClearBit(PLL_DETECT_P8); tmpRC = TP_LFIRand->Write(); if (tmpRC != SUCCESS) { PRDF_ERR(PRDF_FUNC "TP_LFIR_AND write failed" "for chip: 0x%08x", i_chip->GetId()); rc |= tmpRC; } SCAN_COMM_REGISTER_CLASS * oscCerrReg = i_chip->getRegister("OSCERR"); tmpRC = oscCerrReg->Read(); if (tmpRC != SUCCESS) { PRDF_ERR(PRDF_FUNC "OSCERR read failed" "for 0x%08x", i_chip->GetId()); rc |= tmpRC; } oscCerrReg->ClearBit(4); oscCerrReg->ClearBit(5); tmpRC = oscCerrReg->Write(); if (tmpRC != SUCCESS) { PRDF_ERR(PRDF_FUNC "oscCerrReg write failed" "for chip: 0x%08x", i_chip->GetId()); rc |= tmpRC; } } if( rc != SUCCESS ) { PRDF_ERR(PRDF_FUNC "failed for proc: 0x%.8X", i_chip->GetId()); } return rc; #undef PRDF_FUNC }
/** * @fn ClearMbaCalSecondaryBits * @brief Clears MBACAL secondary Fir bits which may come up because of MBSFIR * @param i_chip The Centaur chip. * @param i_sc ServiceDataColector. * @return SUCCESS. */ int32_t ClearMbaCalSecondaryBits( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & i_sc ) { #define PRDF_FUNC "[ClearMbaCalSecondaryBits ] " int32_t l_rc = SUCCESS; do { SCAN_COMM_REGISTER_CLASS * mbsFir = i_chip->getRegister("MBSFIR"); SCAN_COMM_REGISTER_CLASS * mbsFirMask = i_chip->getRegister("MBSFIR_MASK"); l_rc = mbsFir->Read(); l_rc |= mbsFirMask->Read(); if ( SUCCESS != l_rc ) { PRDF_ERR( PRDF_FUNC"MBSFIR/MBSFIR_MASK read failed" "for 0x%08x", i_chip->GetId()); break; } CenMembufDataBundle * membdb = getMembufDataBundle( i_chip ); for( uint32_t i = 0; i < MAX_MBA_PER_MEMBUF; i++ ) { ExtensibleChip * mbaChip = membdb->getMbaChip(i); if ( NULL == mbaChip ) continue; SCAN_COMM_REGISTER_CLASS * mbaCalFir = mbaChip->getRegister("MBACALFIR"); if( SUCCESS != mbaCalFir->Read() ) { // Do not break. Just print error trace and look for // other MBA. PRDF_ERR( PRDF_FUNC"MBACALFIR read failed" "for 0x%08x", mbaChip->GetId()); continue; } if( !( mbaCalFir->IsBitSet( 10 ) || mbaCalFir->IsBitSet( 14 ) )) continue; SCAN_COMM_REGISTER_CLASS * mbaCalAndFir = mbaChip->getRegister("MBACALFIR_AND"); mbaCalAndFir->setAllBits(); mbaCalAndFir->ClearBit(10); mbaCalAndFir->ClearBit(14); l_rc = mbaCalAndFir->Write(); if ( SUCCESS != l_rc ) { // Do not break. Just print error trace and look for // other MBA. PRDF_ERR( PRDF_FUNC"MBACALFIR_AND write failed" "for 0x%08x", mbaChip->GetId()); } } }while( 0 ); return SUCCESS; #undef PRDF_FUNC } PRDF_PLUGIN_DEFINE( Membuf, ClearMbaCalSecondaryBits );
/** * @fn ClearMbsSecondaryBits * @brief Clears MBS secondary Fir bits which may come up because of primary * MBS/MBI FIR bits. * @param i_chip The Centaur chip. * @param i_sc ServiceDataColector. * @return SUCCESS. */ int32_t ClearMbsSecondaryBits( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & i_sc ) { #define PRDF_FUNC "[ClearMbsSecondaryBits] " int32_t l_rc = SUCCESS; do { SCAN_COMM_REGISTER_CLASS * mbsFir = i_chip->getRegister("MBSFIR"); SCAN_COMM_REGISTER_CLASS * mbsFirMask = i_chip->getRegister("MBSFIR_MASK"); SCAN_COMM_REGISTER_CLASS * mbsFirAnd = i_chip->getRegister("MBSFIR_AND"); l_rc = mbsFir->Read(); l_rc |= mbsFirMask->Read(); if ( SUCCESS != l_rc ) { PRDF_ERR( PRDF_FUNC"MBSFIR/MBSFIR_MASK read failed" "for 0x%08x", i_chip->GetId()); break; } mbsFirAnd->setAllBits(); if ( mbsFir->IsBitSet(26) && mbsFir->IsBitSet(9) && ( ! mbsFirMask->IsBitSet(9))) { mbsFirAnd->ClearBit(26); } if( mbsFir->IsBitSet(3) || mbsFir->IsBitSet(4) ) { SCAN_COMM_REGISTER_CLASS * mbiFir = i_chip->getRegister("MBIFIR"); SCAN_COMM_REGISTER_CLASS * mbiFirMask = i_chip->getRegister("MBIFIR_MASK"); l_rc = mbiFir->Read(); l_rc |= mbiFirMask->Read(); if ( SUCCESS != l_rc ) { // Do not break from here, just print error trace. // If there are other secondary bits ( e.g. 26, 27 ), // we want to clear them. PRDF_ERR( PRDF_FUNC"MBIFIR/MASK read failed" "for 0x%08x", i_chip->GetId()); } else if ( mbiFir->IsBitSet( 0 ) && ( ! mbiFirMask->IsBitSet( 0 )) ) { mbsFirAnd->ClearBit(3); mbsFirAnd->ClearBit(4); } } l_rc = mbsFirAnd->Write(); if ( SUCCESS != l_rc ) { PRDF_ERR( PRDF_FUNC"MBSFIR_AND write failed" "for 0x%08x", i_chip->GetId()); break; } }while( 0 ); return SUCCESS; #undef PRDF_FUNC } PRDF_PLUGIN_DEFINE( Membuf, ClearMbsSecondaryBits );
int32_t cleanupSecondaryFirBits( ExtensibleChip * i_chip, TYPE i_busType, uint32_t i_busPos ) { int32_t l_rc = SUCCESS; TargetHandle_t mcsTgt = NULL; TargetHandle_t mbTgt = NULL; ExtensibleChip * mcsChip = NULL; ExtensibleChip * mbChip = NULL; //In case of spare deployed attention for DMI bus, we need to clear // secondary MBIFIR[10] and MCIFIR[10] bits. do { if ( i_busType == TYPE_MCS ) { mcsTgt = getConnectedChild( i_chip->GetChipHandle(), TYPE_MCS, i_busPos); if (!mcsTgt) break; mcsChip = ( ExtensibleChip * )systemPtr->GetChip( mcsTgt ); if (!mcsChip) break; mbChip = getMcsDataBundle( mcsChip )->getMembChip(); if (!mbChip) break; mbTgt = mbChip->GetChipHandle(); if (!mbTgt) break; } else if ( i_busType == TYPE_MEMBUF ) { mbTgt = i_chip->GetChipHandle(); if (!mbTgt) break; mcsChip = getMembufDataBundle( i_chip )->getMcsChip(); if (!mcsChip) break; mcsTgt = mcsChip->GetChipHandle(); if (!mcsTgt) break; mbChip = i_chip; } else { // We only need to clean secondary FIR bits for DMI bus l_rc = SUCCESS; break; } SCAN_COMM_REGISTER_CLASS * mciAnd = mcsChip->getRegister("MCIFIR_AND"); SCAN_COMM_REGISTER_CLASS * mbiAnd = mbChip->getRegister( "MBIFIR_AND"); mciAnd->setAllBits(); mciAnd->ClearBit(10); mbiAnd->setAllBits(); mbiAnd->ClearBit(10); l_rc = mciAnd->Write(); l_rc |= mbiAnd->Write(); if ( SUCCESS != l_rc ) { PRDF_ERR( "[cleanupSecondaryFirBits] Write() failed on " "MCIFIR/MBIFIR: MCS=0x%08x MEMB=0x%08x", mcsChip->GetId(), mbChip->GetId() ); break; } } while (0); return l_rc; }