Exemplo n.º 1
0
/// Returns string representation of scheduler comment
std::string TargetSubtargetInfo::getSchedInfoStr(const MachineInstr &MI) const {
  if (MI.isPseudo() || MI.isTerminator())
    return std::string();
  // We don't cache TSchedModel because it depends on TargetInstrInfo
  // that could be changed during the compilation
  TargetSchedModel TSchedModel;
  TSchedModel.init(this);
  unsigned Latency = TSchedModel.computeInstrLatency(&MI);
  Optional<double> RThroughput = TSchedModel.computeReciprocalThroughput(&MI);
  return createSchedInfoStr(Latency, RThroughput);
}
Exemplo n.º 2
0
bool TargetInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
                                       const MachineInstr *DefMI,
                                       unsigned DefIdx) const {
  const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
  if (!ItinData || ItinData->isEmpty())
    return false;

  unsigned DefClass = DefMI->getDesc().getSchedClass();
  int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
  return (DefCycle != -1 && DefCycle <= 1);
}
Exemplo n.º 3
0
/// Returns string representation of scheduler comment
std::string TargetSubtargetInfo::getSchedInfoStr(MCInst const &MCI) const {
  // We don't cache TSchedModel because it depends on TargetInstrInfo
  // that could be changed during the compilation
  TargetSchedModel TSchedModel;
  TSchedModel.init(this);
  unsigned Latency;
  if (TSchedModel.hasInstrSchedModel())
    Latency = TSchedModel.computeInstrLatency(MCI);
  else if (TSchedModel.hasInstrItineraries()) {
    auto *ItinData = TSchedModel.getInstrItineraries();
    Latency = ItinData->getStageLatency(
        getInstrInfo()->get(MCI.getOpcode()).getSchedClass());
  } else
    return std::string();
  Optional<double> RThroughput =
      TSchedModel.computeReciprocalThroughput(MCI);
  return createSchedInfoStr(Latency, RThroughput);
}