void PCB_EDIT_FRAME::Swap_Layers( wxCommandEvent& event )
{
PCB_LAYER_ID new_layer[PCB_LAYER_ID_COUNT];
DIALOG_SWAP_LAYERS dlg( this, new_layer );
if( dlg.ShowModal() != wxID_OK )
return;
BOARD_COMMIT commit( this );
bool hasChanges = false;
// Change tracks.
for( TRACK* segm = GetBoard()->m_Track; segm; segm = segm->Next() )
{
if( segm->Type() == PCB_VIA_T )
{
VIA* via = (VIA*) segm;
PCB_LAYER_ID top_layer, bottom_layer;
if( via->GetViaType() == VIA_THROUGH )
continue;
via->LayerPair( &top_layer, &bottom_layer );
if( new_layer[bottom_layer] != bottom_layer || new_layer[top_layer] != top_layer )
{
commit.Modify( via );
via->SetLayerPair( new_layer[top_layer], new_layer[bottom_layer] );
GetGalCanvas()->GetView()->Update( via, KIGFX::GEOMETRY );
hasChanges = true;
}
}
else
{
hasChanges |= processBoardItem( this, commit, segm, new_layer );
}
}
for( BOARD_ITEM* zone : GetBoard()->Zones() )
{
hasChanges |= processBoardItem( this, commit, zone, new_layer );
}
for( BOARD_ITEM* drawing : GetBoard()->Drawings() )
{
hasChanges |= processBoardItem( this, commit, drawing, new_layer );
}
if( hasChanges )
{
OnModify();
commit.Push( "Layers moved" );
GetCanvas()->Refresh();
}
}
bool TRACKS_CLEANER::clean_vias()
{
bool modified = false;
for( VIA* via = GetFirstVia( m_Brd->m_Track ); via != NULL;
via = GetFirstVia( via->Next() ) )
{
// Correct via m_End defects (if any), should never happen
if( via->GetStart() != via->GetEnd() )
{
wxFAIL_MSG( wxT( "Via with mismatching ends" ) );
via->SetEnd( via->GetStart() );
}
/* Important: these cleanups only do thru hole vias, they don't
* (yet) handle high density interconnects */
if( via->GetViaType() != VIA_THROUGH )
{
modified |= remove_duplicates_of_via( via );
/* To delete through Via on THT pads at same location
* Examine the list of connected pads:
* if one through pad is found, the via can be removed */
for( unsigned ii = 0; ii < via->m_PadsConnected.size(); ++ii )
{
const D_PAD *pad = via->m_PadsConnected[ii];
const LSET all_cu = LSET::AllCuMask();
if( (pad->GetLayerSet() & all_cu) == all_cu )
{
// redundant: delete the via
m_Brd->GetRatsnest()->Remove( via );
via->ViewRelease();
via->DeleteStructure();
modified = true;
break;
}
}
}
}
return modified;
}
void EDA_3D_CANVAS::buildBoardThroughHolesPolygonList( SHAPE_POLY_SET& allBoardHoles,
int aSegCountPerCircle, bool aOptimizeLargeCircles )
{
// hole diameter value to change seg count by circle:
int small_hole_limit = Millimeter2iu( 1.0 );
int copper_thickness = GetPrm3DVisu().GetCopperThicknessBIU();
BOARD* pcb = GetBoard();
// Build holes of through vias:
for( TRACK* track = pcb->m_Track; track; track = track->Next() )
{
if( track->Type() != PCB_VIA_T )
continue;
VIA *via = static_cast<VIA*>( track );
if( via->GetViaType() != VIA_THROUGH )
continue;
int holediameter = via->GetDrillValue();
int hole_outer_radius = (holediameter + copper_thickness) / 2;
TransformCircleToPolygon( allBoardHoles,
via->GetStart(), hole_outer_radius,
aSegCountPerCircle );
}
// Build holes of through pads:
for( MODULE* footprint = pcb->m_Modules; footprint; footprint = footprint->Next() )
{
for( D_PAD* pad = footprint->Pads(); pad; pad = pad->Next() )
{
// Calculate a factor to apply to segcount for large holes ( > 1 mm)
// (bigger pad drill size -> more segments) because holes in pads can have
// very different sizes and optimizing this segcount gives a better look
// Mainly mounting holes have a size bigger than small_hole_limit
wxSize padHole = pad->GetDrillSize();
if( ! padHole.x ) // Not drilled pad like SMD pad
continue;
// we use the hole diameter to calculate the seg count.
// for round holes, padHole.x == padHole.y
// for oblong holes, the diameter is the smaller of (padHole.x, padHole.y)
int diam = std::min( padHole.x, padHole.y );
int segcount = aSegCountPerCircle;
if( diam > small_hole_limit )
{
double segFactor = (double)diam / small_hole_limit;
segcount = (int)(aSegCountPerCircle * segFactor);
// limit segcount to 48. For a circle this is a very good approx.
if( segcount > 48 )
segcount = 48;
}
// The hole in the body is inflated by copper thickness.
int inflate = copper_thickness;
// If not plated, no copper.
if( pad->GetAttribute () == PAD_HOLE_NOT_PLATED )
inflate = 0;
pad->BuildPadDrillShapePolygon( allBoardHoles, inflate, segcount );
}
}
allBoardHoles.Simplify();
}
void EDA_3D_CANVAS::buildBoard3DView( GLuint aBoardList, GLuint aBodyOnlyList,
REPORTER* aErrorMessages, REPORTER* aActivity )
{
BOARD* pcb = GetBoard();
// If FL_RENDER_SHOW_HOLES_IN_ZONES is true, holes are correctly removed from copper zones areas.
// If FL_RENDER_SHOW_HOLES_IN_ZONES is false, holes are not removed from copper zones areas,
// but the calculation time is twice shorter.
bool remove_Holes = isEnabled( FL_RENDER_SHOW_HOLES_IN_ZONES );
bool realistic_mode = isRealisticMode();
bool useTextures = isRealisticMode() && isEnabled( FL_RENDER_TEXTURES );
// Number of segments to convert a circle to polygon
// We use 2 values: the first gives a good shape (for instanes rond pads)
// the second is used to speed up calculations, when a poor approximation is acceptable (holes)
const int segcountforcircle = 18;
double correctionFactor = 1.0 / cos( M_PI / (segcountforcircle * 2.0) );
const int segcountLowQuality = 12; // segments to draw a circle with low quality
// to reduce time calculations
// for holes and items which do not need
// a fine representation
double correctionFactorLQ = 1.0 / cos( M_PI / (segcountLowQuality * 2.0) );
SHAPE_POLY_SET bufferPolys; // copper areas: tracks, pads and filled zones areas
// when holes are removed from zones
SHAPE_POLY_SET bufferPcbOutlines; // stores the board main outlines
SHAPE_POLY_SET bufferZonesPolys; // copper filled zones areas
// when holes are not removed from zones
SHAPE_POLY_SET currLayerHoles; // Contains holes for the current layer
SHAPE_POLY_SET allLayerHoles; // Contains holes for all layers
// Build a polygon from edge cut items
wxString msg;
if( !pcb->GetBoardPolygonOutlines( bufferPcbOutlines, allLayerHoles, &msg ) )
{
if( aErrorMessages )
{
msg << wxT("\n") << _("Unable to calculate the board outlines.\n"
"Therefore use the board boundary box.") << wxT("\n\n");
aErrorMessages->Report( msg, REPORTER::RPT_WARNING );
}
}
// Build board holes, with optimization of large holes shape.
buildBoardThroughHolesPolygonList( allLayerHoles, segcountLowQuality, true );
LSET cu_set = LSET::AllCuMask( GetPrm3DVisu().m_CopperLayersCount );
glNewList( aBoardList, GL_COMPILE );
for( LSEQ cu = cu_set.CuStack(); cu; ++cu )
{
LAYER_ID layer = *cu;
// Skip non enabled layers in normal mode,
// and internal layers in realistic mode
if( !is3DLayerEnabled( layer ) )
continue;
if( aActivity )
aActivity->Report( wxString::Format( _( "Build layer %s" ), LSET::Name( layer ) ) );
bufferPolys.RemoveAllContours();
bufferZonesPolys.RemoveAllContours();
currLayerHoles.RemoveAllContours();
// Draw track shapes:
for( TRACK* track = pcb->m_Track; track; track = track->Next() )
{
if( !track->IsOnLayer( layer ) )
continue;
track->TransformShapeWithClearanceToPolygon( bufferPolys,
0, segcountforcircle,
correctionFactor );
// Add blind/buried via holes
if( track->Type() == PCB_VIA_T )
{
VIA *via = static_cast<VIA*>( track );
if( via->GetViaType() == VIA_THROUGH )
continue; // already done
int holediameter = via->GetDrillValue();
int thickness = GetPrm3DVisu().GetCopperThicknessBIU();
int hole_outer_radius = (holediameter + thickness) / 2;
TransformCircleToPolygon( currLayerHoles,
via->GetStart(), hole_outer_radius,
segcountLowQuality );
}
}
// draw pad shapes
for( MODULE* module = pcb->m_Modules; module; module = module->Next() )
{
// Note: NPTH pads are not drawn on copper layers when the pad
// has same shape as its hole
module->TransformPadsShapesWithClearanceToPolygon( layer,
bufferPolys,
0,
segcountforcircle,
correctionFactor, true );
// Micro-wave modules may have items on copper layers
module->TransformGraphicShapesWithClearanceToPolygonSet( layer,
bufferPolys,
0,
segcountforcircle,
correctionFactor );
// pad holes are already in list.
}
// Draw copper zones. Note:
// * if the holes are removed from copper zones
// the polygons are stored in bufferPolys (which contains all other polygons)
// * if the holes are NOT removed from copper zones
// the polygons are stored in bufferZonesPolys
if( isEnabled( FL_ZONE ) )
{
for( int ii = 0; ii < pcb->GetAreaCount(); ii++ )
{
ZONE_CONTAINER* zone = pcb->GetArea( ii );
LAYER_NUM zonelayer = zone->GetLayer();
if( zonelayer == layer )
{
zone->TransformSolidAreasShapesToPolygonSet(
remove_Holes ? bufferPolys : bufferZonesPolys,
segcountLowQuality, correctionFactorLQ );
}
}
}
// draw graphic items on copper layers (texts)
for( BOARD_ITEM* item = pcb->m_Drawings; item; item = item->Next() )
{
if( !item->IsOnLayer( layer ) )
continue;
switch( item->Type() )
{
case PCB_LINE_T: // should not exist on copper layers
( (DRAWSEGMENT*) item )->TransformShapeWithClearanceToPolygon(
bufferPolys, 0, segcountforcircle, correctionFactor );
break;
case PCB_TEXT_T:
( (TEXTE_PCB*) item )->TransformShapeWithClearanceToPolygonSet(
bufferPolys, 0, segcountLowQuality, correctionFactor );
break;
default:
break;
}
}
// bufferPolys contains polygons to merge. Many overlaps .
// Calculate merged polygons
if( bufferPolys.IsEmpty() )
continue;
// Use Clipper lib to subtract holes to copper areas
if( currLayerHoles.OutlineCount() )
{
currLayerHoles.Append(allLayerHoles);
currLayerHoles.Simplify();
bufferPolys.BooleanSubtract( currLayerHoles );
}
else
bufferPolys.BooleanSubtract( allLayerHoles );
int thickness = GetPrm3DVisu().GetLayerObjectThicknessBIU( layer );
int zpos = GetPrm3DVisu().GetLayerZcoordBIU( layer );
float zNormal = 1.0f; // When using thickness it will draw first the top and then botton (with z inverted)
// If we are not using thickness, then the z-normal has to match the layer direction
// because just one plane will be drawn
if( !thickness )
zNormal = Get3DLayer_Z_Orientation( layer );
if( realistic_mode )
{
setGLCopperColor();
}
else
{
EDA_COLOR_T color = g_ColorsSettings.GetLayerColor( layer );
SetGLColor( color );
}
// If holes are removed from copper zones, bufferPolys contains all polygons
// to draw (tracks+zones+texts).
Draw3D_SolidHorizontalPolyPolygons( bufferPolys, zpos, thickness,
GetPrm3DVisu().m_BiuTo3Dunits, useTextures,
zNormal );
// If holes are not removed from copper zones (for calculation time reasons,
// the zone polygons are stored in bufferZonesPolys and have to be drawn now:
if( !bufferZonesPolys.IsEmpty() )
{
Draw3D_SolidHorizontalPolyPolygons( bufferZonesPolys, zpos, thickness,
GetPrm3DVisu().m_BiuTo3Dunits, useTextures,
zNormal );
}
}
if( aActivity )
aActivity->Report( _( "Build board body" ) );
// Draw plated vertical holes inside the board, but not always. They are drawn:
// - if the board body is not shown, to show the holes.
// - or if the copper thickness is shown
if( !isEnabled( FL_SHOW_BOARD_BODY ) || isEnabled( FL_USE_COPPER_THICKNESS ) )
{
// Draw vias holes (vertical cylinders)
for( const TRACK* track = pcb->m_Track; track; track = track->Next() )
{
if( track->Type() == PCB_VIA_T )
{
const VIA *via = static_cast<const VIA*>(track);
draw3DViaHole( via );
}
}
// Draw pads holes (vertical cylinders)
for( const MODULE* module = pcb->m_Modules; module; module = module->Next() )
{
for( D_PAD* pad = module->Pads(); pad; pad = pad->Next() )
if( pad->GetAttribute () != PAD_HOLE_NOT_PLATED )
draw3DPadHole( pad );
}
}
glEndList();
// Build the body board:
glNewList( aBodyOnlyList, GL_COMPILE );
if( isRealisticMode() )
{
setGLEpoxyColor( 1.00 );
}
else
{
EDA_COLOR_T color = g_ColorsSettings.GetLayerColor( Edge_Cuts );
SetGLColor( color, 0.7 );
}
float copper_thickness = GetPrm3DVisu().GetCopperThicknessBIU();
// a small offset between substrate and external copper layer to avoid artifacts
// when drawing copper items on board
float epsilon = Millimeter2iu( 0.01 );
float zpos = GetPrm3DVisu().GetLayerZcoordBIU( B_Cu );
float board_thickness = GetPrm3DVisu().GetLayerZcoordBIU( F_Cu )
- GetPrm3DVisu().GetLayerZcoordBIU( B_Cu );
// items on copper layers and having a thickness = copper_thickness
// are drawn from zpos - copper_thickness/2 to zpos + copper_thickness
// therefore substrate position is copper_thickness/2 to
// substrate_height - copper_thickness/2
zpos += (copper_thickness + epsilon) / 2.0f;
board_thickness -= copper_thickness + epsilon;
bufferPcbOutlines.BooleanSubtract( allLayerHoles );
if( !bufferPcbOutlines.IsEmpty() )
{
Draw3D_SolidHorizontalPolyPolygons( bufferPcbOutlines, zpos + board_thickness / 2.0,
board_thickness, GetPrm3DVisu().m_BiuTo3Dunits, useTextures,
1.0f );
}
glEndList();
}
bool PCB_EDIT_FRAME::Other_Layer_Route( TRACK* aTrack, wxDC* DC )
{
unsigned itmp;
if( aTrack == NULL )
{
if( GetActiveLayer() != GetScreen()->m_Route_Layer_TOP )
SetActiveLayer( GetScreen()->m_Route_Layer_TOP );
else
SetActiveLayer( GetScreen()->m_Route_Layer_BOTTOM );
UpdateStatusBar();
return true;
}
// Avoid more than one via on the current location:
if( GetBoard()->GetViaByPosition( g_CurrentTrackSegment->GetEnd(),
g_CurrentTrackSegment->GetLayer() ) )
return false;
for( TRACK* segm = g_FirstTrackSegment; segm; segm = segm->Next() )
{
if( segm->Type() == PCB_VIA_T && g_CurrentTrackSegment->GetEnd() == segm->GetStart() )
return false;
}
// Is the current segment Ok (no DRC error) ?
if( g_Drc_On )
{
if( BAD_DRC==m_drc->Drc( g_CurrentTrackSegment, GetBoard()->m_Track ) )
// DRC error, the change layer is not made
return false;
// Handle 2 segments.
if( g_TwoSegmentTrackBuild && g_CurrentTrackSegment->Back() )
{
if( BAD_DRC == m_drc->Drc( g_CurrentTrackSegment->Back(), GetBoard()->m_Track ) )
return false;
}
}
/* Save current state before placing a via.
* If the via cannot be placed this current state will be reused
*/
itmp = g_CurrentTrackList.GetCount();
Begin_Route( g_CurrentTrackSegment, DC );
m_canvas->CallMouseCapture( DC, wxDefaultPosition, false );
// create the via
VIA* via = new VIA( GetBoard() );
via->SetFlags( IS_NEW );
via->SetViaType( GetDesignSettings().m_CurrentViaType );
via->SetNetCode( GetBoard()->GetHighLightNetCode() );
via->SetPosition( g_CurrentTrackSegment->GetEnd() );
// for microvias, the size and hole will be changed later.
via->SetWidth( GetDesignSettings().GetCurrentViaSize());
via->SetDrill( GetDesignSettings().GetCurrentViaDrill() );
// Usual via is from copper to component.
// layer pair is B_Cu and F_Cu.
via->SetLayerPair( B_Cu, F_Cu );
LAYER_ID first_layer = GetActiveLayer();
LAYER_ID last_layer;
// prepare switch to new active layer:
if( first_layer != GetScreen()->m_Route_Layer_TOP )
last_layer = GetScreen()->m_Route_Layer_TOP;
else
last_layer = GetScreen()->m_Route_Layer_BOTTOM;
// Adjust the actual via layer pair
switch( via->GetViaType() )
{
case VIA_BLIND_BURIED:
via->SetLayerPair( first_layer, last_layer );
break;
case VIA_MICROVIA: // from external to the near neighbor inner layer
{
LAYER_ID last_inner_layer = ToLAYER_ID( ( GetBoard()->GetCopperLayerCount() - 2 ) );
if( first_layer == B_Cu )
last_layer = last_inner_layer;
else if( first_layer == F_Cu )
last_layer = In1_Cu;
else if( first_layer == last_inner_layer )
last_layer = B_Cu;
else if( first_layer == In1_Cu )
last_layer = F_Cu;
// else error: will be removed later
via->SetLayerPair( first_layer, last_layer );
// Update diameter and hole size, which where set previously
// for normal vias
NETINFO_ITEM* net = via->GetNet();
via->SetWidth( net->GetMicroViaSize() );
via->SetDrill( net->GetMicroViaDrillSize() );
}
break;
default:
break;
}
if( g_Drc_On && BAD_DRC == m_drc->Drc( via, GetBoard()->m_Track ) )
{
// DRC fault: the Via cannot be placed here ...
delete via;
m_canvas->CallMouseCapture( DC, wxDefaultPosition, false );
// delete the track(s) added in Begin_Route()
while( g_CurrentTrackList.GetCount() > itmp )
{
Delete_Segment( DC, g_CurrentTrackSegment );
}
SetCurItem( g_CurrentTrackSegment, false );
// Refresh DRC diag, erased by previous calls
if( m_drc->GetCurrentMarker() )
SetMsgPanel( m_drc->GetCurrentMarker() );
return false;
}
SetActiveLayer( last_layer );
TRACK* lastNonVia = g_CurrentTrackSegment;
/* A new via was created. It was Ok.
*/
g_CurrentTrackList.PushBack( via );
/* The via is now in linked list and we need a new track segment
* after the via, starting at via location.
* it will become the new current segment (from via to the mouse cursor)
*/
TRACK* track = (TRACK*)lastNonVia->Clone();
/* the above creates a new segment from the last entered segment, with the
* current width, flags, netcode, etc... values.
* layer, start and end point are not correct,
* and will be modified next
*/
// set the layer to the new value
track->SetLayer( GetActiveLayer() );
/* the start point is the via position and the end point is the cursor
* which also is on the via (will change when moving mouse)
*/
track->SetEnd( via->GetStart() );
track->SetStart( via->GetStart() );
g_CurrentTrackList.PushBack( track );
if( g_TwoSegmentTrackBuild )
{
// Create a second segment (we must have 2 track segments to adjust)
g_CurrentTrackList.PushBack( (TRACK*)g_CurrentTrackSegment->Clone() );
}
m_canvas->CallMouseCapture( DC, wxDefaultPosition, false );
SetMsgPanel( via );
UpdateStatusBar();
return true;
}
bool DIALOG_TRACK_VIA_PROPERTIES::Apply( COMMIT& aCommit )
{
if( !check() )
return false;
bool changeLock = m_lockedCbox->Get3StateValue() != wxCHK_UNDETERMINED;
bool setLock = m_lockedCbox->Get3StateValue() == wxCHK_CHECKED;
for( auto item : m_items )
{
aCommit.Modify( item );
switch( item->Type() )
{
case PCB_TRACE_T:
{
assert( m_tracks );
TRACK* t = static_cast<TRACK*>( item );
if( m_trackStartX.Valid() || m_trackStartY.Valid() )
{
wxPoint start = t->GetStart();
if( m_trackStartX.Valid() )
start.x = m_trackStartX.GetValue();
if( m_trackStartY.Valid() )
start.y = m_trackStartY.GetValue();
t->SetStart( start );
}
if( m_trackEndX.Valid() || m_trackEndY.Valid() )
{
wxPoint end = t->GetEnd();
if( m_trackEndX.Valid() )
end.x = m_trackEndX.GetValue();
if( m_trackEndY.Valid() )
end.y = m_trackEndY.GetValue();
t->SetEnd( end );
}
if( m_trackNetclass->IsChecked() )
{
t->SetWidth( t->GetNetClass()->GetTrackWidth() );
}
else if( m_trackWidth.Valid() )
{
t->SetWidth( m_trackWidth.GetValue() );
}
LAYER_NUM layer = m_TrackLayerCtrl->GetLayerSelection();
if( layer != UNDEFINED_LAYER )
t->SetLayer( (LAYER_ID) layer );
if( changeLock )
t->SetLocked( setLock );
break;
}
case PCB_VIA_T:
{
assert( m_vias );
VIA* v = static_cast<VIA*>( item );
if( m_viaX.Valid() || m_viaY.Valid() )
{
wxPoint pos = v->GetPosition();
if( m_viaX.Valid() )
pos.x = m_viaX.GetValue();
if( m_viaY.Valid() )
pos.y = m_viaY.GetValue();
v->SetPosition( pos );
}
if( m_viaNetclass->IsChecked() )
{
switch( v->GetViaType() )
{
default:
wxFAIL_MSG("Unhandled via type");
// fall through
case VIA_THROUGH:
case VIA_BLIND_BURIED:
v->SetWidth( v->GetNetClass()->GetViaDiameter() );
v->SetDrill( v->GetNetClass()->GetViaDrill() );
break;
case VIA_MICROVIA:
v->SetWidth( v->GetNetClass()->GetuViaDiameter() );
v->SetDrill( v->GetNetClass()->GetuViaDrill() );
break;
}
}
else
{
if( m_viaDiameter.Valid() )
v->SetWidth( m_viaDiameter.GetValue() );
if( m_viaDrill.Valid() )
v->SetDrill( m_viaDrill.GetValue() );
}
if( changeLock )
v->SetLocked( setLock );
break;
}
default:
assert( false );
break;
}
}
return true;
}
void BOARD_ITEM::SwapData( BOARD_ITEM* aImage )
{
if( aImage == NULL )
{
return;
}
EDA_ITEM * pnext = Next();
EDA_ITEM * pback = Back();
switch( Type() )
{
case PCB_MODULE_T:
{
MODULE* tmp = (MODULE*) aImage->Clone();
( (MODULE*) aImage )->Copy( (MODULE*) this );
( (MODULE*) this )->Copy( tmp );
delete tmp;
}
break;
case PCB_ZONE_AREA_T:
{
ZONE_CONTAINER* tmp = (ZONE_CONTAINER*) aImage->Clone();
( (ZONE_CONTAINER*) aImage )->Copy( (ZONE_CONTAINER*) this );
( (ZONE_CONTAINER*) this )->Copy( tmp );
delete tmp;
}
break;
case PCB_LINE_T:
std::swap( *((DRAWSEGMENT*)this), *((DRAWSEGMENT*)aImage) );
break;
case PCB_TRACE_T:
case PCB_VIA_T:
{
TRACK* track = (TRACK*) this;
TRACK* image = (TRACK*) aImage;
EXCHG(track->m_Layer, image->m_Layer );
// swap start, end, width and shape for track and image.
wxPoint exchp = track->GetStart();
track->SetStart( image->GetStart() );
image->SetStart( exchp );
exchp = track->GetEnd();
track->SetEnd( image->GetEnd() );
image->SetEnd( exchp );
int atmp = track->GetWidth();
track->SetWidth( image->GetWidth() );
image->SetWidth( atmp );
if( Type() == PCB_VIA_T )
{
VIA *via = static_cast<VIA*>( this );
VIA *viaimage = static_cast<VIA*>( aImage );
VIATYPE_T viatmp = via->GetViaType();
via->SetViaType( viaimage->GetViaType() );
viaimage->SetViaType( viatmp );
int drilltmp = via->GetDrillValue();
if( via->IsDrillDefault() )
drilltmp = -1;
int itmp = viaimage->GetDrillValue();
if( viaimage->IsDrillDefault() )
itmp = -1;
EXCHG(itmp, drilltmp );
if( drilltmp > 0 )
via->SetDrill( drilltmp );
else
via->SetDrillDefault();
if( itmp > 0 )
viaimage->SetDrill( itmp );
else
viaimage->SetDrillDefault();
}
}
break;
case PCB_TEXT_T:
std::swap( *((TEXTE_PCB*)this), *((TEXTE_PCB*)aImage) );
break;
case PCB_TARGET_T:
std::swap( *((PCB_TARGET*)this), *((PCB_TARGET*)aImage) );
break;
case PCB_DIMENSION_T:
std::swap( *((DIMENSION*)this), *((DIMENSION*)aImage) );
break;
case PCB_ZONE_T:
default:
wxLogMessage( wxT( "SwapData() error: unexpected type %d" ), Type() );
break;
}
if( pnext != Next() || pback != Back() )
{
Pnext = pnext;
Pback = pback;
#ifdef DEBUG
wxLogMessage( wxT( "SwapData Error: %s Pnext or Pback pointers modified" ),
GetClass().GetData() );
#endif
}
}
void BOARD_ITEM::SwapData( BOARD_ITEM* aImage )
{
if( aImage == NULL )
return;
// Remark: to create images of edited items to undo, we are using Clone method
// which can duplication of items foe copy, but does not clone all members
// mainly pointers in chain and time stamp, which is set to new, unique value.
// So we have to use the current values of these parameters.
EDA_ITEM * pnext = Next();
EDA_ITEM * pback = Back();
DHEAD* mylist = m_List;
time_t timestamp = GetTimeStamp();
switch( Type() )
{
case PCB_MODULE_T:
{
MODULE* tmp = (MODULE*) aImage->Clone();
( (MODULE*) aImage )->Copy( (MODULE*) this );
( (MODULE*) this )->Copy( tmp );
delete tmp;
}
break;
case PCB_ZONE_AREA_T:
{
ZONE_CONTAINER* tmp = (ZONE_CONTAINER*) aImage->Clone();
( (ZONE_CONTAINER*) aImage )->Copy( (ZONE_CONTAINER*) this );
( (ZONE_CONTAINER*) this )->Copy( tmp );
delete tmp;
}
break;
case PCB_LINE_T:
std::swap( *((DRAWSEGMENT*)this), *((DRAWSEGMENT*)aImage) );
break;
case PCB_TRACE_T:
case PCB_VIA_T:
{
TRACK* track = (TRACK*) this;
TRACK* image = (TRACK*) aImage;
std::swap(track->m_Layer, image->m_Layer );
// swap start, end, width and shape for track and image.
wxPoint exchp = track->GetStart();
track->SetStart( image->GetStart() );
image->SetStart( exchp );
exchp = track->GetEnd();
track->SetEnd( image->GetEnd() );
image->SetEnd( exchp );
int atmp = track->GetWidth();
track->SetWidth( image->GetWidth() );
image->SetWidth( atmp );
if( Type() == PCB_VIA_T )
{
VIA *via = static_cast<VIA*>( this );
VIA *viaimage = static_cast<VIA*>( aImage );
VIATYPE_T viatmp = via->GetViaType();
via->SetViaType( viaimage->GetViaType() );
viaimage->SetViaType( viatmp );
int drilltmp = via->GetDrillValue();
if( via->IsDrillDefault() )
drilltmp = -1;
int itmp = viaimage->GetDrillValue();
if( viaimage->IsDrillDefault() )
itmp = -1;
std::swap(itmp, drilltmp );
if( drilltmp > 0 )
via->SetDrill( drilltmp );
else
via->SetDrillDefault();
if( itmp > 0 )
viaimage->SetDrill( itmp );
else
viaimage->SetDrillDefault();
}
}
break;
case PCB_TEXT_T:
std::swap( *((TEXTE_PCB*)this), *((TEXTE_PCB*)aImage) );
break;
case PCB_TARGET_T:
std::swap( *((PCB_TARGET*)this), *((PCB_TARGET*)aImage) );
break;
case PCB_DIMENSION_T:
std::swap( *((DIMENSION*)this), *((DIMENSION*)aImage) );
break;
case PCB_ZONE_T:
default:
wxLogMessage( wxT( "SwapData() error: unexpected type %d" ), Type() );
break;
}
// Restore pointers and time stamp, to be sure they are not broken
Pnext = pnext;
Pback = pback;
m_List = mylist;
SetTimeStamp( timestamp );
}
bool DIALOG_TRACK_VIA_PROPERTIES::TransferDataFromWindow()
{
auto connectivity = m_frame->GetBoard()->GetConnectivity();
int newNetCode = m_netSelector->GetSelectedNetcode();
std::vector<D_PAD*> changingPads;
if ( !m_netSelector->IsIndeterminate() )
{
std::set<D_PAD*> connectedPads;
for( auto& item : m_items )
{
const KICAD_T ourTypes[] = { PCB_TRACE_T, PCB_PAD_T, PCB_VIA_T, PCB_MODULE_T, EOT };
auto connectedItems = connectivity->GetConnectedItems( static_cast<BOARD_CONNECTED_ITEM*>( item ), ourTypes, true );
for ( auto citem : connectedItems )
{
if( citem->Type() == PCB_PAD_T )
{
connectedPads.insert( static_cast<D_PAD*>( citem ) );
}
}
}
for( D_PAD* pad : connectedPads )
{
if( pad->GetNetCode() != newNetCode )
changingPads.push_back( pad );
}
}
// Run validations:
if( changingPads.size() )
{
if( !confirmPadChange( changingPads ) )
return false;
}
if( m_vias )
{
if( !m_viaDiameter.Validate( GEOMETRY_MIN_SIZE, INT_MAX )
|| !m_viaDrill.Validate( GEOMETRY_MIN_SIZE, INT_MAX ) )
return false;
if( m_ViaDiameterCtrl->IsEnabled() && !m_viaDiameter.IsIndeterminate()
&& m_ViaDrillCtrl->IsEnabled() && !m_viaDrill.IsIndeterminate()
&& m_viaDiameter.GetValue() <= m_viaDrill.GetValue() )
{
DisplayError( GetParent(), _( "Via drill size must be smaller than via diameter" ) );
m_ViaDrillCtrl->SelectAll();
m_ViaDrillCtrl->SetFocus();
return false;
}
if( m_ViaStartLayer->GetLayerSelection() != UNDEFINED_LAYER &&
m_ViaStartLayer->GetLayerSelection() == m_ViaEndLayer->GetLayerSelection() )
{
DisplayError( GetParent(), _( "Via start layer and end layer cannot be the same" ) );
return false;
}
}
if( m_tracks )
{
if( !m_trackWidth.Validate( GEOMETRY_MIN_SIZE, INT_MAX ) )
return false;
}
// If we survived that, then save the changes:
bool changeLock = m_lockedCbox->Get3StateValue() != wxCHK_UNDETERMINED;
bool setLock = m_lockedCbox->Get3StateValue() == wxCHK_CHECKED;
for( auto item : m_items )
{
m_commit.Modify( item );
switch( item->Type() )
{
case PCB_TRACE_T:
{
wxASSERT( m_tracks );
TRACK* t = static_cast<TRACK*>( item );
if( !m_trackStartX.IsIndeterminate() )
t->SetStart( wxPoint( m_trackStartX.GetValue(), t->GetStart().y ) );
if( !m_trackStartY.IsIndeterminate() )
t->SetStart( wxPoint( t->GetStart().x, m_trackStartY.GetValue() ) );
if( !m_trackEndX.IsIndeterminate() )
t->SetEnd( wxPoint( m_trackEndX.GetValue(), t->GetEnd().y ) );
if( !m_trackEndY.IsIndeterminate() )
t->SetEnd( wxPoint( t->GetEnd().x, m_trackEndY.GetValue() ) );
if( m_trackNetclass->IsChecked() )
t->SetWidth( t->GetNetClass()->GetTrackWidth() );
else if( !m_trackWidth.IsIndeterminate() )
t->SetWidth( m_trackWidth.GetValue() );
LAYER_NUM layer = m_TrackLayerCtrl->GetLayerSelection();
if( layer != UNDEFINED_LAYER )
t->SetLayer( (PCB_LAYER_ID) layer );
if( changeLock )
t->SetLocked( setLock );
if ( !m_netSelector->IsIndeterminate() )
t->SetNetCode( m_netSelector->GetSelectedNetcode() );
break;
}
case PCB_VIA_T:
{
wxASSERT( m_vias );
VIA* v = static_cast<VIA*>( item );
if( !m_viaX.IsIndeterminate() )
v->SetPosition( wxPoint( m_viaX.GetValue(), v->GetPosition().y ) );
if( !m_viaY.IsIndeterminate() )
v->SetPosition( wxPoint( v->GetPosition().x, m_viaY.GetValue() ) );
if( m_ViaTypeChoice->GetSelection() != 3)
{
switch( m_ViaTypeChoice->GetSelection() )
{
default:
case 0: v->SetViaType( VIA_THROUGH ); v->SanitizeLayers(); break;
case 1: v->SetViaType( VIA_MICROVIA ); break;
case 2: v->SetViaType( VIA_BLIND_BURIED ); break;
}
}
auto startLayer = static_cast<PCB_LAYER_ID>( m_ViaStartLayer->GetLayerSelection() );
auto endLayer = static_cast<PCB_LAYER_ID>( m_ViaEndLayer->GetLayerSelection() );
if (startLayer != UNDEFINED_LAYER )
v->SetTopLayer( startLayer );
if (endLayer != UNDEFINED_LAYER )
v->SetBottomLayer( endLayer );
v->SanitizeLayers();
if( m_viaNetclass->IsChecked() )
{
switch( v->GetViaType() )
{
default:
wxFAIL_MSG("Unhandled via type");
// fall through
case VIA_THROUGH:
case VIA_BLIND_BURIED:
v->SetWidth( v->GetNetClass()->GetViaDiameter() );
v->SetDrill( v->GetNetClass()->GetViaDrill() );
break;
case VIA_MICROVIA:
v->SetWidth( v->GetNetClass()->GetuViaDiameter() );
v->SetDrill( v->GetNetClass()->GetuViaDrill() );
break;
}
}
else
{
if( !m_viaDiameter.IsIndeterminate() )
v->SetWidth( m_viaDiameter.GetValue() );
if( !m_viaDrill.IsIndeterminate() )
v->SetDrill( m_viaDrill.GetValue() );
}
if ( !m_netSelector->IsIndeterminate() )
v->SetNetCode( m_netSelector->GetSelectedNetcode() );
if( changeLock )
v->SetLocked( setLock );
break;
}
default:
wxASSERT( false );
break;
}
}
if ( !m_netSelector->IsIndeterminate() )
{
// Commit::Push() will rebuild connectivitiy propagating nets from connected pads
// outwards. We therefore have to update the connected pads in order for the net
// change to "stick".
for( D_PAD* pad : changingPads )
{
m_commit.Modify( pad );
pad->SetNetCode( m_netSelector->GetSelectedNetcode() );
}
}
m_commit.Push( _( "Edit track/via properties" ) );
return true;
}