/**
* Trace PCBS FSMs across primary and secondary chips
*
* @param[in] i_target Chip target
* @param[in] i_msg String to put out in the trace
*
* @retval ECMD_SUCCESS
* @retval ERROR defined in xml
*/
fapi::ReturnCode
p4rs_pcbs_fsm_trace(const fapi::Target& i_primary_target,
const fapi::Target& i_secondary_target,
const char * i_msg)
{
fapi::ReturnCode rc;
do
{
rc = p8_pm_pcbs_fsm_trace_chip (i_primary_target, i_msg);
if (rc)
{
FAPI_ERR("pcbs_fsm_trace_chip failed for Target %s",
i_primary_target.toEcmdString());
break;
}
if ( i_secondary_target.getType() != TARGET_TYPE_NONE )
{
rc = p8_pm_pcbs_fsm_trace_chip (i_secondary_target, i_msg);
if (rc)
{
FAPI_ERR("pcbs_fsm_trace_chip failed for Target %s",
i_secondary_target.toEcmdString());
break;
}
}
} while(0);
return rc;
}
// HWP entry point, comments in header
fapi::ReturnCode proc_chiplet_scominit(const fapi::Target & i_target)
{
fapi::ReturnCode rc;
uint32_t rc_ecmd = 0;
fapi::TargetType target_type;
std::vector<fapi::Target> initfile_targets;
std::vector<fapi::Target> ex_targets;
std::vector<fapi::Target> mcs_targets;
uint8_t nx_enabled;
uint8_t mcs_pos;
uint8_t ex_pos;
uint8_t num_ex_targets;
uint8_t master_mcs_pos = 0xFF;
fapi::Target master_mcs;
uint8_t enable_xbus_resonant_clocking = 0x0;
uint8_t i2c_slave_address = 0x0;
uint8_t dual_capp_present = 0x0;
ecmdDataBufferBase data(64);
ecmdDataBufferBase cfam_data(32);
ecmdDataBufferBase mask(64);
bool is_master = false;
// mark HWP entry
FAPI_INF("proc_chiplet_scominit: Start");
do
{
rc = proc_check_master_sbe_seeprom(i_target, is_master);
if (!rc.ok())
{
FAPI_ERR("proc_cen_ref_clk_enable: Error from proc_check_master_sbe_seeprom");
break;
}
// obtain target type to determine which initfile(s) to execute
target_type = i_target.getType();
// chip level target
if (target_type == fapi::TARGET_TYPE_PROC_CHIP)
{
// execute FBC SCOM initfile
initfile_targets.push_back(i_target);
FAPI_INF("proc_chiplet_scominit: Executing %s on %s",
PROC_CHIPLET_SCOMINIT_FBC_IF, i_target.toEcmdString());
FAPI_EXEC_HWP(
rc,
fapiHwpExecInitFile,
initfile_targets,
PROC_CHIPLET_SCOMINIT_FBC_IF);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: Error from fapiHwpExecInitfile executing %s on %s",
PROC_CHIPLET_SCOMINIT_FBC_IF,
i_target.toEcmdString());
break;
}
// execute PSI SCOM initfile
FAPI_INF("proc_chiplet_scominit: Executing %s on %s",
PROC_CHIPLET_SCOMINIT_PSI_IF, i_target.toEcmdString());
FAPI_EXEC_HWP(
rc,
fapiHwpExecInitFile,
initfile_targets,
PROC_CHIPLET_SCOMINIT_PSI_IF);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: Error from fapiHwpExecInitfile executing %s on %s",
PROC_CHIPLET_SCOMINIT_PSI_IF,
i_target.toEcmdString());
break;
}
// execute TP bridge SCOM initfile
FAPI_INF("proc_chiplet_scominit: Executing %s on %s",
PROC_CHIPLET_SCOMINIT_TPBRIDGE_IF, i_target.toEcmdString());
FAPI_EXEC_HWP(
rc,
fapiHwpExecInitFile,
initfile_targets,
PROC_CHIPLET_SCOMINIT_TPBRIDGE_IF);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: Error from fapiHwpExecInitfile executing %s on %s",
PROC_CHIPLET_SCOMINIT_TPBRIDGE_IF,
i_target.toEcmdString());
break;
}
// query NX partial good attribute
rc = FAPI_ATTR_GET(ATTR_PROC_NX_ENABLE,
&i_target,
nx_enabled);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: Error querying ATTR_PROC_NX_ENABLE");
break;
}
// apply NX/AS SCOM initfiles only if partial good attribute is set
if (nx_enabled == fapi::ENUM_ATTR_PROC_NX_ENABLE_ENABLE)
{
// execute NX SCOM initfile
FAPI_INF("proc_chiplet_scominit: Executing %s on %s",
PROC_CHIPLET_SCOMINIT_NX_IF, i_target.toEcmdString());
FAPI_EXEC_HWP(
rc,
fapiHwpExecInitFile,
initfile_targets,
PROC_CHIPLET_SCOMINIT_NX_IF);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: Error from fapiHwpExecInitfile executing %s on %s",
PROC_CHIPLET_SCOMINIT_NX_IF,
i_target.toEcmdString());
break;
}
// execute CXA SCOM initfile
FAPI_INF("proc_chiplet_scominit: Executing %s on %s",
PROC_CHIPLET_SCOMINIT_CXA_IF, i_target.toEcmdString());
FAPI_EXEC_HWP(
rc,
fapiHwpExecInitFile,
initfile_targets,
PROC_CHIPLET_SCOMINIT_CXA_IF);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: Error from fapiHwpExecInitfile executing %s on %s",
PROC_CHIPLET_SCOMINIT_CXA_IF,
i_target.toEcmdString());
break;
}
// configure CXA APC master LCO settings
rc = fapiGetChildChiplets(i_target,
fapi::TARGET_TYPE_EX_CHIPLET,
ex_targets,
fapi::TARGET_STATE_FUNCTIONAL);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: Error from fapiGetChildChiplets (EX) on %s",
i_target.toEcmdString());
break;
}
// form valid LCO target list
for (std::vector<fapi::Target>::iterator i = ex_targets.begin();
i != ex_targets.end();
i++)
{
// determine EX chiplet number
rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &(*i), ex_pos);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS) on %s",
i->toEcmdString());
break;
}
rc_ecmd |= data.setBit(ex_pos-((ex_pos < 8)?(1):(3)));
}
if (!rc.ok())
{
break;
}
num_ex_targets = ex_targets.size();
rc_ecmd |= data.insertFromRight(
num_ex_targets,
CAPP_APC_MASTER_LCO_TARGET_MIN_START_BIT,
(CAPP_APC_MASTER_LCO_TARGET_MIN_END_BIT-
CAPP_APC_MASTER_LCO_TARGET_MIN_START_BIT+1));
if (rc_ecmd)
{
FAPI_ERR("proc_chiplet_scominit: Error 0x%x setting APC Master LCO Target register data buffer",
rc_ecmd);
rc.setEcmdError(rc_ecmd);
break;
}
rc = fapiPutScom(i_target,
CAPP_APC_MASTER_LCO_TARGET_0x02013021,
data);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: fapiPutScom error (CAPP_APC_MASTER_LCO_TARGET_0x02013021) on %s",
i_target.toEcmdString());
break;
}
// get dual CAPP presence attribute
FAPI_DBG("proc_chiplet_scominit: Querying dual CAPP feature attribute");
rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_DUAL_CAPP_PRESENT,
&i_target,
dual_capp_present);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: Error querying ATTR_CHIP_EC_FEATURE_DUAL_CAPP_PRESENT");
break;
}
if (dual_capp_present != 0)
{
rc = fapiPutScom(i_target,
CAPP1_APC_MASTER_LCO_TARGET_0x020131A1,
data);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: fapiPutScom error (CAPP1_APC_MASTER_LCO_TARGET_0x020131A1) on %s",
i_target.toEcmdString());
break;
}
}
// execute AS SCOM initfile
FAPI_INF("proc_chiplet_scominit: Executing %s on %s",
PROC_CHIPLET_SCOMINIT_AS_IF, i_target.toEcmdString());
FAPI_EXEC_HWP(
rc,
fapiHwpExecInitFile,
initfile_targets,
PROC_CHIPLET_SCOMINIT_AS_IF);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: Error from fapiHwpExecInitfile executing %s on %s",
PROC_CHIPLET_SCOMINIT_AS_IF,
i_target.toEcmdString());
break;
}
}
else
{
FAPI_DBG("proc_chiplet_scominit: Skipping execution of %s/%s/%s (partial good)",
PROC_CHIPLET_SCOMINIT_NX_IF, PROC_CHIPLET_SCOMINIT_CXA_IF, PROC_CHIPLET_SCOMINIT_AS_IF);
}
// conditionally enable I2C Slave
rc = FAPI_ATTR_GET(ATTR_I2C_SLAVE_ADDRESS,
&i_target,
i2c_slave_address);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: Error querying ATTR_I2C_SLAVE_ADDRESS on %s",
i_target.toEcmdString());
break;
}
rc = fapiGetScom(i_target,
I2C_SLAVE_CONFIG_REG_0x000D0000,
data);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: fapiGetScom error (I2C_SLAVE_CONFIG_REG_0x000D0000) on %s",
i_target.toEcmdString());
break;
}
if (i2c_slave_address)
{
FAPI_DBG("proc_chiplet_scominit: I2C Slave enabled (%s) address = %d",
i_target.toEcmdString(),i2c_slave_address);
//set I2C address
rc_ecmd |= data.insert(i2c_slave_address,0,7);
// disable error state. when this is enabled and there
// is an error from I2CS it locks up the I2CS and no
// more operations are allowed unless cleared
// through FSI. Not good for a FSPless system.
rc_ecmd |= data.clearBit(23);
// enable I2C interface
rc_ecmd |= data.setBit(21);
}
else
{
FAPI_DBG("proc_chiplet_scominit: I2C Slave disabled (%s)",
i_target.toEcmdString());
// disable I2C interface when attribute = 0x0
rc_ecmd |= data.clearBit(21);
}
if (rc_ecmd)
{
FAPI_ERR("proc_chiplet_scominit: Error 0x%x setting I2C Slave register data buffer",
rc_ecmd);
rc.setEcmdError(rc_ecmd);
break;
}
rc = fapiPutScom(i_target,
I2C_SLAVE_CONFIG_REG_0x000D0000,
data);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: fapiPutScom error (I2C_SLAVE_CONFIG_REG_0x000D0000) on %s",
i_target.toEcmdString());
break;
}
// conditionally enable resonant clocking for XBUS
rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_XBUS_RESONANT_CLK_VALID,
&i_target,
enable_xbus_resonant_clocking);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: Error querying ATTR_CHIP_EC_FEATURE_XBUS_RESONANT_CLK_VALID on %s",
i_target.toEcmdString());
break;
}
if (enable_xbus_resonant_clocking)
{
FAPI_DBG("proc_chiplet_scominit: Enabling XBUS resonant clocking");
rc = fapiGetScom(i_target,
MBOX_FSIGP6_0x00050015,
data);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: fapiGetScom error (MBOX_FSIGP6_0x00050015) on %s",
i_target.toEcmdString());
break;
}
rc_ecmd |= data.insertFromRight(
XBUS_RESONANT_CLOCK_CONFIG,
MBOX_FSIGP6_XBUS_RESONANT_CLOCK_CONFIG_START_BIT,
(MBOX_FSIGP6_XBUS_RESONANT_CLOCK_CONFIG_END_BIT-
MBOX_FSIGP6_XBUS_RESONANT_CLOCK_CONFIG_START_BIT+1));
if (rc_ecmd)
{
FAPI_ERR("proc_chiplet_scominit: Error 0x%x setting FSI GP6 register data buffer",
rc_ecmd);
rc.setEcmdError(rc_ecmd);
break;
}
if (is_master)
{
rc = fapiPutScom(i_target,
MBOX_FSIGP6_0x00050015,
data);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: fapiPutScom error (MBOX_FSIGP6_0x00050015) on %s",
i_target.toEcmdString());
break;
}
}
else
{
cfam_data.insert(data, 0, 32, 0);
rc = fapiPutCfamRegister(i_target, CFAM_FSI_GP6_0x00002815, cfam_data);
if (rc)
{
FAPI_ERR("proc_cen_ref_clk_enable: fapiPutCfamRegister error (CFAM_FSI_GP8_0x00001017)");
break;
}
}
}
// execute A/X/PCI/DMI FIR init SCOM initfile
FAPI_INF("proc_chiplet_scominit: Executing %s on %s",
PROC_CHIPLET_SCOMINIT_A_X_PCI_DMI_IF, i_target.toEcmdString());
FAPI_EXEC_HWP(
rc,
fapiHwpExecInitFile,
initfile_targets,
PROC_CHIPLET_SCOMINIT_A_X_PCI_DMI_IF);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: Error from fapiHwpExecInitfile executing %s on %s",
PROC_CHIPLET_SCOMINIT_A_X_PCI_DMI_IF,
i_target.toEcmdString());
break;
}
// execute NV scominit file
uint8_t exist_NV = 0x00;
rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_NV_PRESENT, &i_target, exist_NV);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: Error getting attribute value ATTR_CHIP_EC_FEATURE_NV_PRESENT");
break;
}
if (exist_NV)
{
FAPI_INF("proc_chiplet_scominit: Executing %s on %s",
PROC_CHIPLET_SCOMINIT_NPU_IF, i_target.toEcmdString());
FAPI_EXEC_HWP(
rc,
fapiHwpExecInitFile,
initfile_targets,
PROC_CHIPLET_SCOMINIT_NPU_IF);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: Error from fapiHwpExecInitfile executing %s on %s",
PROC_CHIPLET_SCOMINIT_NPU_IF,
i_target.toEcmdString());
break;
}
// cleanup FIR bit (NPU FIR bit 27) caused by NDL/NTL parity error
rc_ecmd = data.flushTo1();
rc_ecmd = data.clearBit(NPU_FIR_NTL_DL2TL_PARITY_ERR_BIT);
if (rc_ecmd)
{
FAPI_ERR("proc_chiplet_scominit: Error 0x%Xforming NPU FIR cleanup data buffer",
rc_ecmd);
rc.setEcmdError(rc_ecmd);
break;
}
rc = fapiPutScom(i_target, NPU_FIR_AND_0x08013D81, data);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: fapiPutScom error (NPU_FIR_AND_0x08013D81) on %s",
i_target.toEcmdString());
break;
}
rc = fapiPutScom(i_target, NPU_FIR_MASK_AND_0x08013D84, data);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: fapiPutScom error (NPU_FIR_MASK_AND_0x08013D84) on %s",
i_target.toEcmdString());
break;
}
}
else
{
FAPI_INF("proc_chiplet_scominit: NV link logic not present, scom initfile processing skipped");
}
// determine set of functional MCS chiplets
rc = fapiGetChildChiplets(i_target,
fapi::TARGET_TYPE_MCS_CHIPLET,
mcs_targets,
fapi::TARGET_STATE_FUNCTIONAL);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: Error from fapiGetChildChiplets (MCS) on %s",
i_target.toEcmdString());
break;
}
// apply MCS SCOM initfile only for functional chiplets
for (std::vector<fapi::Target>::iterator i = mcs_targets.begin();
(i != mcs_targets.end()) && rc.ok();
i++)
{
// execute MCS SCOM initfile
initfile_targets.clear();
initfile_targets.push_back(*i);
initfile_targets.push_back(i_target);
FAPI_INF("proc_chiplet_scominit: Executing %s on %s",
PROC_CHIPLET_SCOMINIT_MCS_IF, i->toEcmdString());
FAPI_EXEC_HWP(
rc,
fapiHwpExecInitFile,
initfile_targets,
PROC_CHIPLET_SCOMINIT_MCS_IF);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: Error from fapiHwpExecInitfile executing %s on %s",
PROC_CHIPLET_SCOMINIT_MCS_IF,
i->toEcmdString());
break;
}
// determine MCS position
rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &(*i), mcs_pos);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS) on %s",
i->toEcmdString());
break;
}
if (mcs_pos < master_mcs_pos)
{
fapi::Target cen_target_unused;
rc = fapiGetOtherSideOfMemChannel(*i,
cen_target_unused,
fapi::TARGET_STATE_FUNCTIONAL);
// use return code only to indicate presence of connected Centaur,
// do not propogate/emit error if not connected
if (rc.ok())
{
FAPI_DBG("Updating master_mcs_pos to %d", mcs_pos);
FAPI_DBG(" Target: %s", cen_target_unused.toEcmdString());
master_mcs = *i;
master_mcs_pos = mcs_pos;
}
else
{
rc = fapi::FAPI_RC_SUCCESS;
}
}
}
if (!rc.ok())
{
break;
}
if (master_mcs.getType() == fapi::TARGET_TYPE_MCS_CHIPLET)
{
// set MCMODE0Q_ENABLE_CENTAUR_SYNC on first target only
// (this bit is required to be set on at most one MCS/chip)
rc_ecmd |= data.flushTo0();
rc_ecmd |= data.setBit(MCSMODE0_EN_CENTAUR_SYNC_BIT);
rc_ecmd |= mask.setBit(MCSMODE0_EN_CENTAUR_SYNC_BIT);
// check buffer manipulation return codes
if (rc_ecmd)
{
FAPI_ERR("proc_chiplet_scominit: Error 0x%X setting up MCSMODE0 data buffer",
rc_ecmd);
rc.setEcmdError(rc_ecmd);
break;
}
// write register with updated content
rc = fapiPutScomUnderMask(master_mcs,
MCS_MCSMODE0_0x02011807,
data,
mask);
if (!rc.ok())
{
FAPI_ERR("proc_chiplet_scominit: fapiPutScomUnderMask error (MCS_MCSMODE0_0x02011807) on %s",
master_mcs.toEcmdString());
break;
}
}
}
// unsupported target type
else
{
FAPI_ERR("proc_chiplet_scominit: Unsupported target type");
const fapi::Target & TARGET = i_target;
FAPI_SET_HWP_ERROR(rc, RC_PROC_CHIPLET_SCOMINIT_INVALID_TARGET);
break;
}
} while(0);
// mark HWP exit
FAPI_INF("proc_chiplet_scominit: End");
return rc;
}
//******************************************************************************
// fapiGetOtherSideOfMemChannel function
//******************************************************************************
fapi::ReturnCode fapiGetOtherSideOfMemChannel(
const fapi::Target& i_target,
fapi::Target & o_target,
const fapi::TargetState i_state)
{
fapi::ReturnCode l_rc;
TargetHandleList l_targetList;
FAPI_DBG(ENTER_MRK "fapiGetOtherSideOfMemChannel. State: 0x%08x",
i_state);
TargetHandle_t l_target =
reinterpret_cast<TargetHandle_t>(i_target.get());
if (l_target == NULL)
{
FAPI_ERR("fapiGetOtherSideOfMemChannel. Embedded NULL target pointer");
/*@
* @errortype
* @moduleid fapi::MOD_FAPI_GET_OTHER_SIDE_OF_MEM_CHANNEL
* @reasoncode fapi::RC_EMBEDDED_NULL_TARGET_PTR
* @devdesc Target has embedded null target pointer
*/
const bool hbSwError = true;
errlHndl_t l_pError = new ERRORLOG::ErrlEntry(
ERRORLOG::ERRL_SEV_UNRECOVERABLE,
fapi::MOD_FAPI_GET_OTHER_SIDE_OF_MEM_CHANNEL,
fapi::RC_EMBEDDED_NULL_TARGET_PTR,
0, 0, hbSwError);
// Attach the error log to the fapi::ReturnCode
l_rc.setPlatError(reinterpret_cast<void *> (l_pError));
}
else if (i_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET)
{
// find the Centaur that is associated with this MCS
getChildAffinityTargets(l_targetList, l_target,
CLASS_CHIP, TYPE_MEMBUF, false);
if(l_targetList.size() != 1) // one and only one expected
{
FAPI_ERR("fapiGetOtherSideOfMemChannel. expect 1 Centaur %d",
l_targetList.size());
/*@
* @errortype
* @moduleid fapi::MOD_FAPI_GET_OTHER_SIDE_OF_MEM_CHANNEL
* @reasoncode fapi::RC_NO_SINGLE_MEMBUFF
* @userdata1 Number of Memory Buffers
* @userdata2 MCS HUID
* @devdesc fapiGetOtherSideOfMemChannel could not find exactly
* one target on the other side of the correct state
*/
const bool hbSwError = true;
errlHndl_t l_pError = new ERRORLOG::ErrlEntry(
ERRORLOG::ERRL_SEV_UNRECOVERABLE,
fapi::MOD_FAPI_GET_OTHER_SIDE_OF_MEM_CHANNEL,
fapi::RC_NO_SINGLE_MEMBUFF,
l_targetList.size(),
TARGETING::get_huid(l_target),
hbSwError);
// Attach the error log to the fapi::ReturnCode
l_rc.setPlatError(reinterpret_cast<void *> (l_pError));
}
else
{
o_target.setType(fapi::TARGET_TYPE_MEMBUF_CHIP);
o_target.set(reinterpret_cast<void *>(l_targetList[0]));
}
}
else if (i_target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP)
{
// find the MCS that is associated with this Centaur
getParentAffinityTargets (l_targetList, l_target,
CLASS_UNIT, TYPE_MCS, false);
if(l_targetList.size() != 1) // one and only one expected
{
FAPI_ERR("fapiGetOtherSideOfMemChannel. expect 1 MCS %d",
l_targetList.size());
/*@
* @errortype
* @moduleid fapi::MOD_FAPI_GET_OTHER_SIDE_OF_MEM_CHANNEL
* @reasoncode fapi::RC_NO_SINGLE_MCS
* @userdata1 Number of MCSs
* @userdata2 Membuf HUID
* @devdesc fapiGetOtherSideOfMemChannel could not find exactly
* one target on the other side of the correct state
*/
const bool hbSwError = true;
errlHndl_t l_pError = new ERRORLOG::ErrlEntry(
ERRORLOG::ERRL_SEV_UNRECOVERABLE,
fapi::MOD_FAPI_GET_OTHER_SIDE_OF_MEM_CHANNEL,
fapi::RC_NO_SINGLE_MCS,
l_targetList.size(),
TARGETING::get_huid(l_target),
hbSwError);
// Attach the error log to the fapi::ReturnCode
l_rc.setPlatError(reinterpret_cast<void *> (l_pError));
}
else
{
o_target.setType(fapi::TARGET_TYPE_MCS_CHIPLET);
o_target.set(reinterpret_cast<void *>(l_targetList[0]));
}
}
else
{
FAPI_ERR("fapiGetOtherSideOfMemChannel. target 0x%08x not supported",
i_target.getType());
/*@
* @errortype
* @moduleid fapi::MOD_FAPI_GET_OTHER_SIDE_OF_MEM_CHANNEL
* @reasoncode fapi::RC_UNSUPPORTED_REQUEST
* @userdata1 Requested type
* @userdata2 Unsupported Target HUID
* @devdesc fapiGetOtherSideOfMemChannel request for unsupported
* or invalid target type
*/
const bool hbSwError = true;
errlHndl_t l_pError = new ERRORLOG::ErrlEntry(
ERRORLOG::ERRL_SEV_UNRECOVERABLE,
fapi::MOD_FAPI_GET_OTHER_SIDE_OF_MEM_CHANNEL,
fapi::RC_UNSUPPORTED_REQUEST,
i_target.getType(),
TARGETING::get_huid(l_target),
hbSwError);
// Attach the error log to the fapi::ReturnCode
l_rc.setPlatError(reinterpret_cast<void *> (l_pError));
}
if (!l_rc) // OK so far, check that state is as requested
{
HwasState l_state =
l_targetList[0]->getAttr<ATTR_HWAS_STATE>();
if (((i_state == fapi::TARGET_STATE_PRESENT) && !l_state.present) ||
((i_state == fapi::TARGET_STATE_FUNCTIONAL) && !l_state.functional))
{
FAPI_ERR("fapiGetOtherSideOfMemChannel. state mismatch");
/*@
* @errortype
* @moduleid fapi::MOD_FAPI_GET_OTHER_SIDE_OF_MEM_CHANNEL
* @reasoncode fapi::RC_STATE_MISMATCH
* @userdata1 Requested state
* @userdata2 Other Target HUID
* @devdesc fapiGetOtherSideOfMemChannel target not present or
* functional as requested
*/
const bool hbSwError = true;
errlHndl_t l_pError = new ERRORLOG::ErrlEntry(
ERRORLOG::ERRL_SEV_UNRECOVERABLE,
fapi::MOD_FAPI_GET_OTHER_SIDE_OF_MEM_CHANNEL,
fapi::RC_STATE_MISMATCH,
i_state,
TARGETING::get_huid(l_targetList[0]),
hbSwError);
// Attach the error log to the fapi::ReturnCode
l_rc.setPlatError(reinterpret_cast<void *> (l_pError));
}
}
FAPI_DBG(EXIT_MRK "fapiGetOtherSideOfMemChannel. rc = 0x%x",
static_cast<uint32_t>(l_rc));
return l_rc;
}
//******************************************************************************
// fapiGetParentChip function
//******************************************************************************
fapi::ReturnCode fapiGetParentChip(
const fapi::Target& i_chiplet,
fapi::Target & o_chip)
{
FAPI_DBG(ENTER_MRK "fapiGetParentChip");
fapi::ReturnCode l_rc;
// Extract the HostBoot Target pointer for the input chiplet
TARGETING::Target * l_pChiplet =
reinterpret_cast<TARGETING::Target*>(i_chiplet.get());
// Check that the input target is a chiplet
if (!i_chiplet.isChiplet())
{
FAPI_ERR("fapiGetParentChip. Input target type 0x%08x is not a chiplet",
i_chiplet.getType());
/*@
* @errortype
* @moduleid fapi::MOD_FAPI_GET_PARENT_CHIP
* @reasoncode fapi::RC_INVALID_REQUEST
* @userdata1 Type of input target
* @userdata2 Input Target HUID
* @devdesc fapiGetParentChip request for non-chiplet
*/
const bool hbSwError = true;
errlHndl_t l_pError = new ERRORLOG::ErrlEntry(
ERRORLOG::ERRL_SEV_UNRECOVERABLE,
fapi::MOD_FAPI_GET_PARENT_CHIP,
fapi::RC_INVALID_REQUEST,
i_chiplet.getType(),
TARGETING::get_huid(l_pChiplet),
hbSwError);
// Attach the error log to the fapi::ReturnCode
l_rc.setPlatError(reinterpret_cast<void *> (l_pError));
}
else
{
if (l_pChiplet == NULL)
{
/*@
* @errortype
* @moduleid fapi::MOD_FAPI_GET_PARENT_CHIP
* @reasoncode fapi::RC_EMBEDDED_NULL_TARGET_PTR
* @devdesc Target has embedded null target pointer
*/
const bool hbSwError = true;
errlHndl_t l_pError = new ERRORLOG::ErrlEntry(
ERRORLOG::ERRL_SEV_UNRECOVERABLE,
fapi::MOD_FAPI_GET_PARENT_CHIP,
fapi::RC_EMBEDDED_NULL_TARGET_PTR,
0, 0, hbSwError);
// Attach the error log to the fapi::ReturnCode
l_rc.setPlatError(reinterpret_cast<void *> (l_pError));
}
else
{
const TARGETING::Target * l_pChip =
TARGETING::getParentChip(l_pChiplet);
if (l_pChip == NULL)
{
FAPI_ERR("fapiGetParentChip. Parent not found");
/*@
* @errortype
* @moduleid fapi::MOD_FAPI_GET_PARENT_CHIP
* @reasoncode fapi::RC_NO_SINGLE_PARENT
* @userdata1 Input Chiplet Target HUID
* @devdesc fapiGetParentChip did not find one parent
*/
const bool hbSwError = true;
errlHndl_t l_pError = new ERRORLOG::ErrlEntry(
ERRORLOG::ERRL_SEV_UNRECOVERABLE,
fapi::MOD_FAPI_GET_PARENT_CHIP,
fapi::RC_NO_SINGLE_PARENT,
TARGETING::get_huid(l_pChiplet),
0, hbSwError);
// Attach the error log to the fapi::ReturnCode
l_rc.setPlatError(reinterpret_cast<void *> (l_pError));
}
else
{
// Set the output chip type
if (l_pChip->getAttr<TARGETING::ATTR_TYPE>() ==
TARGETING::TYPE_PROC)
{
o_chip.setType(fapi::TARGET_TYPE_PROC_CHIP);
}
else
{
o_chip.setType(fapi::TARGET_TYPE_MEMBUF_CHIP);
}
// Set the output chip (platform specific) handle
o_chip.set(reinterpret_cast<void *>
(const_cast<TARGETING::Target*>(l_pChip)));
}
}
}
FAPI_DBG(EXIT_MRK "fapiGetParentChip");
return l_rc;
}
//******************************************************************************
// fapiGetChildChiplets function
//******************************************************************************
fapi::ReturnCode fapiGetChildChiplets(
const fapi::Target & i_chip,
const fapi::TargetType i_chipletType,
std::vector<fapi::Target> & o_chiplets,
const fapi::TargetState i_state)
{
FAPI_DBG(ENTER_MRK "fapiGetChildChiplets. Chiplet Type:0x%08x State:0x%08x",
i_chipletType, i_state);
fapi::ReturnCode l_rc;
o_chiplets.clear();
// Extract the HostBoot Target pointer for the input chip
TARGETING::Target * l_pChip =
reinterpret_cast<TARGETING::Target*>(i_chip.get());
// Check that the input target is a chip
if (!i_chip.isChip())
{
FAPI_ERR("fapiGetChildChiplets. Input target type 0x%08x is not a chip",
i_chip.getType());
/*@
* @errortype
* @moduleid fapi::MOD_FAPI_GET_CHILD_CHIPLETS
* @reasoncode fapi::RC_INVALID_REQUEST
* @userdata1 Type of input target
* @userdata2 Input Target HUID
* @devdesc fapiGetChildChiplets request for non-chip
*/
const bool hbSwError = true;
errlHndl_t l_pError = new ERRORLOG::ErrlEntry(
ERRORLOG::ERRL_SEV_UNRECOVERABLE,
fapi::MOD_FAPI_GET_CHILD_CHIPLETS,
fapi::RC_INVALID_REQUEST,
i_chip.getType(),
TARGETING::get_huid(l_pChip),
hbSwError);
// Attach the error log to the fapi::ReturnCode
l_rc.setPlatError(reinterpret_cast<void *> (l_pError));
}
else
{
TARGETING::TYPE l_type = TARGETING::TYPE_NA;
if (i_chipletType == fapi::TARGET_TYPE_EX_CHIPLET)
{
l_type = TARGETING::TYPE_EX;
}
else if (i_chipletType == fapi::TARGET_TYPE_MBA_CHIPLET)
{
l_type = TARGETING::TYPE_MBA;
}
else if (i_chipletType == fapi::TARGET_TYPE_MCS_CHIPLET)
{
l_type = TARGETING::TYPE_MCS;
}
else if (i_chipletType == fapi::TARGET_TYPE_XBUS_ENDPOINT)
{
l_type = TARGETING::TYPE_XBUS;
}
else if (i_chipletType == fapi::TARGET_TYPE_ABUS_ENDPOINT)
{
l_type = TARGETING::TYPE_ABUS;
}
else if (i_chipletType == fapi::TARGET_TYPE_L4)
{
l_type = TARGETING::TYPE_L4;
}
else
{
FAPI_ERR("fapiGetChildChiplets. Chiplet type 0x%08x not supported",
i_chipletType);
/*@
* @errortype
* @moduleid fapi::MOD_FAPI_GET_CHILD_CHIPLETS
* @reasoncode fapi::RC_UNSUPPORTED_REQUEST
* @userdata1 Type of requested chiplet
* @userdata2 Input Chip Target HUID
* @devdesc fapiGetChildChiplets request for unsupported
* or invalid chiplet type
*/
const bool hbSwError = true;
errlHndl_t l_pError = new ERRORLOG::ErrlEntry(
ERRORLOG::ERRL_SEV_UNRECOVERABLE,
fapi::MOD_FAPI_GET_CHILD_CHIPLETS,
fapi::RC_UNSUPPORTED_REQUEST,
i_chipletType,
TARGETING::get_huid(l_pChip),
hbSwError);
// Attach the error log to the fapi::ReturnCode
l_rc.setPlatError(reinterpret_cast<void *> (l_pError));
}
if (!l_rc)
{
if (l_pChip == NULL)
{
FAPI_ERR("fapiGetChildChiplets. Embedded NULL target pointer");
/*@
* @errortype
* @moduleid fapi::MOD_FAPI_GET_CHILD_CHIPLETS
* @reasoncode fapi::RC_EMBEDDED_NULL_TARGET_PTR
* @devdesc Target has embedded null target pointer
*/
const bool hbSwError = true;
errlHndl_t l_pError = new ERRORLOG::ErrlEntry(
ERRORLOG::ERRL_SEV_UNRECOVERABLE,
fapi::MOD_FAPI_GET_CHILD_CHIPLETS,
fapi::RC_EMBEDDED_NULL_TARGET_PTR,
0, 0, hbSwError);
// Attach the error log to the fapi::ReturnCode
l_rc.setPlatError(reinterpret_cast<void *> (l_pError));
}
else
{
TARGETING::TargetHandleList l_chipletList;
TARGETING::getChildChiplets(l_chipletList, l_pChip, l_type,
false);
// Return fapi::Targets to the caller
for (TARGETING::TargetHandleList::const_iterator
chipletIter = l_chipletList.begin();
chipletIter != l_chipletList.end();
++chipletIter)
{
TARGETING::HwasState l_state =
(*chipletIter)->getAttr<TARGETING::ATTR_HWAS_STATE>();
// HWPs/FAPI considers partial good chiplets as present, but
// firmware considers them not-present. Return all chiplets
// in the model when caller requests PRESENT
if ((fapi::TARGET_STATE_FUNCTIONAL == i_state) &&
!l_state.functional)
{
continue;
}
fapi::Target l_chiplet(i_chipletType,
reinterpret_cast<void *>(*chipletIter));
o_chiplets.push_back(l_chiplet);
}
}
}
}
FAPI_DBG(EXIT_MRK "fapiGetChildChiplets. %d results", o_chiplets.size());
return l_rc;
}
// HWP entry point, comments in header
fapi::ReturnCode proc_pcie_config(
const fapi::Target & i_target)
{
fapi::ReturnCode rc;
uint8_t pcie_enabled;
uint8_t num_phb;
// mark HWP entry
FAPI_INF("proc_pcie_config: Start");
do
{
// check for supported target type
if (i_target.getType() != fapi::TARGET_TYPE_PROC_CHIP)
{
FAPI_ERR("proc_pcie_config: Unsupported target type");
const fapi::Target & TARGET = i_target;
FAPI_SET_HWP_ERROR(rc, RC_PROC_PCIE_CONFIG_INVALID_TARGET);
break;
}
// query PCIE partial good attribute
rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_ENABLE,
&i_target,
pcie_enabled);
if (!rc.ok())
{
FAPI_ERR("proc_pcie_config: Error querying ATTR_PROC_PCIE_ENABLE");
break;
}
// initialize PBCQ/AIB, configure PBCQ FIRs (only if partial good
// atttribute is set)
if (pcie_enabled == fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE)
{
// determine PHB configuration
rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_NUM_PHB,
&i_target,
num_phb);
if (!rc.ok())
{
FAPI_ERR("proc_pcie_config: Error from FAPI_ATTR_GET (ATTR_PROC_PCIE_NUM_PHB)");
break;
}
rc = proc_pcie_config_pbcq(i_target);
if (!rc.ok())
{
FAPI_ERR("proc_pcie_config: Error from proc_pcie_config_pbcq");
break;
}
rc = proc_pcie_config_pbcq_fir(i_target, num_phb);
if (!rc.ok())
{
FAPI_ERR("proc_pcie_config: Error from proc_pcie_config_pbcq_fir");
break;
}
rc = proc_a_x_pci_dmi_pll_setup_unmask_lock(
i_target,
PCIE_CHIPLET_0x09000000);
if (!rc.ok())
{
FAPI_ERR("proc_pcie_config: Error from proc_a_x_pci_dmi_pll_setup_unmask_lock");
break;
}
}
else
{
FAPI_DBG("proc_pcie_config: Skipping initialization (partial good)");
}
} while(0);
// mark HWP exit
FAPI_INF("proc_pcie_config: End");
return rc;
}
/**
* p8_pm_prep_for_reset Call underlying unit procedure to perform readiness for
* reinitialization of PM complex.
*
* @param[in] i_primary_chip_target Primary Chip target which will be passed
* to all the procedures
* @param[in] i_secondary_chip_target Secondary Chip target will be passed for
* pmc_init -reset only if it is DCM otherwise this should be NULL.
* @param[in] i_mode (PM_RESET (hard - will kill the PMC);
* PM_RESET_SOFT (will not fully reset the PMC))
*
* @retval ECMD_SUCCESS
* @retval ERROR defined in xml
*/
fapi::ReturnCode
p8_pm_prep_for_reset( const fapi::Target &i_primary_chip_target,
const fapi::Target &i_secondary_chip_target,
uint32_t i_mode )
{
fapi::ReturnCode rc;
fapi::ReturnCode rc_hold;
uint32_t e_rc = 0;
std::vector<fapi::Target> l_exChiplets;
ecmdDataBufferBase data(64);
ecmdDataBufferBase mask(64);
uint64_t address = 0;
const char * PM_MODE_NAME_VAR; // Defines storage for PM_MODE_NAME
bool b_special_wakeup_pri = false;
bool b_special_wakeup_sec = false;
fapi::Target dummy;
do
{
FAPI_INF("p8_pm_prep_for_reset start ....");
uint8_t ipl_mode = 0;
rc = FAPI_ATTR_GET(ATTR_IS_MPIPL, NULL, ipl_mode);
if (!rc.ok())
{
FAPI_ERR("fapiGetAttribute of ATTR_IS_MPIPL rc = 0x%x", (uint32_t)rc);
break;
}
FAPI_INF("IPL mode = %s", ipl_mode ? "MPIPL" : "NORMAL");
if (i_mode == PM_RESET)
{
FAPI_INF("Hard reset detected");
}
else if (i_mode == PM_RESET_SOFT)
{
FAPI_INF("Soft reset detected. Idle functions will not be affected");
}
else
{
FAPI_ERR("Mode parameter value not supported: %u", i_mode);
uint32_t & MODE = i_mode;
FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PREP_UNSUPPORTED_MODE_ERR);
break;
}
if ( i_secondary_chip_target.getType() == TARGET_TYPE_NONE )
{
if ( i_primary_chip_target.getType() == TARGET_TYPE_NONE )
{
FAPI_ERR("Set primay target properly for SCM " );
const fapi::Target PRIMARY_TARGET = i_primary_chip_target;
FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PREP_TARGET_ERR);
break;
}
FAPI_INF("Running on SCM");
}
else
{
FAPI_INF("Running on DCM");
}
// ******************************************************************
// Clear the Deep Exit Masks to allow Special Wake-up to occur
// ******************************************************************
// Primary
rc = clear_deep_exit_mask(i_primary_chip_target);
if (rc)
{
FAPI_ERR("clear_deep_exit_mask: Failed for Primary Target %s",
i_primary_chip_target.toEcmdString());
break;
}
// Secondary
if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
{
rc = clear_deep_exit_mask(i_secondary_chip_target);
if (rc)
{
FAPI_ERR("clear_deep_exit_mask: Failed for Secondary Target %s",
i_secondary_chip_target.toEcmdString());
break;
}
}
// ******************************************************************
// FSM trace
// ******************************************************************
rc = p4rs_pcbs_fsm_trace (i_primary_chip_target, i_secondary_chip_target, "start of prep for reset");
if (!rc.ok())
{
break;
}
// ******************************************************************
// Put all EX chiplets in special wakeup
// *****************************************************************
// This is done before FIR masking to ensure that idle functions
// are properly monitored
// Primary
rc = special_wakeup_all (i_primary_chip_target, true);
if (rc)
{
FAPI_ERR("special_wakeup_all - Enable: Failed for Target %s",
i_primary_chip_target.toEcmdString());
break;
}
b_special_wakeup_pri = true;
rc = p8_pm_glob_fir_trace (i_primary_chip_target, "after SPWKUP");
if (!rc.ok()) {
break;
}
// Secondary
if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
{
rc = special_wakeup_all (i_secondary_chip_target, true);
if (rc)
{
FAPI_ERR("special_wakeup_all - Enable: Failed for Target %s",
i_secondary_chip_target.toEcmdString());
break;
}
b_special_wakeup_sec = true;
rc = p8_pm_glob_fir_trace (i_secondary_chip_target, "after SPWKUP");
if (!rc.ok()) {
break;
}
}
// ******************************************************************
// FSM trace
// ******************************************************************
rc = p4rs_pcbs_fsm_trace (i_primary_chip_target, i_secondary_chip_target,
"after special wake-up setting");
if (!rc.ok())
{
break;
}
// ******************************************************************
// Mask the FIRs as error can occur in what follows
// ******************************************************************
FAPI_INF("Executing:p8_pm_firinit in mode PM_RESET");
FAPI_EXEC_HWP(rc, p8_pm_firinit, i_primary_chip_target , i_mode );
if (rc)
{
FAPI_ERR("ERROR: p8_pm_firinit detected failed result");
break;
}
rc = p8_pm_glob_fir_trace (i_primary_chip_target, "after Masking");
if (!rc.ok()) {
break;
}
if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
{
FAPI_EXEC_HWP(rc, p8_pm_firinit, i_secondary_chip_target , PM_RESET );
if (rc)
{
FAPI_ERR("ERROR: p8_pm_firinit detected failed result");
break;
}
rc = p8_pm_glob_fir_trace (i_secondary_chip_target, "after Masking");
if (!rc.ok()) {
break;
}
}
// ******************************************************************
// FSM trace
// ******************************************************************
rc = p4rs_pcbs_fsm_trace (i_primary_chip_target, i_secondary_chip_target,
"after FIR masking");
if (!rc.ok())
{
break;
}
// ******************************************************************
// Disable PMC OCC HEARTBEAT before reset OCC
// ******************************************************************
// Primary
rc = fapiGetScom(i_primary_chip_target, PMC_OCC_HEARTBEAT_REG_0x00062066 , data );
if (rc)
{
FAPI_ERR("fapiGetScom(PMC_OCC_HEARTBEAT_REG_0x00062066) failed.");
break;
}
e_rc = data.clearBit(16);
if (e_rc)
{
FAPI_ERR("ecmdDataBufferBase error setting up PMC_OCC_HEARTBEAT_REG_0x00062066 on master during reset");
rc.setEcmdError(e_rc);
break;
}
rc = fapiPutScom(i_primary_chip_target, PMC_OCC_HEARTBEAT_REG_0x00062066 , data );
if (rc)
{
FAPI_ERR("fapiPutScom(PMC_OCC_HEARTBEAT_REG_0x00062066) failed.");
break;
}
// Secondary
if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
{
rc = fapiGetScom(i_secondary_chip_target, PMC_OCC_HEARTBEAT_REG_0x00062066 , data );
if (rc)
{
FAPI_ERR("fapiGetScom(PMC_OCC_HEARTBEAT_REG_0x00062066) failed.");
break;
}
e_rc = data.clearBit(16);
if (e_rc)
{
FAPI_ERR("ecmdDataBufferBase error setting up PMC_OCC_HEARTBEAT_REG_0x00062066 on slave during reset");
rc.setEcmdError(e_rc);
break;
}
rc = fapiPutScom(i_secondary_chip_target, PMC_OCC_HEARTBEAT_REG_0x00062066 , data );
if (rc)
{
FAPI_ERR("fapiPutScom(PMC_OCC_HEARTBEAT_REG_0x00062066) failed.");
break;
}
}
// ******************************************************************
// Put OCC PPC405 into reset safely
// ******************************************************************
FAPI_INF("Put OCC PPC405 into reset safely");
FAPI_DBG("Executing: p8_occ_control.C");
FAPI_EXEC_HWP(rc, p8_occ_control, i_primary_chip_target, PPC405_RESET_SEQUENCE, 0);
if (rc)
{
FAPI_ERR("p8_occ_control: Failed to prepare OCC for RESET. With rc = 0x%x", (uint32_t)rc);
break;
}
if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
{
FAPI_EXEC_HWP(rc, p8_occ_control, i_secondary_chip_target, PPC405_RESET_SEQUENCE, 0);
if (rc)
{
FAPI_ERR("p8_occ_control: Failed to prepare OCC for RESET. With rc = 0x%x", (uint32_t)rc);
break;
}
}
// ******************************************************************
// FSM trace
// ******************************************************************
rc = p4rs_pcbs_fsm_trace (i_primary_chip_target, i_secondary_chip_target,
"after OCC Reset");
if (!rc.ok())
{
break;
}
// Check for xstops and recoverables
rc = p8_pm_glob_fir_trace (i_primary_chip_target, "after OCC Reset");
if (!rc.ok()) {
break;
}
if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
{
rc = p8_pm_glob_fir_trace (i_secondary_chip_target, "after OCC Reset");
if (!rc.ok()) {
break;
}
}
// ******************************************************************
// Force Vsafe value into voltage controller
// ******************************************************************
FAPI_INF("Force Vsafe value into voltage controller");
FAPI_DBG("Executing: p8_pmc_force_vsafe.C");
// Primary
// Secondary passed in for FFDC reasons upon error
FAPI_EXEC_HWP(rc, p8_pmc_force_vsafe, i_primary_chip_target, i_secondary_chip_target);
if (rc)
{
FAPI_ERR("Failed to force Vsafe value into voltage controller. With rc = 0x%x", (uint32_t)rc);
break;
}
// Secondary
// Primary passed in for FFDC reasons upon error
if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
{
FAPI_EXEC_HWP(rc, p8_pmc_force_vsafe, i_secondary_chip_target, i_primary_chip_target);
if (rc)
{
FAPI_ERR("Failed to force Vsafe value into voltage controller. With rc = 0x%x", (uint32_t)rc);
break;
}
}
// ******************************************************************
// FSM trace
// ******************************************************************
rc = p4rs_pcbs_fsm_trace (i_primary_chip_target, i_secondary_chip_target,
"after force Vsafe");
if (!rc.ok())
{
break;
}
// Check for xstops and recoverables
rc = p8_pm_glob_fir_trace (i_primary_chip_target, "after Force Vsafe");
if (!rc.ok()) {
break;
}
if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
{
rc = p8_pm_glob_fir_trace (i_secondary_chip_target, "after Force Vsafe");
if (!rc.ok()) {
break;
}
}
// ******************************************************************
// Prepare PCBS_PM for RESET
// ******************************************************************
// - p8_pcbs_init internally loops over all enabled chiplets
FAPI_INF("Prepare PCBSLV_PM for RESET");
FAPI_DBG("Executing: p8_pcbs_init.C");
// Primary
FAPI_EXEC_HWP(rc, p8_pcbs_init, i_primary_chip_target, PM_RESET);
if (rc)
{
FAPI_ERR("p8_pcbs_init: Failed to prepare PCBSLV_PM for RESET. With rc = 0x%x", (uint32_t)rc);
break;
}
address = READ_GLOBAL_RECOV_FIR_0x570F001C;
GETSCOM(rc, i_primary_chip_target, address, data);
if (data.getNumBitsSet(0,64))
{
FAPI_INF("Recoverable attention is **ACTIVE** in prep_for_reset after PCBS reset");
}
// Secondary
if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
{
FAPI_EXEC_HWP(rc, p8_pcbs_init, i_secondary_chip_target, PM_RESET);
if (rc)
{
FAPI_ERR("p8_pcbs_init: Failed to prepare PCBSLV_PM for RESET. With rc = 0x%x", (uint32_t)rc);
break;
}
GETSCOM(rc, i_secondary_chip_target, address, data);
if (data.getNumBitsSet(0,64))
{
FAPI_INF("Recoverable attention is **ACTIVE** in prep_for_reset after PCBS reset");
}
}
// ******************************************************************
// FSM trace
// ******************************************************************
rc = p4rs_pcbs_fsm_trace (i_primary_chip_target, i_secondary_chip_target, "after PCBS reset");
if (!rc.ok())
{
break;
}
// Check for xstops and recoverables
rc = p8_pm_glob_fir_trace (i_primary_chip_target, "after PCBS reset");
if (!rc.ok()) {
break;
}
if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
{
rc = p8_pm_glob_fir_trace (i_secondary_chip_target, "after PCBS reset");
if (!rc.ok()) {
break;
}
}
// ******************************************************************
// Reset PMC
// ******************************************************************
FAPI_INF("Issue reset to PMC");
FAPI_DBG("Executing: p8_pmc_init");
FAPI_EXEC_HWP(rc, p8_pmc_init, i_primary_chip_target, i_secondary_chip_target, i_mode);
if (rc)
{
FAPI_ERR("p8_pmc_init: Failed to issue PMC reset. With rc = 0x%x", (uint32_t)rc);
break;
}
// ******************************************************************
// FSM trace
// ******************************************************************
rc = p4rs_pcbs_fsm_trace (i_primary_chip_target, i_secondary_chip_target,
"after PMC reset");
if (!rc.ok())
{
break;
}
// ******************************************************************
// As the PMC reset kills ALL of the configuration, the idle portion
// must be reestablished to allow that portion to operate. This is
// what p8_poreslw_init -init does. Additionally, this lets us drop
// special wake-up before exiting.
// ******************************************************************
// - call p8_poreslw_init.C *chiptarget, ENUM:PM_INIT
//
FAPI_INF("Re-establish PMC Idle configuration");
FAPI_DBG("Executing: p8_poreslw_init in mode %s", PM_MODE_NAME(PM_INIT_PMC));
// Primary
FAPI_EXEC_HWP(rc, p8_poreslw_init, i_primary_chip_target, PM_INIT_PMC);
if (rc)
{
FAPI_ERR("p8_poreslw_init: Failed to to reinialize the idle portion of the PMC. With rc = 0x%x", (uint32_t)rc);
break;
}
// Secondary
if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
{
FAPI_EXEC_HWP(rc, p8_poreslw_init, i_secondary_chip_target, PM_INIT_PMC);
if (rc)
{
FAPI_ERR("p8_poreslw_init: Failed to to reinialize the idle portion of the PMC. With rc = 0x%x", (uint32_t)rc);
break;
}
}
// Check for xstops and recoverables
rc = p8_pm_glob_fir_trace (i_primary_chip_target, "after PMC and SLW reinit");
if (!rc.ok()) {
break;
}
if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
{
rc = p8_pm_glob_fir_trace (i_secondary_chip_target, "after PMC and SLW reinit");
if (!rc.ok()) {
break;
}
}
// ******************************************************************
// Issue reset to PSS macro
// ******************************************************************
FAPI_INF("Issue reset to PSS macro");
FAPI_DBG("Executing: p8_pss_init.C");
// Primary
FAPI_EXEC_HWP(rc, p8_pss_init, i_primary_chip_target, PM_RESET);
if (rc)
{
FAPI_ERR("p8_pss_init: Failed to issue reset to PSS macro. With rc = 0x%x", (uint32_t)rc);
break;
}
// Secondary
if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
{
FAPI_DBG("FAPI_EXEC_HWP(rc, p8_pss_init, i_secondary_chip_target, PM_RESET);");
FAPI_EXEC_HWP(rc, p8_pss_init, i_secondary_chip_target, PM_RESET);
if (rc)
{
FAPI_ERR("p8_pss_init: Failed to issue reset to PSS macro. With rc = 0x%x", (uint32_t)rc);
break;
}
}
// ******************************************************************
// Issue reset to PORE General Purpose Engine
// ******************************************************************
FAPI_INF("Issue reset to PORE General Purpose Engine");
FAPI_DBG("Executing: p8_poregpe_init.C");
// Primary
FAPI_EXEC_HWP(rc, p8_poregpe_init, i_primary_chip_target, PM_RESET, GPEALL );
if (rc)
{
FAPI_ERR("p8_poregpe_init: Failed to issue reset to PORE General Purpose Engine. With rc = 0x%x", (uint32_t)rc);
break;
}
// Secondary
if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
{
FAPI_EXEC_HWP(rc, p8_poregpe_init, i_secondary_chip_target, PM_RESET, GPEALL );
if (rc)
{
FAPI_ERR("p8_poregpe_init: Failed to issue reset to PORE General Purpose Engine. With rc = 0x%x", (uint32_t)rc);
break;
}
}
// ******************************************************************
// Issue reset to PBA
// ******************************************************************
// Note: this voids the channel used by the SLW engine
FAPI_INF("Issue reset to PBA");
FAPI_DBG("Executing: p8_pba_init.C");
// Primary
FAPI_EXEC_HWP(rc, p8_pba_init, i_primary_chip_target, PM_RESET );
if (rc)
{
FAPI_ERR("p8_pba_init: Failed to issue reset to PBA. With rc = 0x%x", (uint32_t)rc);
break;
}
// Secondary
if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
{
FAPI_EXEC_HWP(rc, p8_pba_init, i_secondary_chip_target, PM_RESET );
if (rc)
{
FAPI_ERR("p8_pba_init: Failed to issue reset to PBA. With rc = 0x%x", (uint32_t)rc);
break;
}
}
// Check for xstops and recoverables
rc = p8_pm_glob_fir_trace (i_primary_chip_target, "after PBA reset");
if (!rc.ok()) {
break;
}
if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
{
rc = p8_pm_glob_fir_trace (i_secondary_chip_target, "after PBA reset");
if (!rc.ok()) {
break;
}
}
// ******************************************************************
// Issue reset to OCC-SRAM
// ******************************************************************
FAPI_INF("Issue reset to OCC-SRAM");
FAPI_DBG("Executing: p8_occ_sram_init.C");
// Primary
FAPI_EXEC_HWP(rc, p8_occ_sram_init, i_primary_chip_target, PM_RESET );
if (rc)
{
FAPI_ERR("p8_occ_sram_init: Failed to issue reset to OCC-SRAM. With rc = 0x%x", (uint32_t)rc);
break;
}
// Secondary
if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
{
FAPI_EXEC_HWP(rc, p8_occ_sram_init, i_secondary_chip_target, PM_RESET );
if (rc)
{
FAPI_ERR("p8_occ_sram_init: Failed to issue reset to OCC-SRAM. With rc = 0x%x", (uint32_t)rc);
break;
}
}
// ******************************************************************
// Issue reset to OCB
// ******************************************************************
FAPI_INF("Issue reset to OCB");
FAPI_DBG("Executing: p8_ocb_init.C");
// Primary
FAPI_EXEC_HWP(rc, p8_ocb_init, i_primary_chip_target, PM_RESET,0 , 0, 0, 0, 0, 0 );
if (rc)
{
FAPI_ERR("p8_ocb_init: Failed to issue reset to OCB. With rc = 0x%x", (uint32_t)rc);
break;
}
// Secondary
if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
{
FAPI_EXEC_HWP(rc, p8_ocb_init, i_secondary_chip_target, PM_RESET,0 , 0, 0, 0, 0, 0 );
if (rc)
{
FAPI_ERR("p8_ocb_init: Failed to issue reset to OCB. With rc = 0x%x", (uint32_t)rc);
break;
}
}
// Check for xstops and recoverables
rc = p8_pm_glob_fir_trace (i_primary_chip_target, "after OCB reset");
if (!rc.ok()) {
break;
}
if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
{
rc = p8_pm_glob_fir_trace (i_secondary_chip_target, "after OCB reset");
if (!rc.ok()) {
break;
}
}
// ******************************************************************
// Remove the EX chiplet special wakeups
// *****************************************************************
// Primary
rc = special_wakeup_all (i_primary_chip_target, false);
if (rc)
{
FAPI_ERR("special_wakeup_all - Disable: Failed for Target %s",
i_primary_chip_target.toEcmdString());
break;
}
b_special_wakeup_pri = false;
// Secondary
if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
{
rc = special_wakeup_all (i_secondary_chip_target, false);
if (rc)
{
FAPI_ERR("special_wakeup_all - Disable: Failed for Target %s",
i_secondary_chip_target.toEcmdString());
break;
}
b_special_wakeup_sec = false;
}
// ******************************************************************
// FSM trace
// ******************************************************************
rc = p4rs_pcbs_fsm_trace (i_primary_chip_target, i_secondary_chip_target,
"after special wake-up clearing");
if (!rc.ok())
{
break;
}
// Check for xstops and recoverables
rc = p8_pm_glob_fir_trace (i_primary_chip_target, "after special wake-up clearing");
if (!rc.ok()) {
break;
}
if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
{
rc = p8_pm_glob_fir_trace (i_secondary_chip_target, "after special wake-up clearing");
if (!rc.ok()) {
break;
}
}
} while(0);
// Clear special wakeups that might have been set before a subsequent
// error occured. Only attempts them on targets that have the boolean
// flag set that they were successfully put into special wakeup.
if (!rc.ok())
{
// Save the original RC
rc_hold = rc;
do
{
// Primary
if (b_special_wakeup_pri)
{
// Primary
rc = special_wakeup_all (i_primary_chip_target, false);
if (rc)
{
FAPI_ERR("special_wakeup_all - Disable: Failed during cleanup from a previous error for Target %s",
i_primary_chip_target.toEcmdString());
FAPI_ERR("special_wakeup_all - Disable: The original error is being returned");
fapiLogError(rc, fapi::FAPI_ERRL_SEV_RECOVERED);
break;
}
}
// Secondary
if (b_special_wakeup_sec)
{
rc = special_wakeup_all (i_secondary_chip_target, false);
if (rc)
{
FAPI_ERR("special_wakeup_all - Disable: Failed during cleanup from a previous error for Target %s",
i_primary_chip_target.toEcmdString());
FAPI_ERR("special_wakeup_all - Disable: The original error is being returned");
fapiLogError(rc, fapi::FAPI_ERRL_SEV_RECOVERED);
break;
}
}
} while(0);
// Restore the original RC
rc = rc_hold;
}
FAPI_INF("p8_pm_prep_for_reset end ....");
return rc;
} // Procedure
ReturnCode io_fir_isolation(const fapi::Target &i_target){
ReturnCode o_rc;
uint32_t rc_ecmd=0;
fir_io_interface_t interface;
io_interface_t gcr_interface; // requires different base address for gcr scoms
uint32_t group;
ecmdDataBufferBase fir_data(64);
rc_ecmd|=fir_data.flushTo0();
if(rc_ecmd)
{
o_rc.setEcmdError(rc_ecmd);
return(o_rc);
}
//on dmi
if( (i_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET )){
FAPI_DBG("This is a Processor DMI bus using base DMI scom address");
interface=FIR_CP_IOMC0_P0; // base scom for MC bus
gcr_interface=CP_IOMC0_P0;
o_rc=read_fir_reg(i_target,interface,fir_data);
group=3;
if(o_rc)
return(o_rc);
o_rc=io_error_isolation(i_target,gcr_interface,group,fir_data);
}
//on cen side
else if((i_target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP)){
FAPI_DBG("This is a Centaur DMI bus using base DMI scom address");
interface=FIR_CEN_DMI;
gcr_interface=CEN_DMI;
o_rc=read_fir_reg(i_target,interface,fir_data);
group=0;
if(o_rc)
return(o_rc);
o_rc=io_error_isolation(i_target,gcr_interface,group,fir_data);
}
// on x bus
else if((i_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT)){
FAPI_DBG("This is a X Bus invocation");
interface=FIR_CP_FABRIC_X0;
gcr_interface=CP_FABRIC_X0;
o_rc=read_fir_reg(i_target,interface,fir_data);
group=0;
if(o_rc)
return(o_rc);
o_rc=io_error_isolation(i_target,gcr_interface,group,fir_data);
}
//on a bus
else if((i_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT)){
FAPI_DBG("This is an A Bus invocation");
interface=FIR_CP_FABRIC_A0;
gcr_interface=CP_FABRIC_A0;
o_rc=read_fir_reg(i_target,interface,fir_data);
group=0;
if(o_rc)
return(o_rc);
o_rc=io_error_isolation(i_target,gcr_interface,group,fir_data);
}
else{
FAPI_ERR("Invalid io_fir HWP invocation . Target doesnt belong to DMI/X/A instances");
const fapi::Target & ENDPOINT = i_target;
FAPI_SET_HWP_ERROR(o_rc, IO_FIR_INVALID_INVOCATION_RC);
}
return(o_rc);
}