void TR_PPCRegisterDependencyGroup::assignRegisters(TR::Instruction *currentInstruction,
TR_RegisterKinds kindToBeAssigned,
uint32_t numberOfRegisters,
TR::CodeGenerator *cg)
{
// *this swipeable for debugging purposes
TR::Machine *machine = cg->machine();
TR::Register *virtReg;
TR::RealRegister::RegNum dependentRegNum;
TR::RealRegister *dependentRealReg, *assignedRegister, *realReg;
int i, j;
TR::Compilation *comp = cg->comp();
int num_gprs = 0;
int num_fprs = 0;
int num_vrfs = 0;
// Use to do lookups using real register numbers
TR_PPCRegisterDependencyMap map(_dependencies, numberOfRegisters);
if (!comp->getOption(TR_DisableOOL))
{
for (i = 0; i< numberOfRegisters; i++)
{
virtReg = _dependencies[i].getRegister();
dependentRegNum = _dependencies[i].getRealRegister();
if (dependentRegNum == TR::RealRegister::SpilledReg)
{
TR_ASSERT(virtReg->getBackingStorage(),"should have a backing store if dependentRegNum == spillRegIndex()\n");
if (virtReg->getAssignedRealRegister())
{
// this happens when the register was first spilled in main line path then was reverse spilled
// and assigned to a real register in OOL path. We protected the backing store when doing
// the reverse spill so we could re-spill to the same slot now
traceMsg (comp,"\nOOL: Found register spilled in main line and re-assigned inside OOL");
TR::Node *currentNode = currentInstruction->getNode();
TR::RealRegister *assignedReg = toRealRegister(virtReg->getAssignedRegister());
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(currentNode, (TR::SymbolReference*)virtReg->getBackingStorage()->getSymbolReference(), sizeof(uintptr_t), cg);
TR::InstOpCode::Mnemonic opCode;
TR_RegisterKinds rk = virtReg->getKind();
switch (rk)
{
case TR_GPR:
opCode =TR::InstOpCode::Op_load;
break;
case TR_FPR:
opCode = virtReg->isSinglePrecision() ? TR::InstOpCode::lfs : TR::InstOpCode::lfd;
break;
default:
TR_ASSERT(0, "\nRegister kind not supported in OOL spill\n");
break;
}
TR::Instruction *inst = generateTrg1MemInstruction(cg, opCode, currentNode, assignedReg, tempMR, currentInstruction);
assignedReg->setAssignedRegister(NULL);
virtReg->setAssignedRegister(NULL);
assignedReg->setState(TR::RealRegister::Free);
if (comp->getDebug())
cg->traceRegisterAssignment("Generate reload of virt %s due to spillRegIndex dep at inst %p\n",comp->getDebug()->getName(virtReg),currentInstruction);
cg->traceRAInstruction(inst);
}
if (!(std::find(cg->getSpilledRegisterList()->begin(), cg->getSpilledRegisterList()->end(), virtReg) != cg->getSpilledRegisterList()->end()))
cg->getSpilledRegisterList()->push_front(virtReg);
}
// we also need to free up all locked backing storage if we are exiting the OOL during backwards RA assignment
else if (currentInstruction->isLabel() && virtReg->getAssignedRealRegister())
{
TR::PPCLabelInstruction *labelInstr = (TR::PPCLabelInstruction *)currentInstruction;
TR_BackingStore * location = virtReg->getBackingStorage();
TR_RegisterKinds rk = virtReg->getKind();
int32_t dataSize;
if (labelInstr->getLabelSymbol()->isStartOfColdInstructionStream() && location)
{
traceMsg (comp,"\nOOL: Releasing backing storage (%p)\n", location);
if (rk == TR_GPR)
dataSize = TR::Compiler->om.sizeofReferenceAddress();
else
dataSize = 8;
location->setMaxSpillDepth(0);
cg->freeSpill(location,dataSize,0);
virtReg->setBackingStorage(NULL);
}
}
}
}
for (i = 0; i < numberOfRegisters; i++)
{
map.addDependency(_dependencies[i], i);
virtReg = _dependencies[i].getRegister();
dependentRegNum = _dependencies[i].getRealRegister();
if (dependentRegNum != TR::RealRegister::SpilledReg)
{
if (virtReg->getKind() == TR_GPR)
num_gprs++;
else if (virtReg->getKind() == TR_FPR)
num_fprs++;
else if (virtReg->getKind() == TR_VRF)
num_vrfs++;
}
}
#ifdef DEBUG
int locked_gprs = 0;
int locked_fprs = 0;
int locked_vrfs = 0;
// count up how many registers are locked for each type
for(i = TR::RealRegister::FirstGPR; i <= TR::RealRegister::LastGPR; i++)
{
realReg = machine->getPPCRealRegister((TR::RealRegister::RegNum)i);
if (realReg->getState() == TR::RealRegister::Locked)
locked_gprs++;
}
for(i = TR::RealRegister::FirstFPR; i <= TR::RealRegister::LastFPR; i++)
{
realReg = machine->getPPCRealRegister((TR::RealRegister::RegNum)i);
if (realReg->getState() == TR::RealRegister::Locked)
locked_fprs++;
}
for(i = TR::RealRegister::FirstVRF; i <= TR::RealRegister::LastVRF; i++)
{
realReg = machine->getPPCRealRegister((TR::RealRegister::RegNum)i);
if (realReg->getState() == TR::RealRegister::Locked)
locked_vrfs++;
}
TR_ASSERT( locked_gprs == machine->getNumberOfLockedRegisters(TR_GPR),"Inconsistent number of locked GPRs");
TR_ASSERT( locked_fprs == machine->getNumberOfLockedRegisters(TR_FPR),"Inconsistent number of locked FPRs");
TR_ASSERT( locked_vrfs == machine->getNumberOfLockedRegisters(TR_VRF), "Inconsistent number of locked VRFs");
#endif
// To handle circular dependencies, we block a real register if (1) it is already assigned to a correct
// virtual register and (2) if it is assigned to one register in the list but is required by another.
// However, if all available registers are requested, we do not block in case (2) to avoid all registers
// being blocked.
bool block_gprs = true;
bool block_fprs = true;
bool block_vrfs = true;
TR_ASSERT(num_gprs <= (TR::RealRegister::LastGPR - TR::RealRegister::FirstGPR + 1 - machine->getNumberOfLockedRegisters(TR_GPR)), "Too many GPR dependencies, unable to assign" );
TR_ASSERT(num_fprs <= (TR::RealRegister::LastFPR - TR::RealRegister::FirstFPR + 1 - machine->getNumberOfLockedRegisters(TR_FPR)), "Too many FPR dependencies, unable to assign" );
TR_ASSERT(num_vrfs <= (TR::RealRegister::LastVRF - TR::RealRegister::FirstVRF + 1 - machine->getNumberOfLockedRegisters(TR_VRF)), "Too many VRF dependencies, unable to assign" );
if (num_gprs == (TR::RealRegister::LastGPR - TR::RealRegister::FirstGPR + 1 - machine->getNumberOfLockedRegisters(TR_GPR)))
block_gprs = false;
if (num_fprs == (TR::RealRegister::LastFPR - TR::RealRegister::FirstFPR + 1 - machine->getNumberOfLockedRegisters(TR_FPR)))
block_fprs = false;
if (num_vrfs == (TR::RealRegister::LastVRF - TR::RealRegister::FirstVRF + 1 - machine->getNumberOfLockedRegisters(TR_VRF)))
block_vrfs = false;
for (i = 0; i < numberOfRegisters; i++)
{
virtReg = _dependencies[i].getRegister();
if (virtReg->getAssignedRealRegister()!=NULL)
{
if (_dependencies[i].getRealRegister() == TR::RealRegister::NoReg)
{
virtReg->block();
}
else
{
TR::RealRegister::RegNum assignedRegNum;
assignedRegNum = toRealRegister(virtReg->getAssignedRealRegister())->getRegisterNumber();
// always block if required register and assigned register match;
// block if assigned register is required by other dependency but only if
// any spare registers are left to avoid blocking all existing registers
if (_dependencies[i].getRealRegister() == assignedRegNum ||
(map.getDependencyWithTarget(assignedRegNum) &&
((virtReg->getKind() != TR_GPR || block_gprs) &&
(virtReg->getKind() != TR_FPR || block_fprs) &&
(virtReg->getKind() != TR_VRF || block_vrfs))))
{
virtReg->block();
}
}
}
}
// Assign all virtual regs that depend on a specific real reg that is free
for (i = 0; i < numberOfRegisters; i++)
{
virtReg = _dependencies[i].getRegister();
dependentRegNum = _dependencies[i].getRealRegister();
dependentRealReg = machine->getPPCRealRegister(dependentRegNum);
if (dependentRegNum != TR::RealRegister::NoReg &&
dependentRegNum != TR::RealRegister::SpilledReg &&
dependentRealReg->getState() == TR::RealRegister::Free)
{
assignFreeRegisters(currentInstruction, &_dependencies[i], map, cg);
}
}
// Assign all virtual regs that depend on a specfic real reg that is not free
for (i = 0; i < numberOfRegisters; i++)
{
virtReg = _dependencies[i].getRegister();
assignedRegister = NULL;
if (virtReg->getAssignedRealRegister() != NULL)
{
assignedRegister = toRealRegister(virtReg->getAssignedRealRegister());
}
dependentRegNum = _dependencies[i].getRealRegister();
dependentRealReg = machine->getPPCRealRegister(dependentRegNum);
if (dependentRegNum != TR::RealRegister::NoReg &&
dependentRegNum != TR::RealRegister::SpilledReg &&
dependentRealReg != assignedRegister)
{
bool depsBlocked = false;
switch (_dependencies[i].getRegister()->getKind())
{
case TR_GPR:
depsBlocked = block_gprs;
break;
case TR_FPR:
depsBlocked = block_fprs;
break;
case TR_VRF:
depsBlocked = block_vrfs;
break;
}
assignContendedRegisters(currentInstruction, &_dependencies[i], map, depsBlocked, cg);
}
}
// Assign all virtual regs that depend on NoReg but exclude gr0
for (i=0; i<numberOfRegisters; i++)
{
if (_dependencies[i].getRealRegister() == TR::RealRegister::NoReg && _dependencies[i].getExcludeGPR0())
{
TR::RealRegister *realOne;
virtReg = _dependencies[i].getRegister();
realOne = virtReg->getAssignedRealRegister();
if (realOne!=NULL && toRealRegister(realOne)->getRegisterNumber()==TR::RealRegister::gr0)
{
if ((assignedRegister = machine->findBestFreeRegister(currentInstruction, virtReg->getKind(), true, false, virtReg)) == NULL)
{
assignedRegister = machine->freeBestRegister(currentInstruction, virtReg, NULL, true);
}
machine->coerceRegisterAssignment(currentInstruction, virtReg, assignedRegister->getRegisterNumber());
}
else if (realOne == NULL)
{
machine->assignOneRegister(currentInstruction, virtReg, true);
}
virtReg->block();
}
}
// Assign all virtual regs that depend on NoReg
for (i=0; i<numberOfRegisters; i++)
{
if (_dependencies[i].getRealRegister() == TR::RealRegister::NoReg && !_dependencies[i].getExcludeGPR0())
{
TR::RealRegister *realOne;
virtReg = _dependencies[i].getRegister();
realOne = virtReg->getAssignedRealRegister();
if (!realOne)
{
machine->assignOneRegister(currentInstruction, virtReg, false);
}
virtReg->block();
}
}
unblockRegisters(numberOfRegisters);
for (i = 0; i < numberOfRegisters; i++)
{
TR::Register *dependentRegister = getRegisterDependency(i)->getRegister();
// dependentRegister->getAssignedRegister() is NULL if the reg has already been spilled due to a spilledReg dep
if (comp->getOption(TR_DisableOOL) || (!(cg->isOutOfLineColdPath()) && !(cg->isOutOfLineHotPath())))
{
TR_ASSERT(dependentRegister->getAssignedRegister(),
"assignedRegister can not be NULL");
}
if (dependentRegister->getAssignedRegister())
{
TR::RealRegister *assignedRegister = dependentRegister->getAssignedRegister()->getRealRegister();
if (getRegisterDependency(i)->getRealRegister() == TR::RealRegister::NoReg)
getRegisterDependency(i)->setRealRegister(toRealRegister(assignedRegister)->getRegisterNumber());
machine->decFutureUseCountAndUnlatch(dependentRegister);
}
}
}
void TR_ARMRegisterDependencyGroup::assignRegisters(TR::Instruction *currentInstruction,
TR_RegisterKinds kindToBeAssigned,
uint32_t numberOfRegisters,
TR::CodeGenerator *cg)
{
TR::Compilation *comp = cg->comp();
TR::Machine *machine = cg->machine();
TR::Register *virtReg;
TR::RealRegister::RegNum dependentRegNum;
TR::RealRegister *dependentRealReg, *assignedRegister;
uint32_t i, j;
bool changed;
if (!comp->getOption(TR_DisableOOL))
{
for (i = 0; i< numberOfRegisters; i++)
{
virtReg = dependencies[i].getRegister();
dependentRegNum = dependencies[i].getRealRegister();
if (dependentRegNum == TR::RealRegister::SpilledReg)
{
TR_ASSERT(virtReg->getBackingStorage(),"should have a backing store if dependentRegNum == spillRegIndex()\n");
if (virtReg->getAssignedRealRegister())
{
// this happens when the register was first spilled in main line path then was reverse spilled
// and assigned to a real register in OOL path. We protected the backing store when doing
// the reverse spill so we could re-spill to the same slot now
traceMsg (comp,"\nOOL: Found register spilled in main line and re-assigned inside OOL");
TR::Node *currentNode = currentInstruction->getNode();
TR::RealRegister *assignedReg = toRealRegister(virtReg->getAssignedRegister());
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(currentNode, (TR::SymbolReference*)virtReg->getBackingStorage()->getSymbolReference(), sizeof(uintptr_t), cg);
TR_ARMOpCodes opCode;
TR_RegisterKinds rk = virtReg->getKind();
switch (rk)
{
case TR_GPR:
opCode = ARMOp_ldr;
break;
case TR_FPR:
opCode = virtReg->isSinglePrecision() ? ARMOp_ldfs : ARMOp_ldfd;
break;
default:
TR_ASSERT(0, "\nRegister kind not supported in OOL spill\n");
break;
}
TR::Instruction *inst = generateTrg1MemInstruction(cg, opCode, currentNode, assignedReg, tempMR, currentInstruction);
assignedReg->setAssignedRegister(NULL);
virtReg->setAssignedRegister(NULL);
assignedReg->setState(TR::RealRegister::Free);
if (comp->getDebug())
cg->traceRegisterAssignment("Generate reload of virt %s due to spillRegIndex dep at inst %p\n", cg->comp()->getDebug()->getName(virtReg),currentInstruction);
cg->traceRAInstruction(inst);
}
if (!(std::find(cg->getSpilledRegisterList()->begin(), cg->getSpilledRegisterList()->end(), virtReg) != cg->getSpilledRegisterList()->end()))
cg->getSpilledRegisterList()->push_front(virtReg);
}
// we also need to free up all locked backing storage if we are exiting the OOL during backwards RA assignment
else if (currentInstruction->isLabel() && virtReg->getAssignedRealRegister())
{
TR::ARMLabelInstruction *labelInstr = (TR::ARMLabelInstruction *)currentInstruction;
TR_BackingStore *location = virtReg->getBackingStorage();
TR_RegisterKinds rk = virtReg->getKind();
int32_t dataSize;
if (labelInstr->getLabelSymbol()->isStartOfColdInstructionStream() && location)
{
traceMsg (comp,"\nOOL: Releasing backing storage (%p)\n", location);
if (rk == TR_GPR)
dataSize = TR::Compiler->om.sizeofReferenceAddress();
else
dataSize = 8;
location->setMaxSpillDepth(0);
cg->freeSpill(location,dataSize,0);
virtReg->setBackingStorage(NULL);
}
}
}
}
for (i = 0; i < numberOfRegisters; i++)
{
virtReg = dependencies[i].getRegister();
if (virtReg->getAssignedRealRegister()!=NULL)
{
if (dependencies[i].getRealRegister() == TR::RealRegister::NoReg)
{
virtReg->block();
}
else
{
dependentRegNum = toRealRegister(virtReg->getAssignedRealRegister())->getRegisterNumber();
for (j=0; j<numberOfRegisters; j++)
{
if (dependentRegNum == dependencies[j].getRealRegister())
{
virtReg->block();
break;
}
}
}
}
}
do
{
changed = false;
for (i = 0; i < numberOfRegisters; i++)
{
virtReg = dependencies[i].getRegister();
dependentRegNum = dependencies[i].getRealRegister();
dependentRealReg = machine->getRealRegister(dependentRegNum);
if (dependentRegNum != TR::RealRegister::NoReg &&
dependentRegNum != TR::RealRegister::SpilledReg &&
dependentRealReg->getState() == TR::RealRegister::Free)
{
machine->coerceRegisterAssignment(currentInstruction, virtReg, dependentRegNum);
virtReg->block();
changed = true;
}
}
} while (changed == true);
do
{
changed = false;
for (i = 0; i < numberOfRegisters; i++)
{
virtReg = dependencies[i].getRegister();
assignedRegister = NULL;
if (virtReg->getAssignedRealRegister() != NULL)
{
assignedRegister = toRealRegister(virtReg->getAssignedRealRegister());
}
dependentRegNum = dependencies[i].getRealRegister();
dependentRealReg = machine->getRealRegister(dependentRegNum);
if (dependentRegNum != TR::RealRegister::NoReg &&
dependentRegNum != TR::RealRegister::SpilledReg &&
dependentRealReg != assignedRegister)
{
machine->coerceRegisterAssignment(currentInstruction, virtReg, dependentRegNum);
virtReg->block();
changed = true;
}
}
} while (changed == true);
for (i=0; i<numberOfRegisters; i++)
{
if (dependencies[i].getRealRegister() == TR::RealRegister::NoReg)
{
bool excludeGPR0 = dependencies[i].getExcludeGPR0()?true:false;
TR::RealRegister *realOne;
virtReg = dependencies[i].getRegister();
realOne = virtReg->getAssignedRealRegister();
if (realOne!=NULL && excludeGPR0 && toRealRegister(realOne)->getRegisterNumber()==TR::RealRegister::gr0)
{
if ((assignedRegister = machine->findBestFreeRegister(virtReg->getKind(), true)) == NULL)
{
assignedRegister = machine->freeBestRegister(currentInstruction, virtReg->getKind(), NULL, true);
}
machine->coerceRegisterAssignment(currentInstruction, virtReg, assignedRegister->getRegisterNumber());
}
else if (realOne == NULL)
{
if (virtReg->getTotalUseCount() == virtReg->getFutureUseCount())
{
if ((assignedRegister = machine->findBestFreeRegister(virtReg->getKind(), excludeGPR0, true)) == NULL)
{
assignedRegister = machine->freeBestRegister(currentInstruction, virtReg->getKind(), NULL, excludeGPR0);
}
}
else
{
assignedRegister = machine->reverseSpillState(currentInstruction, virtReg, NULL, excludeGPR0);
}
virtReg->setAssignedRegister(assignedRegister);
assignedRegister->setAssignedRegister(virtReg);
assignedRegister->setState(TR::RealRegister::Assigned);
virtReg->block();
}
}
}
unblockRegisters(numberOfRegisters);
for (i = 0; i < numberOfRegisters; i++)
{
TR::Register *dependentRegister = getRegisterDependency(i)->getRegister();
if (dependentRegister->getAssignedRegister())
{
TR::RealRegister *assignedRegister = dependentRegister->getAssignedRegister()->getRealRegister();
if (getRegisterDependency(i)->getRealRegister() == TR::RealRegister::NoReg)
getRegisterDependency(i)->setRealRegister(toRealRegister(assignedRegister)->getRegisterNumber());
if (dependentRegister->decFutureUseCount() == 0)
{
dependentRegister->setAssignedRegister(NULL);
assignedRegister->setAssignedRegister(NULL);
assignedRegister->setState(TR::RealRegister::Unlatched); // Was setting to Free
}
}
}
}