void Vgen::emit(const ldimmq& i) {
union {
double dval;
int64_t ival;
};
ival = i.s.q();
if (i.d.isSIMD()) {
// Assembler::fmov (which you'd think shouldn't be a macro instruction)
// will emit a ldr from a literal pool if IsImmFP64 is false. vixl's
// literal pools don't work well with our codegen pattern, so if that
// would happen, emit the raw bits into a GPR first and then move them
// unmodified into a SIMD.
if (vixl::Assembler::IsImmFP64(dval)) {
a->Fmov(D(i.d), dval);
} else if (ival == 0) { // careful: dval==0.0 is true for -0.0
// 0.0 is not encodeable as an immediate to Fmov, but this works.
a->Fmov(D(i.d), vixl::xzr);
} else {
a->Mov(rAsm, ival); // XXX avoid scratch register somehow.
a->Fmov(D(i.d), rAsm);
}
} else {
a->Mov(X(i.d), ival);
}
}
void Vgen::emit(const copy& i) {
if (i.s.isGP() && i.d.isGP()) {
a->Mov(X(i.d), X(i.s));
} else if (i.s.isSIMD() && i.d.isGP()) {
a->Fmov(X(i.d), D(i.s));
} else if (i.s.isGP() && i.d.isSIMD()) {
a->Fmov(D(i.d), X(i.s));
} else {
assertx(i.s.isSIMD() && i.d.isSIMD());
a->Fmov(D(i.d), D(i.s));
}
}
