OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1); OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE | A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) | A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff)); OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1); OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER)); OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1); OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) | A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) | A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) | A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) | A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) | A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) | A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) | A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP)); OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1); OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0.0)); OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); OUT_RING(ring, 0); /* VFD_INDEX_MIN */ OUT_RING(ring, 2); /* VFD_INDEX_MAX */ OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */ OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */ OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1); OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) | A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
static void
fd3_draw(struct fd_context *ctx, const struct pipe_draw_info *info)
{
unsigned dirty = ctx->dirty;
struct fd3_shader_key key = {
/* do binning pass first: */
.binning_pass = true,
.color_two_side = ctx->rasterizer ? ctx->rasterizer->light_twoside : false,
// TODO set .half_precision based on render target format,
// ie. float16 and smaller use half, float32 use full..
.half_precision = !!(fd_mesa_debug & FD_DBG_FRAGHALF),
};
draw_impl(ctx, info, ctx->binning_ring,
dirty & ~(FD_DIRTY_BLEND), key);
/* and now regular (non-binning) pass: */
key.binning_pass = false;
draw_impl(ctx, info, ctx->ring, dirty, key);
}
/* binning pass cmds for a clear:
* NOTE: newer blob drivers don't use binning for clear, which is probably
* preferable since it is low vtx count. However that doesn't seem to
* actually work for me. Not sure if it is depending on support for
* clear pass (rather than using solid-fill shader), or something else
* that newer blob is doing differently. Once that is figured out, we
* can remove fd3_clear_binning().
*/
static void
fd3_clear_binning(struct fd_context *ctx, unsigned dirty)
{
struct fd3_context *fd3_ctx = fd3_context(ctx);
struct fd_ringbuffer *ring = ctx->binning_ring;
struct fd3_shader_key key = {
.binning_pass = true,
.half_precision = true,
};
fd3_emit_state(ctx, ring, &ctx->solid_prog, dirty, key);
fd3_emit_vertex_bufs(ring, fd3_shader_variant(ctx->solid_prog.vp, key),
(struct fd3_vertex_buf[]) {{
.prsc = fd3_ctx->solid_vbuf,
.stride = 12,
.format = PIPE_FORMAT_R32G32B32_FLOAT,
}}, 1);
OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
OUT_RING(ring, 0); /* VFD_INDEX_MIN */
OUT_RING(ring, 2); /* VFD_INDEX_MAX */
OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
OUT_RING(ring, 0xffffffff); /* PC_RESTART_INDEX */
OUT_PKT3(ring, CP_EVENT_WRITE, 1);
OUT_RING(ring, PERFCOUNTER_STOP);
fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
}
static void
fd3_clear(struct fd_context *ctx, unsigned buffers,
const union pipe_color_union *color, double depth, unsigned stencil)
{
struct fd3_context *fd3_ctx = fd3_context(ctx);
struct fd_ringbuffer *ring = ctx->ring;
unsigned dirty = ctx->dirty;
unsigned ce, i;
struct fd3_shader_key key = {
.half_precision = true,
};
dirty &= FD_DIRTY_VIEWPORT | FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR;
dirty |= FD_DIRTY_PROG;
fd3_clear_binning(ctx, dirty);
/* emit generic state now: */
fd3_emit_state(ctx, ring, &ctx->solid_prog, dirty, key);
OUT_PKT0(ring, REG_A3XX_RB_BLEND_ALPHA, 1);
OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
OUT_RINGP(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER),
&fd3_ctx->rbrc_patches);
if (buffers & PIPE_CLEAR_DEPTH) {
OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS));
OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_ZOFFSET, 2);
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(depth));
ctx->dirty |= FD_DIRTY_VIEWPORT;
} else {
OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
}
if (buffers & PIPE_CLEAR_STENCIL) {
OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(stencil) |
A3XX_RB_STENCILREFMASK_STENCILMASK(stencil) |
A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
0xff000000 | // XXX ???
A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE) |
A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
} else {
OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
OUT_RING(ring, A3XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
A3XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
}
if (buffers & PIPE_CLEAR_COLOR) {
ce = 0xf;
} else {
ce = 0x0;
}
for (i = 0; i < 4; i++) {
OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_ALWAYS) |
A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(ce));
OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO) |
A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE);
}
OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
fd3_emit_vertex_bufs(ring, fd3_shader_variant(ctx->solid_prog.vp, key),
(struct fd3_vertex_buf[]) {{
.prsc = fd3_ctx->solid_vbuf,
.stride = 12,
.format = PIPE_FORMAT_R32G32B32_FLOAT,
}}, 1);
fd_wfi(ctx, ring);
fd3_emit_constant(ring, SB_FRAG_SHADER, 0, 0, 4, color->ui, NULL);
OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
OUT_RING(ring, 0); /* VFD_INDEX_MIN */
OUT_RING(ring, 2); /* VFD_INDEX_MAX */
OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
OUT_RING(ring, 0xffffffff); /* PC_RESTART_INDEX */
OUT_PKT3(ring, CP_EVENT_WRITE, 1);
OUT_RING(ring, PERFCOUNTER_STOP);
fd_draw(ctx, ring, DI_PT_RECTLIST, USE_VISIBILITY,
DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
}
void
fd3_draw_init(struct pipe_context *pctx)
{
struct fd_context *ctx = fd_context(pctx);
ctx->draw = fd3_draw;
ctx->clear = fd3_clear;
}
static void
fd3_clear(struct fd_context *ctx, unsigned buffers,
const union pipe_color_union *color, double depth, unsigned stencil)
{
struct fd3_context *fd3_ctx = fd3_context(ctx);
struct fd_ringbuffer *ring = ctx->ring;
unsigned ce, i;
/* emit generic state now: */
fd3_emit_state(ctx, ctx->dirty & (FD_DIRTY_VIEWPORT |
FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR));
OUT_PKT0(ring, REG_A3XX_RB_BLEND_ALPHA, 1);
OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
fd3_emit_rbrc_draw_state(ring,
A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
if (buffers & PIPE_CLEAR_DEPTH) {
OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS));
OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_ZOFFSET, 2);
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(depth));
ctx->dirty |= FD_DIRTY_VIEWPORT;
} else {
OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
}
if (buffers & PIPE_CLEAR_STENCIL) {
OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(stencil) |
A3XX_RB_STENCILREFMASK_STENCILMASK(stencil) |
A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
0xff000000 | // XXX ???
A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE) |
A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
} else {
OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
OUT_RING(ring, A3XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
A3XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
}
if (buffers & PIPE_CLEAR_COLOR) {
ce = 0xf;
} else {
ce = 0x0;
}
for (i = 0; i < 4; i++) {
OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(12) |
A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_ALWAYS) |
A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(ce));
OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO) |
A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE);
}
OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
fd3_program_emit(ring, &ctx->solid_prog);
fd3_emit_vertex_bufs(ring, &ctx->solid_prog, (struct fd3_vertex_buf[]) {
{ .prsc = fd3_ctx->solid_vbuf, .stride = 12, .format = PIPE_FORMAT_R32G32B32_FLOAT },
}, 1);
static void
fd3_emit_tile_gmem2mem(struct fd_context *ctx, uint32_t xoff, uint32_t yoff,
uint32_t bin_w, uint32_t bin_h)
{
struct fd3_context *fd3_ctx = fd3_context(ctx);
struct fd_ringbuffer *ring = ctx->ring;
struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
OUT_RING(ring, 0xff000000 |
A3XX_RB_STENCILREFMASK_STENCILREF(0) |
A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
OUT_RING(ring, 0xff000000 |
A3XX_RB_STENCILREFMASK_STENCILREF(0) |
A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width/2.0 - 0.5));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width/2.0));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb->height/2.0 - 0.5));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb->height/2.0));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
fd3_emit_rbrc_draw_state(ring,
A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
A3XX_GRAS_SC_CONTROL_RASTER_MODE(1));
OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
OUT_RING(ring, 0); /* VFD_INDEX_MIN */
OUT_RING(ring, 2); /* VFD_INDEX_MAX */
OUT_RING(ring, 0); /* VFD_INSTANCEID_OFFSET */
OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
fd3_program_emit(ring, &ctx->solid_prog);
fd3_emit_vertex_bufs(ring, &ctx->solid_prog, (struct fd3_vertex_buf[]) {
{ .prsc = fd3_ctx->solid_vbuf, .stride = 12, .format = PIPE_FORMAT_R32G32B32_FLOAT },
}, 1);
void *
fd3_zsa_state_create(struct pipe_context *pctx,
const struct pipe_depth_stencil_alpha_state *cso)
{
struct fd3_zsa_stateobj *so;
so = CALLOC_STRUCT(fd3_zsa_stateobj);
if (!so)
return NULL;
so->base = *cso;
so->rb_depth_control |=
A3XX_RB_DEPTH_CONTROL_ZFUNC(cso->depth.func); /* maps 1:1 */
if (cso->depth.enabled)
so->rb_depth_control |=
A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE;
if (cso->depth.writemask)
so->rb_depth_control |= A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE;
if (cso->stencil[0].enabled) {
const struct pipe_stencil_state *s = &cso->stencil[0];
so->rb_stencil_control |=
A3XX_RB_STENCIL_CONTROL_STENCIL_READ |
A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
A3XX_RB_STENCIL_CONTROL_FUNC(s->func) | /* maps 1:1 */
A3XX_RB_STENCIL_CONTROL_FAIL(fd_stencil_op(s->fail_op)) |
A3XX_RB_STENCIL_CONTROL_ZPASS(fd_stencil_op(s->zpass_op)) |
A3XX_RB_STENCIL_CONTROL_ZFAIL(fd_stencil_op(s->zfail_op));
so->rb_stencilrefmask |=
0xff000000 | /* ??? */
A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(s->writemask) |
A3XX_RB_STENCILREFMASK_STENCILMASK(s->valuemask);
if (cso->stencil[1].enabled) {
const struct pipe_stencil_state *bs = &cso->stencil[1];
so->rb_stencil_control |=
A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
A3XX_RB_STENCIL_CONTROL_FUNC_BF(bs->func) | /* maps 1:1 */
A3XX_RB_STENCIL_CONTROL_FAIL_BF(fd_stencil_op(bs->fail_op)) |
A3XX_RB_STENCIL_CONTROL_ZPASS_BF(fd_stencil_op(bs->zpass_op)) |
A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(fd_stencil_op(bs->zfail_op));
so->rb_stencilrefmask_bf |=
0xff000000 | /* ??? */
A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(bs->writemask) |
A3XX_RB_STENCILREFMASK_STENCILMASK(bs->valuemask);
}
}
if (cso->alpha.enabled) {
so->rb_render_control =
A3XX_RB_RENDER_CONTROL_ALPHA_TEST |
A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(cso->alpha.func);
so->rb_alpha_ref =
A3XX_RB_ALPHA_REF_UINT(cso->alpha.ref_value * 255.0) |
A3XX_RB_ALPHA_REF_FLOAT(cso->alpha.ref_value);
so->rb_depth_control |=
A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
}
return so;
}
