/****************************************************************************** Function Name : ADC0__Config (from Inga Harris' Nucleus ADC0_ Validation) Engineer : r54940 Date : 04/08/08 Parameters : Returns : NONE Notes : Configures ADC0_ ******************************************************************************/ void ADC_Config(ADC_MemMapPtr adcmap, uint8_t CONFIG1, uint8_t CONFIG2, uint16_t COMPARE1, uint16_t COMPARE2, uint8_t STATUS2, uint8_t STATUS3, uint8_t STATUS1A, uint8_t STATUS1B, uint32_t PGA ) { ADC_CFG1_REG(adcmap) = CONFIG1; ADC_CFG2_REG(adcmap) = CONFIG2; ADC_CV1_REG(adcmap) = COMPARE1; ADC_CV2_REG(adcmap) = COMPARE2; ADC_SC2_REG(adcmap) = STATUS2; ADC_SC3_REG(adcmap) = STATUS3; ADC_SC1_REG(adcmap,A) = STATUS1A; ADC_SC1_REG(adcmap,B) = STATUS1B; ADC_PGA_REG(adcmap) = PGA; }
void ADC_Config_Alt(ADC_MemMapPtr adcmap, tADC_ConfigPtr ADC_CfgPtr) { ADC_CFG1_REG(adcmap) = ADC_CfgPtr->CONFIG1; ADC_CFG2_REG(adcmap) = ADC_CfgPtr->CONFIG2; ADC_CV1_REG(adcmap) = ADC_CfgPtr->COMPARE1; ADC_CV2_REG(adcmap) = ADC_CfgPtr->COMPARE2; ADC_SC2_REG(adcmap) = ADC_CfgPtr->STATUS2; ADC_SC3_REG(adcmap) = ADC_CfgPtr->STATUS3; ADC_PGA_REG(adcmap) = ADC_CfgPtr->PGA; ADC_SC1_REG(adcmap,A)= ADC_CfgPtr->STATUS1A; ADC_SC1_REG(adcmap,B)= ADC_CfgPtr->STATUS1B; }
int adc_init() { adc_pixelIndex = 0; // disable ADC irq - not ready yet disable_irq(ADC_IRQ_NUM); // turn on clock to ADC0 SIM_SCGC6 |= (SIM_SCGC6_ADC0_MASK); // to setup SW trigger on FTM2 SIM_SOPT7 = SIM_SOPT7_ADC0TRGSEL(10); // to calibrate the ADC module unsigned short cal_var; cal_var = 0x0000; // add the plus-side calibration results cal_var += ADC_CLP0_REG(ADC0_BASE_PTR); cal_var += ADC_CLP1_REG(ADC0_BASE_PTR); cal_var += ADC_CLP2_REG(ADC0_BASE_PTR); cal_var += ADC_CLP3_REG(ADC0_BASE_PTR); cal_var += ADC_CLP4_REG(ADC0_BASE_PTR); cal_var += ADC_CLPS_REG(ADC0_BASE_PTR); cal_var /= 2; cal_var |= 0x8000; // store value in plus-side gain calibration register (PG) ADC_PG_REG(ADC0_BASE_PTR) = ADC_PG_PG(cal_var); cal_var = 0x0000; // add the minus-side calibration results cal_var += ADC_CLM0_REG(ADC0_BASE_PTR); cal_var += ADC_CLM1_REG(ADC0_BASE_PTR); cal_var += ADC_CLM2_REG(ADC0_BASE_PTR); cal_var += ADC_CLM3_REG(ADC0_BASE_PTR); cal_var += ADC_CLM4_REG(ADC0_BASE_PTR); cal_var += ADC_CLMS_REG(ADC0_BASE_PTR); cal_var /= 2; cal_var |= 0x8000; // store value in minus-side gain calibration register (MG) ADC_MG_REG(ADC0_BASE_PTR) = ADC_MG_MG(cal_var); ADC_SC3_REG(ADC0_BASE_PTR) &= ~ADC_SC3_CAL_MASK; // to set the configuration register 1 (CFG1) to select the mode of // operation, clock source, clock divide, and configuration for low // power or long sample time ADC_CFG1_REG(ADC0_BASE_PTR) = ADLPC_NORMAL | ADC_CFG1_ADIV(ADIV_1) | ADLSMP_SHORT | ADC_CFG1_MODE(MODE_8) | ADC_CFG1_ADICLK(ADICLK_BUS); // to set the configuration register 2 (CFG2) to select the special // high-speed configuration for very high speed conversions and // select the long sample time duration during long sample mode ADC_CFG2_REG(ADC0_BASE_PTR) = MUXSEL_ADCA | ADACKEN_DISABLED | ADHSC_HISPEED | ADC_CFG2_ADLSTS(ADLSTS_2); // to configure the status and control register 2 (SC2) ADC_SC2_REG(ADC0_BASE_PTR) = ADTRG_SW | ACFE_DISABLED | ACFGT_GREATER | ACREN_DISABLED | DMAEN_DISABLED | ADC_SC2_REFSEL(REFSEL_EXT); // to configure the status and control register 3 (SC3) // enable hw averaging, 16 samples taken ADC_SC3_REG(ADC0_BASE_PTR) = CAL_OFF | ADCO_SINGLE | AVGE_ENABLED | ADC_SC3_AVGS(AVGS_16); // to configure the status and control register 1 (SC1) // enable the interrupt, single-ended conversion, on AD18 ADC_SC1_REG(ADC0_BASE_PTR, A)= AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(18); // to configure the PGA register ADC_PGA_REG(ADC0_BASE_PTR) = PGAEN_DISABLED | PGACHP_NOCHOP | PGALP_NORMAL | ADC_PGA_PGAG(PGAG_64); // enable ADC irq enable_irq(ADC_IRQ_NUM); return ADC_RET_SUCCESS; }