void
ar9002_hw_pa_cal(struct ath_hal *ah, HAL_BOOL is_reset)
{
if (AR_SREV_KITE_11_OR_LATER(ah)) {
if (is_reset || !AH9285(ah)->pacal_info.skipcount)
ar9285_hw_pa_cal(ah, is_reset);
else
AH9285(ah)->pacal_info.skipcount--;
}
}
static void
ar9285WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
u_int modesIndex, freqIndex;
int regWrites = 0;
/* Setup the indices for the next set of register array writes */
/* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
freqIndex = 2;
if (IEEE80211_IS_CHAN_HT40(chan))
modesIndex = 3;
else if (IEEE80211_IS_CHAN_108G(chan))
modesIndex = 5;
else
modesIndex = 4;
/* Set correct Baseband to analog shift setting to access analog chips. */
OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
modesIndex, regWrites);
if (AR_SREV_KITE_12_OR_LATER(ah)) {
regWrites = ath_hal_ini_write(ah, &AH9285(ah)->ah_ini_txgain,
modesIndex, regWrites);
}
regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
1, regWrites);
}
static void
ar9285WriteIni(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
{
u_int modesIndex, freqIndex;
int regWrites = 0;
/* Setup the indices for the next set of register array writes */
/* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
freqIndex = 2;
if (IS_CHAN_HT40(chan))
modesIndex = 3;
else if (IS_CHAN_108G(chan))
modesIndex = 5;
else
modesIndex = 4;
/* Set correct Baseband to analog shift setting to access analog chips. */
OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
modesIndex, regWrites);
if (AR_SREV_KITE_12_OR_LATER(ah)) {
regWrites = ath_hal_ini_write(ah, &AH9285(ah)->ah_ini_txgain,
modesIndex, regWrites);
}
regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
1, regWrites);
OS_REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
uint32_t val;
val = OS_REG_READ(ah, AR_PCU_MISC_MODE2) &
(~AR_PCU_MISC_MODE2_HWWAR1);
OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
OS_REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
}
}
static void
ar9285_hw_pa_cal(struct ath_hal *ah, HAL_BOOL is_reset)
{
uint32_t regVal;
int i, offset, offs_6_1, offs_0;
uint32_t ccomp_org, reg_field;
uint32_t regList[][2] = {
{ 0x786c, 0 },
{ 0x7854, 0 },
{ 0x7820, 0 },
{ 0x7824, 0 },
{ 0x7868, 0 },
{ 0x783c, 0 },
{ 0x7838, 0 },
};
/* PA CAL is not needed for high power solution */
if (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL) ==
AR5416_EEP_TXGAIN_HIGH_POWER)
return;
HALDEBUG(ah, HAL_DEBUG_PERCAL, "Running PA Calibration\n");
for (i = 0; i < N(regList); i++)
regList[i][1] = OS_REG_READ(ah, regList[i][0]);
regVal = OS_REG_READ(ah, 0x7834);
regVal &= (~(0x1));
OS_REG_WRITE(ah, 0x7834, regVal);
regVal = OS_REG_READ(ah, 0x9808);
regVal |= (0x1 << 27);
OS_REG_WRITE(ah, 0x9808, regVal);
OS_REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
OS_REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
OS_REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
OS_REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
ccomp_org = MS(OS_REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
OS_REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
OS_DELAY(30);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
for (i = 6; i > 0; i--) {
regVal = OS_REG_READ(ah, 0x7834);
regVal |= (1 << (19 + i));
OS_REG_WRITE(ah, 0x7834, regVal);
OS_DELAY(1);
regVal = OS_REG_READ(ah, 0x7834);
regVal &= (~(0x1 << (19 + i)));
reg_field = MS(OS_REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
regVal |= (reg_field << (19 + i));
OS_REG_WRITE(ah, 0x7834, regVal);
}
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
OS_DELAY(1);
reg_field = MS(OS_REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
offs_6_1 = MS(OS_REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
offs_0 = MS(OS_REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
offset = (offs_6_1<<1) | offs_0;
offset = offset - 0;
offs_6_1 = offset>>1;
offs_0 = offset & 1;
if ((!is_reset) && (AH9285(ah)->pacal_info.prev_offset == offset)) {
if (AH9285(ah)->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
AH9285(ah)->pacal_info.max_skipcount =
2 * AH9285(ah)->pacal_info.max_skipcount;
AH9285(ah)->pacal_info.skipcount = AH9285(ah)->pacal_info.max_skipcount;
} else {
AH9285(ah)->pacal_info.max_skipcount = 1;
AH9285(ah)->pacal_info.skipcount = 0;
AH9285(ah)->pacal_info.prev_offset = offset;
}
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
regVal = OS_REG_READ(ah, 0x7834);
regVal |= 0x1;
OS_REG_WRITE(ah, 0x7834, regVal);
regVal = OS_REG_READ(ah, 0x9808);
regVal &= (~(0x1 << 27));
OS_REG_WRITE(ah, 0x9808, regVal);
for (i = 0; i < N(regList); i++)
OS_REG_WRITE(ah, regList[i][0], regList[i][1]);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
}