void shutdownAudio(void)
{
// close codec.
AIC3106_writeRegister(AIC3106_REG_PAGESELECT, 0);
AIC3106_writeRegister(AIC3106_REG_RESET, 0x80);
// close mcasp.
MCASP->SRCTL0 = 0;
MCASP->SRCTL1 = 0;
MCASP->SRCTL2 = 0;
MCASP->SRCTL3 = 0;
MCASP->SRCTL5 = 0;
MCASP->SRCTL11 = 0;
MCASP->SRCTL12 = 0;
MCASP->GBLCTL = 0;
}
void AIC3106_Init_TTO(void)
{
// select page 0 and reset codec.
AIC3106_writeRegister(AIC3106_REG_PAGESELECT, 0);
AIC3106_writeRegister(AIC3106_REG_RESET, 0x80);
// config codec regs. please see AIC3106 documentation for explanation.
// Document Num: TLV320AIC3106
#ifdef FS_48KHZ // 48kHz sampling rate
AIC3106_writeRegister(3,
(0 << 7) | // PLL is disabled
(4 << 3) | // PLL Q value = 4
(2 << 0)); // PLL P value = 2
//0x22); // PLL disabled, Q=4, P=2
AIC3106_writeRegister(2,
(0 << 4) | // ADC fs = fs(ref)/1
(0 << 0)); // DAC fs = fs(ref)/1
//0x00); //ADC/DAC sample rate = f(s)/1 = MCLK/(128*Q)/1
#endif
#ifdef FS_8KHz
AIC3106_writeRegister(3,
(0 << 7) | // PLL is disabled
(4 << 3) | // PLL Q value = 4
(2 << 0)); // PLL P value = 2
//AIC3106_writeRegister(3, 0x22); // PLL disabled, Q=4, P=2
AIC3106_writeRegister(2,
(10 << 4) | // ADC fs = fs(ref)/6
(10 << 0)); // DAC fs = fs(ref)/6
//AIC3106_writeRegister(2, 0xAA); //ADC/DAC sample rate = f(s)/6 = MCLK/(128*Q)/6
#endif
#ifdef FS_10KHz // it's actually 9.6kHz
AIC3106_writeRegister(3,
(0 << 7) | // PLL is disabled
(10 << 3) | // PLL Q value = 10
(2 << 0)); // PLL P value = 2
//AIC3106_writeRegister(3, (0 << 7) | (10 << 3) | (2 << 0)); // PLL disabled, Q=10, P=2
AIC3106_writeRegister(2,
(2 << 4) | // ADC fs = fs(ref)/6
(2 << 0)); // DAC fs = fs(ref)/6
//AIC3106_writeRegister(2, 0x22); //ADC/DAC sample rate = f(s)/2 = MCLK/(128*Q)/2
#endif
AIC3106_writeRegister(7,
(0 << 7) | // fs(ref) = 48kHz (needed only for AGC time constants, not used)
(0 << 6) | // ADC dual rate mode is disabled
(0 << 5) | // DAC dual rate mode is disabled
(1 << 3) | // left DAC datapath plays left channel input data
(1 << 1) | // right DAC datapath plays right channel input data
(0 << 0)); // reserved
//0x0A);
AIC3106_writeRegister(8,
(0 << 7) | // BCLK is input (use "1" for output)
(0 << 6) | // WCLK is input (use "1" for output)
(0 << 5) | // do no place DOUT in high-z when inactive
(0 << 4) | // BCLK & WCLK disabled in master mode if code powered down
(0 << 3) | // reserved
(0 << 2) | // disable 3D effect
(0 << 0)); // digital mic support disabled
//0xC0); // BCLK and WCLK are output
AIC3106_writeRegister(9,
(0 << 6) | // serial data bus in i2s mode
(3 << 4) | // audio word length 32 bits
(0 << 3) | // continuous transfer mode
(0 << 2) | // don't resync DAC w/ group delay variation
(0 << 1) | // don't resync ADC w/ group delay variation
(0 << 0)); // resync w/o soft muting
//0x30); // I2S mode, 32-bit data words, continous xfer mode
//AIC3106_writeRegister(10, 0x00); // data word offset
#if 1 // turn input gain off
// PGA setting, 0 means 0dB gain
AIC3106_writeRegister(15,
(0 << 7) | // left ADC PGA is not muted
(0 << 0)); // left ADC PGA gain setting = 0 dB
//(0);
AIC3106_writeRegister(16,
(0 << 7) | // right ADC PGA is not muted
(0 << 0)); // right ADC PGA gain setting = 0 dB
//(0);
#else // turn input gain on
AIC3106_writeRegister(15,
(0 << 7) | // left ADC PGA is not muted
(44 << 0)); // left ADC PGA gain setting = 22 dB
//(0);
AIC3106_writeRegister(16,
(0 << 7) | // right ADC PGA is not muted
(44 << 0)); // right ADC PGA gain setting = 22 dB
#endif
AIC3106_writeRegister(19, 0x04); // left ADC is powered up
AIC3106_writeRegister(22, 0x04); // right ADC is powered up
AIC3106_writeRegister(27, 0); // left AGC maximum gain allowed is 0dB (AGC not used)
AIC3106_writeRegister(30, 0); // right AGC maximum gain allowed is 0dB (AGC not used)
AIC3106_writeRegister(37,
(1 << 7) | // left DAC powered up
(1 << 6) | // right DAC powered up
(2 << 4) | // HPLCOM configured as independent single-ended output (not used here)
(0 << 0)); // reserved
//0xE0);
// set the DAC gain
AIC3106_writeRegister(43,
(0 << 7) | // left DAC channel is not muted
(0 << 0)); // left DAC gain setting = 0dB
AIC3106_writeRegister(44,
(0 << 7) | // right DAC channel is not muted
(0 << 0)); // left DAC gain setting = 0dB
#if 0
// set the DAC gain
AIC3106_writeRegister(43,
(0 << 7) | // left DAC channel is not muted
(0x28 << 0)); // left DAC gain setting = -20dB
AIC3106_writeRegister(44,
(0 << 7) | // right DAC channel is not muted
(0x28 << 0)); // left DAC gain setting = -20dB
#endif
AIC3106_writeRegister(82,
(1 << 7) | // DAC_L1 is routed to LEFT_LOP/M
(0 << 0)); // DAC_L1 to LEFT_LOP/M analog volum control
//0x80);
AIC3106_writeRegister(86,
(4 << 4) | // LEFT_LOP/M output level control = 0dB
(1 << 3) | // LEFT_LOP/M is not muted
(0 << 2) | // reserved, read only
(0 << 1) | // read only
(1 << 0)); // read only (must write 1 for some reason)
// 0x09);
AIC3106_writeRegister(92,
(1 << 7) | // DAC_R1 is routed to RIGHT_LOP/M
(0 << 0)); // DAC_R1 to RIGHT_LOP/M analog volum control
//0x80);
AIC3106_writeRegister(93,
(4 << 4) | // RIGHT_LOP/M output level control = 0dB
(1 << 3) | // RIGHT_LOP/M is not muted
(0 << 2) | // reserved, read only
(0 << 1) | // read only
(1 << 0)); // read only (must write 1 for some reason)
// 0x09);
AIC3106_writeRegister(101,
(0 << 6) | // read only
(0 << 5) | // MFP3 pin as GPI disabled
(0 << 3) | // read only
(0 << 2) | // MFP2 pin as GPO disabled
(0 << 1) | // MFP2 drives low when configured as GPO
(1 << 0)); // CODEC_CLKIN uses CLKDIV_OUT
//0x01);
AIC3106_writeRegister(102,
(0 << 6) | // CLKDIV_IN uses MCLK
(0 << 4) | // PLLCLK_IN uses MCLK
(0 << 0)); // PLL clock divider N = 16
//0); // CLKDIV_IN uses MCLK
}
//-----------------------------------------------------------------------------
// /brief Initialize the audio codec
//
// /param none
//
// /return uint32_t ERR_NO_ERROR on sucess
//
//-----------------------------------------------------------------------------
uint32_t AIC3106_init(void)
{
// select page 0 and reset codec.
AIC3106_writeRegister(AIC3106_REG_PAGESELECT, 0);
AIC3106_writeRegister(AIC3106_REG_RESET, 0x80);
// config codec regs. please see AIC3106 documentation for explination.
// Document Num: TLV320AIC3106
AIC3106_writeRegister(3, 0x22);
AIC3106_writeRegister(4, 0x20);
AIC3106_writeRegister(5, 0x6E);
AIC3106_writeRegister(6, 0x23);
AIC3106_writeRegister(7, 0x0A);
AIC3106_writeRegister(8, 0x00);
AIC3106_writeRegister(9, 0x00);
AIC3106_writeRegister(10, 0x00);
AIC3106_writeRegister(15, 0);
AIC3106_writeRegister(16, 0);
AIC3106_writeRegister(19, 0x04);
AIC3106_writeRegister(22, 0x04);
AIC3106_writeRegister(27, 0);
AIC3106_writeRegister(30, 0);
AIC3106_writeRegister(37, 0xE0);
AIC3106_writeRegister(38, 0x10);
AIC3106_writeRegister(43, 10);
AIC3106_writeRegister(44, 10);
AIC3106_writeRegister(58, 0);
AIC3106_writeRegister(72, 0);
AIC3106_writeRegister(82, 0x80);
AIC3106_writeRegister(86, 0x09);
AIC3106_writeRegister(92, 0x80);
AIC3106_writeRegister(93, 0x09);
AIC3106_writeRegister(101, 0x01);
AIC3106_writeRegister(102, 0);
AIC3106_writeRegister(43, 0x28); //turn down the L DAC gain
AIC3106_writeRegister(44, 0x28); //turn down the R DAC gain
return (ERR_NO_ERROR);
}
