static int __init gpio_test_init(void)
{
const struct wl12xx_platform_data *wlan_data;
wlan_data = wl12xx_get_platform_data();
bt_enable_pin = wlan_data->bt_enable_gpio;
/* Default to alpha EVM in case the element is not initialized */
if (! bt_enable_pin)
{
pr_info("BT Enable pin is not initialized, defaulting to EVM Rev 1.0A.\n");
bt_enable_pin = GPIO_TO_PIN(1, 31);
}
/* Select pad conf register based on EVM board rev */
if ( bt_enable_pin == GPIO_TO_PIN(3, 21) )
selected_pad = AM33XX_CONTROL_PADCONF_MCASP0_AHCLKX_OFFSET;
else
selected_pad = AM33XX_CONTROL_PADCONF_GPMC_CSN2_OFFSET;
printk("Gpio value is :%d\n", bt_enable_pin);
gpio_direction_output(bt_enable_pin, 0);
msleep(1);
printk("WL1271: BT Enable\n");
gpio_direction_output(bt_enable_pin, 1);
/* Enable pullup on the enable pin for keeping BT active during suspend */
pad_mux_value = readl(AM33XX_CTRL_REGADDR(selected_pad));
pad_mux_value &= (~AM33XX_PULL_DISA);
writel(pad_mux_value, AM33XX_CTRL_REGADDR(selected_pad));
return 0;
}
void am33xx_cpsw_init(unsigned int gigen)
{
u32 mac_lo, mac_hi;
u32 i;
mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_LO);
mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_HI);
am33xx_cpsw_slaves[0].mac_addr[0] = mac_hi & 0xFF;
am33xx_cpsw_slaves[0].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
am33xx_cpsw_slaves[0].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
am33xx_cpsw_slaves[0].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
am33xx_cpsw_slaves[0].mac_addr[4] = mac_lo & 0xFF;
am33xx_cpsw_slaves[0].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
/* Read MACID0 from eeprom if eFuse MACID is invalid */
if (!is_valid_ether_addr(am33xx_cpsw_slaves[0].mac_addr)) {
for (i = 0; i < ETH_ALEN; i++)
am33xx_cpsw_slaves[0].mac_addr[i] = am33xx_macid0[i];
}
mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_LO);
mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_HI);
am33xx_cpsw_slaves[1].mac_addr[0] = mac_hi & 0xFF;
am33xx_cpsw_slaves[1].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
am33xx_cpsw_slaves[1].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
am33xx_cpsw_slaves[1].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
am33xx_cpsw_slaves[1].mac_addr[4] = mac_lo & 0xFF;
am33xx_cpsw_slaves[1].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
/* Read MACID1 from eeprom if eFuse MACID is invalid */
if (!is_valid_ether_addr(am33xx_cpsw_slaves[1].mac_addr)) {
for (i = 0; i < ETH_ALEN; i++)
am33xx_cpsw_slaves[1].mac_addr[i] = am33xx_macid1[i];
}
if (am33xx_evmid == BEAGLE_BONE_OLD) {
__raw_writel(RMII_MODE_ENABLE,
AM33XX_CTRL_REGADDR(MAC_MII_SEL));
} else if (am33xx_evmid == BEAGLE_BONE_A3) {
__raw_writel(MII_MODE_ENABLE,
AM33XX_CTRL_REGADDR(MAC_MII_SEL));
} else if (am33xx_evmid == IND_AUT_MTR_EVM) {
am33xx_cpsw_slaves[0].phy_id = "0:1e";
am33xx_cpsw_slaves[1].phy_id = "0:00";
} else {
__raw_writel(RGMII_MODE_ENABLE,
AM33XX_CTRL_REGADDR(MAC_MII_SEL));
}
am33xx_cpsw_pdata.gigabit_en = gigen;
memcpy(am33xx_cpsw_pdata.mac_addr,
am33xx_cpsw_slaves[0].mac_addr, ETH_ALEN);
platform_device_register(&am33xx_cpsw_mdiodevice);
platform_device_register(&am33xx_cpsw_device);
clk_add_alias(NULL, dev_name(&am33xx_cpsw_mdiodevice.dev),
NULL, &am33xx_cpsw_device.dev);
}
static void __exit gpio_test_exit(void)
{
printk("WL1271: BT Disable\n");
gpio_direction_output(bt_enable_pin, 0);
/* Disable pullup on the enable pin to allow BT shut down during suspend */
pad_mux_value = readl(AM33XX_CTRL_REGADDR(selected_pad));
pad_mux_value |= AM33XX_PULL_DISA;
writel(pad_mux_value, AM33XX_CTRL_REGADDR(selected_pad));
}
static void d_can_hw_raminit(unsigned int instance, unsigned int enable)
{
u32 val;
/* Read the value */
val = readl(AM33XX_CTRL_REGADDR(AM33XX_DCAN_RAMINIT_OFFSET));
if (enable) {
/* Set to "1" */
val &= ~AM33XX_DCAN_RAMINIT_START(instance);
val |= AM33XX_DCAN_RAMINIT_START(instance);
writel(val, AM33XX_CTRL_REGADDR(AM33XX_DCAN_RAMINIT_OFFSET));
} else {
/* Set to "0" */
val &= ~AM33XX_DCAN_RAMINIT_START(instance);
writel(val, AM33XX_CTRL_REGADDR(AM33XX_DCAN_RAMINIT_OFFSET));
}
}
static void d_can_hw_raminit(unsigned int instance)
{
u32 val;
/* Read the value */
val = __raw_readl(AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET));
/* Modify by setting "0" */
val &= ~AM33XX_D_CAN_RAMINIT_START(instance);
__raw_writel(val, AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET));
/* Reset to one */
val |= AM33XX_D_CAN_RAMINIT_START(instance);
__raw_writel(val, AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET));
/* Give some time delay for transition from 0 -> 1 */
udelay(1);
}
/**
* map_xbar_event_to_channel - maps a crossbar event to a DMA channel
* according to the configuration provided
* @event: the event number for which mapping is required
* @channel: channel being activated
* @xbar_event_mapping: array that has the event to channel map
*
* Events that are routed by default are not mapped. Only events that
* are crossbar mapped are routed to available channels according to
* the configuration provided
*
* Returns zero on success, else negative errno.
*/
int map_xbar_event_to_channel(unsigned int event, unsigned int *channel,
struct event_to_channel_map *xbar_event_mapping)
{
unsigned int ctrl = 0;
unsigned int xbar_evt_no = 0;
unsigned int val = 0;
unsigned int offset = 0;
unsigned int mask = 0;
ctrl = EDMA_CTLR(event);
xbar_evt_no = event - (edma_cc[ctrl]->num_channels);
if (event < edma_cc[ctrl]->num_channels) {
*channel = event;
} else if (event < edma_cc[ctrl]->num_events) {
*channel = xbar_event_mapping[xbar_evt_no].channel_no;
/* confirm the range */
if (*channel < EDMA_MAX_DMACH)
clear_bit(*channel, edma_cc[ctrl]->edma_unused);
mask = (*channel)%4;
offset = (*channel)/4;
offset *= 4;
offset += mask;
val = (unsigned int)__raw_readl(AM33XX_CTRL_REGADDR(
AM33XX_SCM_BASE_EDMA + offset));
val = val & (~(0xFF));
val = val | (xbar_event_mapping[xbar_evt_no].xbar_event_no);
__raw_writel(val,
AM33XX_CTRL_REGADDR(AM33XX_SCM_BASE_EDMA + offset));
return 0;
} else {
return -EINVAL;
}
return 0;
}
DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
/* Oscillator clock */
/* 19.2, 24, 25 or 26 MHz */
static const char *sys_clkin_ck_parents[] = {
"virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck",
"virt_26000000_ck",
};
/*
* sys_clk in: input to the dpll and also used as funtional clock for,
* adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
*
*/
DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT,
AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH,
0, NULL);
/* External clock - 12 MHz */
DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0);
/* Module clocks and DPLL outputs */
/* DPLL_CORE */
static struct dpll_data dpll_core_dd = {
.mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE,
.clk_bypass = &sys_clkin_ck,
.clk_ref = &sys_clkin_ck,
.control_reg = AM33XX_CM_CLKMODE_DPLL_CORE,
static struct clk tclkin_ck = {
.name = "tclkin_ck",
.rate = 12000000,
.ops = &clkops_null,
};
/*
* sys_clk in: input to the dpll and also used as funtional clock for,
* adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
*
*/
static struct clk sys_clkin_ck = {
.name = "sys_clkin_ck",
.parent = &virt_24000000_ck,
.init = &omap2_init_clksel_parent,
.clksel_reg = AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
.clksel_mask = AM33XX_CONTROL_STATUS_SYSBOOT1_MASK,
.clksel = sys_clkin_sel,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
};
/* DPLL_CORE */
static struct dpll_data dpll_core_dd = {
.mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE,
.clk_bypass = &sys_clkin_ck,
.clk_ref = &sys_clkin_ck,
.control_reg = AM33XX_CM_CLKMODE_DPLL_CORE,
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
.idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE,
.mult_mask = AM33XX_DPLL_MULT_MASK,
int am33xx_cpsw_init(enum am33xx_cpsw_mac_mode mode, unsigned char *phy_id0,
unsigned char *phy_id1)
{
struct omap_hwmod *oh;
struct platform_device *pdev;
u32 mac_lo, mac_hi, gmii_sel;
u32 i;
mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_LO);
mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_HI);
am33xx_cpsw_slaves[0].mac_addr[0] = mac_hi & 0xFF;
am33xx_cpsw_slaves[0].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
am33xx_cpsw_slaves[0].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
am33xx_cpsw_slaves[0].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
am33xx_cpsw_slaves[0].mac_addr[4] = mac_lo & 0xFF;
am33xx_cpsw_slaves[0].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
/* Read MACID0 from eeprom if eFuse MACID is invalid */
if (!is_valid_ether_addr(am33xx_cpsw_slaves[0].mac_addr)) {
for (i = 0; i < ETH_ALEN; i++)
am33xx_cpsw_slaves[0].mac_addr[i] = am33xx_macid0[i];
}
mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_LO);
mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_HI);
am33xx_cpsw_slaves[1].mac_addr[0] = mac_hi & 0xFF;
am33xx_cpsw_slaves[1].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
am33xx_cpsw_slaves[1].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
am33xx_cpsw_slaves[1].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
am33xx_cpsw_slaves[1].mac_addr[4] = mac_lo & 0xFF;
am33xx_cpsw_slaves[1].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
/* Read MACID1 from eeprom if eFuse MACID is invalid */
if (!is_valid_ether_addr(am33xx_cpsw_slaves[1].mac_addr)) {
for (i = 0; i < ETH_ALEN; i++)
am33xx_cpsw_slaves[1].mac_addr[i] = am33xx_macid1[i];
}
switch (mode) {
case AM33XX_CPSW_MODE_MII:
gmii_sel = AM33XX_MII_MODE_EN;
break;
case AM33XX_CPSW_MODE_RMII:
gmii_sel = AM33XX_RMII_MODE_EN;
break;
case AM33XX_CPSW_MODE_RGMII:
gmii_sel = AM33XX_RGMII_MODE_EN;
break;
case CALIXTO_EVM_ETHERNET_INTERFACE:
gmii_sel = CALIXTO_EVM_ETHERNET_MODE_EN;
break;
default:
return -EINVAL;
}
writel(gmii_sel, AM33XX_CTRL_REGADDR(AM33XX_CONTROL_GMII_SEL_OFFSET));
if (phy_id0 != NULL)
am33xx_cpsw_slaves[0].phy_id = phy_id0;
if (phy_id1 != NULL)
am33xx_cpsw_slaves[1].phy_id = phy_id1;
memcpy(am33xx_cpsw_pdata.mac_addr,
am33xx_cpsw_slaves[0].mac_addr, ETH_ALEN);
oh = omap_hwmod_lookup("mdio");
if (!oh) {
pr_err("could not find cpgmac0 hwmod data\n");
return -ENODEV;
}
pdev = omap_device_build("davinci_mdio", 0, oh, &am33xx_cpsw_mdiopdata,
sizeof(am33xx_cpsw_mdiopdata), NULL, 0, 0);
if (IS_ERR(pdev))
pr_err("could not build omap_device for cpsw\n");
oh = omap_hwmod_lookup("cpgmac0");
if (!oh) {
pr_err("could not find cpgmac0 hwmod data\n");
return -ENODEV;
}
pdev = omap_device_build("cpsw", -1, oh, &am33xx_cpsw_pdata,
sizeof(am33xx_cpsw_pdata), NULL, 0, 0);
if (IS_ERR(pdev))
pr_err("could not build omap_device for cpsw\n");
return 0;
}
DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
/* Oscillator clock */
/* 19.2, 24, 25 or 26 MHz */
static const char *sys_clkin_ck_parents[] = {
"virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck",
"virt_26000000_ck",
};
/*
* sys_clk in: input to the dpll and also used as funtional clock for,
* adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
*
*/
DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT,
AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH,
0, NULL);
/* External clock - 12 MHz */
DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0);
/* Module clocks and DPLL outputs */
/* DPLL_CORE */
static struct dpll_data dpll_core_dd = {
.mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE,
.clk_bypass = &sys_clkin_ck,
.clk_ref = &sys_clkin_ck,
.control_reg = AM33XX_CM_CLKMODE_DPLL_CORE,
static void save_padconf(void)
{
lp_padconf.mii1_col = readl(AM33XX_CTRL_REGADDR(0x0908));
lp_padconf.mii1_crs = readl(AM33XX_CTRL_REGADDR(0x090c));
lp_padconf.mii1_rxerr = readl(AM33XX_CTRL_REGADDR(0x0910));
lp_padconf.mii1_txen = readl(AM33XX_CTRL_REGADDR(0x0914));
lp_padconf.mii1_rxdv = readl(AM33XX_CTRL_REGADDR(0x0918));
lp_padconf.mii1_txd3 = readl(AM33XX_CTRL_REGADDR(0x091c));
lp_padconf.mii1_txd2 = readl(AM33XX_CTRL_REGADDR(0x0920));
lp_padconf.mii1_txd1 = readl(AM33XX_CTRL_REGADDR(0x0924));
lp_padconf.mii1_txd0 = readl(AM33XX_CTRL_REGADDR(0x0928));
lp_padconf.mii1_txclk = readl(AM33XX_CTRL_REGADDR(0x092c));
lp_padconf.mii1_rxclk = readl(AM33XX_CTRL_REGADDR(0x0930));
lp_padconf.mii1_rxd3 = readl(AM33XX_CTRL_REGADDR(0x0934));
lp_padconf.mii1_rxd2 = readl(AM33XX_CTRL_REGADDR(0x0938));
lp_padconf.mii1_rxd1 = readl(AM33XX_CTRL_REGADDR(0x093c));
lp_padconf.mii1_rxd0 = readl(AM33XX_CTRL_REGADDR(0x0940));
lp_padconf.rmii1_refclk = readl(AM33XX_CTRL_REGADDR(0x0944));
lp_padconf.mdio_data = readl(AM33XX_CTRL_REGADDR(0x0948));
lp_padconf.mdio_clk = readl(AM33XX_CTRL_REGADDR(0x094c));
gmii_sel = readl(AM33XX_CTRL_REGADDR(0x0650));
/* sdio */
lp_padconf.gpmc_a1 = readl(AM33XX_CTRL_REGADDR(0x0844));
lp_padconf.gpmc_a2 = readl(AM33XX_CTRL_REGADDR(0x0848));
lp_padconf.gpmc_a3 = readl(AM33XX_CTRL_REGADDR(0x084c));
lp_padconf.gpmc_ben1 = readl(AM33XX_CTRL_REGADDR(0x0878));
lp_padconf.gpmc_csn3 = readl(AM33XX_CTRL_REGADDR(0x0888));
lp_padconf.gpmc_clk = readl(AM33XX_CTRL_REGADDR(0x088c));
/* uart1 */
lp_padconf.uart1_ctsn = readl(AM33XX_CTRL_REGADDR(0x0978));
lp_padconf.uart1_rtsn = readl(AM33XX_CTRL_REGADDR(0x097C));
lp_padconf.uart1_rxd = readl(AM33XX_CTRL_REGADDR(0x0980));
lp_padconf.uart1_txd = readl(AM33XX_CTRL_REGADDR(0x0984));
}
static void restore_padconf(void)
{
writel(lp_padconf.mii1_col, AM33XX_CTRL_REGADDR(0x0908));
writel(lp_padconf.mii1_crs, AM33XX_CTRL_REGADDR(0x090c));
writel(lp_padconf.mii1_rxerr, AM33XX_CTRL_REGADDR(0x0910));
writel(lp_padconf.mii1_txen, AM33XX_CTRL_REGADDR(0x0914));
writel(lp_padconf.mii1_rxdv, AM33XX_CTRL_REGADDR(0x0918));
writel(lp_padconf.mii1_txd3, AM33XX_CTRL_REGADDR(0x091c));
writel(lp_padconf.mii1_txd2, AM33XX_CTRL_REGADDR(0x0920));
writel(lp_padconf.mii1_txd1, AM33XX_CTRL_REGADDR(0x0924));
writel(lp_padconf.mii1_txd0, AM33XX_CTRL_REGADDR(0x0928));
writel(lp_padconf.mii1_txclk, AM33XX_CTRL_REGADDR(0x092c));
writel(lp_padconf.mii1_rxclk, AM33XX_CTRL_REGADDR(0x0930));
writel(lp_padconf.mii1_rxd3, AM33XX_CTRL_REGADDR(0x0934));
writel(lp_padconf.mii1_rxd2, AM33XX_CTRL_REGADDR(0x0938));
writel(lp_padconf.mii1_rxd1, AM33XX_CTRL_REGADDR(0x093c));
writel(lp_padconf.mii1_rxd0, AM33XX_CTRL_REGADDR(0x0940));
writel(lp_padconf.rmii1_refclk, AM33XX_CTRL_REGADDR(0x0944));
writel(lp_padconf.mdio_data, AM33XX_CTRL_REGADDR(0x0948));
writel(lp_padconf.mdio_clk, AM33XX_CTRL_REGADDR(0x094c));
writel(gmii_sel, AM33XX_CTRL_REGADDR(0x0650));
/* sdio */
writel(lp_padconf.gpmc_a1, AM33XX_CTRL_REGADDR(0x0844));
writel(lp_padconf.gpmc_a2, AM33XX_CTRL_REGADDR(0x0848));
writel(lp_padconf.gpmc_a3, AM33XX_CTRL_REGADDR(0x084c));
writel(lp_padconf.gpmc_ben1, AM33XX_CTRL_REGADDR(0x0878));
writel(lp_padconf.gpmc_csn3, AM33XX_CTRL_REGADDR(0x0888));
writel(lp_padconf.gpmc_clk, AM33XX_CTRL_REGADDR(0x088c));
/* Uart1 */
writel(lp_padconf.uart1_ctsn, AM33XX_CTRL_REGADDR(0x0978));
writel(lp_padconf.uart1_rtsn, AM33XX_CTRL_REGADDR(0x097C));
writel(lp_padconf.uart1_rxd, AM33XX_CTRL_REGADDR(0x0980));
writel(lp_padconf.uart1_txd, AM33XX_CTRL_REGADDR(0x0984));
}
