Пример #1
0
static void
ath_hal_dumpqcu(FILE *fd, int what)
{
	int i;

	/* QCU registers */
	fprintf(fd, "%-8s %08x  %-8s %08x  %-8s %08x\n"
		, "Q_TXE", OS_REG_READ(ah, AR_Q_TXE)
		, "Q_TXD", OS_REG_READ(ah, AR_Q_TXD)
		, "Q_RDYTIMSHD", OS_REG_READ(ah, AR_Q_RDYTIMESHDN)
	);
	fprintf(fd, "Q_ONESHOTARM_SC %08x  Q_ONESHOTARM_CC %08x\n"
		, OS_REG_READ(ah, AR_Q_ONESHOTARM_SC)
		, OS_REG_READ(ah, AR_Q_ONESHOTARM_CC)
	);
	for (i = 0; i < 10; i++)
		fprintf(fd, "Q[%u] TXDP %08x CBR %08x RDYT %08x MISC %08x STS %08x\n"
			, i
			, OS_REG_READ(ah, AR_QTXDP(i))
			, OS_REG_READ(ah, AR_QCBRCFG(i))
			, OS_REG_READ(ah, AR_QRDYTIMECFG(i))
			, OS_REG_READ(ah, AR_QMISC(i))
			, OS_REG_READ(ah, AR_QSTS(i))
		);
}
void 
ar9300_tx99_tgt_start(struct ath_hal *ah, u_int8_t data)
{
    a_uint32_t val;
    a_uint32_t qnum = (a_uint32_t)data;

    /* Disable AGC to A2 */
    OS_REG_WRITE(ah, AR_PHY_TEST, (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR) );
    OS_REG_WRITE(ah, 0x9864, OS_REG_READ(ah, 0x9864) | 0x7f000);
    OS_REG_WRITE(ah, 0x9924, OS_REG_READ(ah, 0x9924) | 0x7f00fe);
    OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS);
    //OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) | (AR_DIAG_FORCE_RX_CLEAR+AR_DIAG_IGNORE_VIRT_CS));
    OS_REG_WRITE(ah, AR_CR, AR_CR_RXD);     // set receive disable
    //set CW_MIN and CW_MAX both to 0, AIFS=2
    OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
    OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); //50 OK
    OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);
    OS_REG_WRITE(ah, AR_TIME_OUT, 0x00000400); //200 ok for HT20, 400 ok for HT40 
    OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
    
    /* set QCU modes to early termination */
    val = OS_REG_READ(ah, AR_QMISC(qnum));
    OS_REG_WRITE(ah, AR_QMISC(qnum), val | AR_Q_MISC_DCU_EARLY_TERM_REQ);
}
Пример #3
0
Файл: mac.c Проект: 020gzh/linux
bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
{
	struct ath_common *common = ath9k_hw_common(ah);
	struct ath9k_tx_queue_info *qi;
	u32 cwMin, chanCwMin, value;

	qi = &ah->txq[q];
	if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
		ath_dbg(common, QUEUE, "Reset TXQ, inactive queue: %u\n", q);
		return true;
	}

	ath_dbg(common, QUEUE, "Reset TX queue: %u\n", q);

	if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
		chanCwMin = INIT_CWMIN;

		for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1);
	} else
		cwMin = qi->tqi_cwmin;

	ENABLE_REGWRITE_BUFFER(ah);

	REG_WRITE(ah, AR_DLCL_IFS(q),
		  SM(cwMin, AR_D_LCL_IFS_CWMIN) |
		  SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) |
		  SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));

	REG_WRITE(ah, AR_DRETRY_LIMIT(q),
		  SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |
		  SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) |
		  SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));

	REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);

	if (AR_SREV_9340(ah) && !AR_SREV_9340_13_OR_LATER(ah))
		REG_WRITE(ah, AR_DMISC(q),
			  AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1);
	else
		REG_WRITE(ah, AR_DMISC(q),
			  AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);

	if (qi->tqi_cbrPeriod) {
		REG_WRITE(ah, AR_QCBRCFG(q),
			  SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
			  SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
		REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR |
			    (qi->tqi_cbrOverflowLimit ?
			     AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
	}
	if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
		REG_WRITE(ah, AR_QRDYTIMECFG(q),
			  SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
			  AR_Q_RDYTIMECFG_EN);
	}

	REG_WRITE(ah, AR_DCHNTIME(q),
		  SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
		  (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));

	if (qi->tqi_burstTime
	    && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE))
		REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY);

	if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE)
		REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);

	REGWRITE_BUFFER_FLUSH(ah);

	if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
		REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN);

	switch (qi->tqi_type) {
	case ATH9K_TX_QUEUE_BEACON:
		ENABLE_REGWRITE_BUFFER(ah);

		REG_SET_BIT(ah, AR_QMISC(q),
			    AR_Q_MISC_FSP_DBA_GATED
			    | AR_Q_MISC_BEACON_USE
			    | AR_Q_MISC_CBR_INCR_DIS1);

		REG_SET_BIT(ah, AR_DMISC(q),
			    (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
			     AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
			    | AR_D_MISC_BEACON_USE
			    | AR_D_MISC_POST_FR_BKOFF_DIS);

		REGWRITE_BUFFER_FLUSH(ah);

		/*
		 * cwmin and cwmax should be 0 for beacon queue
		 * but not for IBSS as we would create an imbalance
		 * on beaconing fairness for participating nodes.
		 */
		if (AR_SREV_9300_20_OR_LATER(ah) &&
		    ah->opmode != NL80211_IFTYPE_ADHOC) {
			REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
				  | SM(0, AR_D_LCL_IFS_CWMAX)
				  | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
		}
		break;
	case ATH9K_TX_QUEUE_CAB:
		ENABLE_REGWRITE_BUFFER(ah);

		REG_SET_BIT(ah, AR_QMISC(q),
			    AR_Q_MISC_FSP_DBA_GATED
			    | AR_Q_MISC_CBR_INCR_DIS1
			    | AR_Q_MISC_CBR_INCR_DIS0);
		value = (qi->tqi_readyTime -
			 (ah->config.sw_beacon_response_time -
			  ah->config.dma_beacon_response_time)) * 1024;
		REG_WRITE(ah, AR_QRDYTIMECFG(q),
			  value | AR_Q_RDYTIMECFG_EN);
		REG_SET_BIT(ah, AR_DMISC(q),
			    (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
			     AR_D_MISC_ARB_LOCKOUT_CNTRL_S));

		REGWRITE_BUFFER_FLUSH(ah);

		break;
	case ATH9K_TX_QUEUE_PSPOLL:
		REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_CBR_INCR_DIS1);
		break;
	case ATH9K_TX_QUEUE_UAPSD:
		REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
		break;
	default:
		break;
	}

	if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
		REG_SET_BIT(ah, AR_DMISC(q),
			    SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
			       AR_D_MISC_ARB_LOCKOUT_CNTRL) |
			    AR_D_MISC_POST_FR_BKOFF_DIS);
	}

	if (AR_SREV_9300_20_OR_LATER(ah))
		REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);

	ath9k_hw_clear_queue_interrupts(ah, q);
	if (qi->tqi_qflags & TXQ_FLAG_TXINT_ENABLE) {
		ah->txok_interrupt_mask |= 1 << q;
		ah->txerr_interrupt_mask |= 1 << q;
	}
	if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
		ah->txdesc_interrupt_mask |= 1 << q;
	if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
		ah->txeol_interrupt_mask |= 1 << q;
	if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
		ah->txurn_interrupt_mask |= 1 << q;
	ath9k_hw_set_txq_interrupts(ah, qi);

	return true;
}
Пример #4
0
void
ar5416_ContTxMode(struct ath_hal *ah, void *ds, int mode)
{
        static int qnum =0;
        int i;
        unsigned int qbits;
#if AH_DEBUG
        struct ar5416_desc *ads = AR5416DESC(ds);
        unsigned int val, val1, val2;
#endif
        if(mode == 10) return;

    if (mode==7) {                      // print status from the cont tx desc
#if AH_DEBUG
                if (ads) {
                        val1 = ads->ds_txstatus0;
                        val2 = ads->ds_txstatus1;
                        HDPRINTF(ah, HAL_DBG_TXDESC, "s0(%x) s1(%x)\n",
                                                   (unsigned)val1, (unsigned)val2);
                }
#endif
                HDPRINTF(ah, HAL_DBG_TXDESC, "txe(%x) txd(%x)\n",
                                           OS_REG_READ(ah, AR_Q_TXE),
                                           OS_REG_READ(ah, AR_Q_TXD)
                        );
#if AH_DEBUG
                for(i=0;i<HAL_NUM_TX_QUEUES; i++) {
                        val = OS_REG_READ(ah, AR_QTXDP(i));
                        val2 = OS_REG_READ(ah, AR_QSTS(i)) & AR_Q_STS_PEND_FR_CNT;
                        HDPRINTF(ah, HAL_DBG_TXDESC, "[%d] %x %d\n", i, val, val2);
                }
#endif
                return;
    }
    if (mode==8) {                      // set TXE for qnum
                OS_REG_WRITE(ah, AR_Q_TXE, 1<<qnum);
                return;
    }
    if (mode==9) {
                return;
    }

    if (mode >= 1) {                    // initiate cont tx operation
                /* Disable AGC to A2 */
#if !_MAVERICK_STA_
		qnum = (int)ds;
#else
		/* handle the x86_64 case - we know ds is 32-bit, so cast is OK */
		qnum = (int)(uintptr_t)ds;
#endif

                OS_REG_WRITE(ah, AR_PHY_TEST,
                                         (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR) );

                OS_REG_WRITE(ah, 0x9864, OS_REG_READ(ah, 0x9864) | 0x7f000);
                OS_REG_WRITE(ah, 0x9924, OS_REG_READ(ah, 0x9924) | 0x7f00fe);
                OS_REG_WRITE(ah, AR_DIAG_SW,
                                         (OS_REG_READ(ah, AR_DIAG_SW) | (AR_DIAG_FORCE_RX_CLEAR+AR_DIAG_IGNORE_VIRT_CS)) );


                OS_REG_WRITE(ah, AR_CR, AR_CR_RXD);     // set receive disable

                if (mode == 3 || mode == 4) {
                        int txcfg;

                        if (mode == 3) {
                                OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
                                OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
                                OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 100);
                                OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 100);
                                OS_REG_WRITE(ah, AR_TIME_OUT, 2);
                                OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, 100);
                        }
                        OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
                        OS_REG_WRITE(ah, AR_D_FPCTL, 0x10|qnum);        // enable prefetch on qnum
                        txcfg = 5 | (6<<AR_FTRIG_S);
                        OS_REG_WRITE(ah, AR_TXCFG, txcfg);

                        OS_REG_WRITE(ah, AR_QMISC(qnum),        // set QCU modes
                                                 AR_Q_MISC_DCU_EARLY_TERM_REQ
                                                 +AR_Q_MISC_FSP_ASAP
                                                 +AR_Q_MISC_CBR_INCR_DIS1
                                                 +AR_Q_MISC_CBR_INCR_DIS0
                                );

                        /* stop tx dma all all except qnum */
                        qbits = 0x3ff;
                        qbits &= ~(1<<qnum);
                        for (i=0; i<10; i++) {
                                if (i==qnum) continue;
                                OS_REG_WRITE(ah, AR_Q_TXD, 1<<i);
                        }
                        OS_REG_WRITE(ah, AR_Q_TXD, qbits);

                        /* clear and freeze MIB counters */
                        OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
                        OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);

                        OS_REG_WRITE(ah, AR_DMISC(qnum),
                                                 (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
                                                 +(AR_D_MISC_ARB_LOCKOUT_IGNORE)
                                                 +(AR_D_MISC_POST_FR_BKOFF_DIS)
                                                 +(AR_D_MISC_VIR_COL_HANDLING_IGNORE << AR_D_MISC_VIR_COL_HANDLING_S)
                                );

                        for(i=0; i<HAL_NUM_TX_QUEUES+2; i++) {  // disconnect QCUs
                                if (i==qnum) continue;
                                OS_REG_WRITE(ah, AR_DQCUMASK(i), 0);
                        }
                }
    }
    if (mode == 0) {

                OS_REG_WRITE(ah, AR_PHY_TEST,
                                         (OS_REG_READ(ah, AR_PHY_TEST) & ~PHY_AGC_CLR) );
                OS_REG_WRITE(ah, AR_DIAG_SW,
                                         (OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_FORCE_RX_CLEAR+AR_DIAG_IGNORE_VIRT_CS)) );
    }
}
Пример #5
0
/*
 * Set the retry, aifs, cwmin/max, readyTime regs for specified queue
 */
HAL_BOOL
ar5211ResetTxQueue(struct ath_hal *ah, u_int q)
{
	struct ath_hal_5211 *ahp = AH5211(ah);
	const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
	HAL_TX_QUEUE_INFO *qi;
	uint32_t cwMin, chanCwMin, value;

	if (q >= HAL_NUM_TX_QUEUES) {
		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
		    __func__, q);
		return AH_FALSE;
	}
	qi = &ahp->ah_txq[q];
	if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
		HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",
		    __func__, q);
		return AH_TRUE;		/* XXX??? */
	}

	if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) {
		/*
		 * Select cwmin according to channel type.
		 * NB: chan can be NULL during attach
		 */
		if (chan && IEEE80211_IS_CHAN_B(chan))
			chanCwMin = INIT_CWMIN_11B;
		else
			chanCwMin = INIT_CWMIN;
		/* make sure that the CWmin is of the form (2^n - 1) */
		for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1)
			;
	} else
		cwMin = qi->tqi_cwmin;

	/* set cwMin/Max and AIFS values */
	OS_REG_WRITE(ah, AR_DLCL_IFS(q),
		  SM(cwMin, AR_D_LCL_IFS_CWMIN)
		| SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
		| SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));

	/* Set retry limit values */
	OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q), 
		   SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH)
		 | SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG)
		 | SM(qi->tqi_lgretry, AR_D_RETRY_LIMIT_FR_LG)
		 | SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)
	);

	/* enable early termination on the QCU */
	OS_REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);

	if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU) {
		/* Configure DCU to use the global sequence count */
		OS_REG_WRITE(ah, AR_DMISC(q), AR5311_D_MISC_SEQ_NUM_CONTROL);
	}
	/* multiqueue support */
	if (qi->tqi_cbrPeriod) {
		OS_REG_WRITE(ah, AR_QCBRCFG(q), 
			  SM(qi->tqi_cbrPeriod,AR_Q_CBRCFG_CBR_INTERVAL)
			| SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_CBR_OVF_THRESH));
		OS_REG_WRITE(ah, AR_QMISC(q),
			OS_REG_READ(ah, AR_QMISC(q)) |
			AR_Q_MISC_FSP_CBR |
			(qi->tqi_cbrOverflowLimit ?
				AR_Q_MISC_CBR_EXP_CNTR_LIMIT : 0));
	}
	if (qi->tqi_readyTime) {
		OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),
			SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_INT) | 
			AR_Q_RDYTIMECFG_EN);
	}
	if (qi->tqi_burstTime) {
		OS_REG_WRITE(ah, AR_DCHNTIME(q),
			SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
			AR_D_CHNTIME_EN);
		if (qi->tqi_qflags & HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE) {
			OS_REG_WRITE(ah, AR_QMISC(q),
			     OS_REG_READ(ah, AR_QMISC(q)) |
			     AR_Q_MISC_RDYTIME_EXP_POLICY);
		}
	}

	if (qi->tqi_qflags & HAL_TXQ_BACKOFF_DISABLE) {
		OS_REG_WRITE(ah, AR_DMISC(q),
			OS_REG_READ(ah, AR_DMISC(q)) |
			AR_D_MISC_POST_FR_BKOFF_DIS);
	}
	if (qi->tqi_qflags & HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE) {
		OS_REG_WRITE(ah, AR_DMISC(q),
			OS_REG_READ(ah, AR_DMISC(q)) |
			AR_D_MISC_FRAG_BKOFF_EN);
	}
	switch (qi->tqi_type) {
	case HAL_TX_QUEUE_BEACON:
		/* Configure QCU for beacons */
		OS_REG_WRITE(ah, AR_QMISC(q),
			OS_REG_READ(ah, AR_QMISC(q))
			| AR_Q_MISC_FSP_DBA_GATED
			| AR_Q_MISC_BEACON_USE
			| AR_Q_MISC_CBR_INCR_DIS1);
		/* Configure DCU for beacons */
		value = (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
			| AR_D_MISC_BEACON_USE | AR_D_MISC_POST_FR_BKOFF_DIS;
		if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU)
			value |= AR5311_D_MISC_SEQ_NUM_CONTROL;
		OS_REG_WRITE(ah, AR_DMISC(q), value);
		break;
	case HAL_TX_QUEUE_CAB:
		/* Configure QCU for CAB (Crap After Beacon) frames */
		OS_REG_WRITE(ah, AR_QMISC(q),
			OS_REG_READ(ah, AR_QMISC(q))
			| AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_CBR_INCR_DIS1
			| AR_Q_MISC_CBR_INCR_DIS0 | AR_Q_MISC_RDYTIME_EXP_POLICY);

		value = (ahp->ah_beaconInterval
			- (ah->ah_config.ah_sw_beacon_response_time
			        - ah->ah_config.ah_dma_beacon_response_time)
			- ah->ah_config.ah_additional_swba_backoff) * 1024;
		OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), value | AR_Q_RDYTIMECFG_EN);

		/* Configure DCU for CAB */
		value = (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << AR_D_MISC_ARB_LOCKOUT_CNTRL_S);
		if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU)
			value |= AR5311_D_MISC_SEQ_NUM_CONTROL;
		OS_REG_WRITE(ah, AR_QMISC(q), value);
		break;
	default:
		/* NB: silence compiler */
		break;
	}

	/*
	 * Always update the secondary interrupt mask registers - this
	 * could be a new queue getting enabled in a running system or
	 * hw getting re-initialized during a reset!
	 *
	 * Since we don't differentiate between tx interrupts corresponding
	 * to individual queues - secondary tx mask regs are always unmasked;
	 * tx interrupts are enabled/disabled for all queues collectively
	 * using the primary mask reg
	 */
	if (qi->tqi_qflags & HAL_TXQ_TXOKINT_ENABLE)
		ahp->ah_txOkInterruptMask |= 1 << q;
	else
		ahp->ah_txOkInterruptMask &= ~(1 << q);
	if (qi->tqi_qflags & HAL_TXQ_TXERRINT_ENABLE)
		ahp->ah_txErrInterruptMask |= 1 << q;
	else
		ahp->ah_txErrInterruptMask &= ~(1 << q);
	if (qi->tqi_qflags & HAL_TXQ_TXDESCINT_ENABLE)
		ahp->ah_txDescInterruptMask |= 1 << q;
	else
		ahp->ah_txDescInterruptMask &= ~(1 << q);
	if (qi->tqi_qflags & HAL_TXQ_TXEOLINT_ENABLE)
		ahp->ah_txEolInterruptMask |= 1 << q;
	else
		ahp->ah_txEolInterruptMask &= ~(1 << q);
	if (qi->tqi_qflags & HAL_TXQ_TXURNINT_ENABLE)
		ahp->ah_txUrnInterruptMask |= 1 << q;
	else
		ahp->ah_txUrnInterruptMask &= ~(1 << q);
	setTxQInterrupts(ah, qi);

	return AH_TRUE;
}
Пример #6
0
void
ar9300DumpRegs(FILE *fd, int what)
{
#define N(a)    (sizeof(a) / sizeof(a[0]))
    static const HAL_REG regs[] = {
        /* NB: keep these sorted by address */
        { "CR",     AR_CR },
        { "HPRXDP", AR_HP_RXDP },
        { "LPRXDP", AR_LP_RXDP },
        { "CFG",    AR_CFG },
        { "IER",    AR_IER },
        { "TXCFG",  AR_TXCFG },
        { "RXCFG",  AR_RXCFG },
        { "MIBC",   AR_MIBC },
        { "TOPS",   AR_TOPS },
        { "RXNPTO", AR_RXNPTO },
        { "TXNPTO", AR_TXNPTO },
        { "RPGTO",  AR_RPGTO },
        { "MACMISC", AR_MACMISC },
        { "D_SIFS", AR_D_GBL_IFS_SIFS },
        { "D_SEQNUM", AR_D_SEQNUM },
        { "D_SLOT", AR_D_GBL_IFS_SLOT },
        { "D_EIFS", AR_D_GBL_IFS_EIFS },
        { "D_MISC", AR_D_GBL_IFS_MISC },
        { "D_TXPSE", AR_D_TXPSE },
        { "RC",     AR9300_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL) },
//      { "SCR",    AR_SCR },
//      { "INTPEND",    AR_INTPEND },
//      { "SFR",    AR_SFR },
//      { "PCICFG", AR_PCICFG },
//      { "GPIOCR", AR_GPIOCR },
        { "SREV",   AR9300_HOSTIF_OFFSET(HOST_INTF_SREV) },
        { "STA_ID0",    AR_STA_ID0 },
        { "STA_ID1",    AR_STA_ID1 },
        { "BSS_ID0",    AR_BSS_ID0 },
        { "BSS_ID1",    AR_BSS_ID1 },
        { "TIME_OUT",   AR_TIME_OUT },
        { "RSSI_THR",   AR_RSSI_THR },
        { "USEC",   AR_USEC },
//      { "BEACON", AR_BEACON },
//      { "CFP_PER",    AR_CFP_PERIOD },
//      { "TIMER0", AR_TIMER0 },
//      { "TIMER1", AR_TIMER1 },
//      { "TIMER2", AR_TIMER2 },
//      { "TIMER3", AR_TIMER3 },
//      { "CFP_DUR",    AR_CFP_DUR },
        { "RX_FILTR",   AR_RX_FILTER },
        { "MCAST_0",    AR_MCAST_FIL0 },
        { "MCAST_1",    AR_MCAST_FIL1 },
        { "DIAG_SW",    AR_DIAG_SW },
        { "TSF_L32",    AR_TSF_L32 },
        { "TSF_U32",    AR_TSF_U32 },
        { "TST_ADAC",   AR_TST_ADDAC },
        { "DEF_ANT",    AR_DEF_ANTENNA },
        { "LAST_TST",   AR_LAST_TSTP },
        { "NAV",    AR_NAV },
        { "RTS_OK",     AR_RTS_OK },
        { "RTS_FAIL",   AR_RTS_FAIL },
        { "ACK_FAIL",   AR_ACK_FAIL },
        { "FCS_FAIL",   AR_FCS_FAIL },
        { "BEAC_CNT",   AR_BEACON_CNT },
#ifdef AH_SUPPORT_XR
        { "XRMODE", AR_XRMODE },
        { "XRDEL",  AR_XRDEL },
        { "XRTO",   AR_XRTO },
        { "XRCRP",  AR_XRCRP },
        { "XRSTMP", AR_XRSTMP },
#endif /* AH_SUPPORT_XR */
        { "SLEEP1", AR_SLEEP1 },
        { "SLEEP2", AR_SLEEP2 },
//      { "SLEEP3", AR_SLEEP3 },
        { "BSSMSKL",    AR_BSSMSKL },
        { "BSSMSKU",    AR_BSSMSKU },
        { "TPC",    AR_TPC },
        { "TFCNT",  AR_TFCNT },
        { "RFCNT",  AR_RFCNT },
        { "RCCNT",  AR_RCCNT },
        { "CCCNT",  AR_CCCNT },
//      { "NOACK",  AR_NOACK },
        { "PHY_ERR",    AR_PHY_ERR },
//      { "QOSCTL", AR_QOS_CONTROL },
//      { "QOSSEL", AR_QOS_SELECT },
//      { "MISCMODE",   AR_MISC_MODE },
//      { "FILTOFDM",   AR_FILTOFDM },
//      { "FILTCCK",    AR_FILTCCK },
//      { "PHYCNT1",    AR_PHYCNT1 },
//      { "PHYCMSK1",   AR_PHYCNTMASK1 },
//      { "PHYCNT2",    AR_PHYCNT2 },
//      { "PHYCMSK2",   AR_PHYCNTMASK2 },
    };
    int i;
    u_int32_t v;

    if (what & DUMP_BASIC) {
        ath_hal_dumpregs(fd, regs, N(regs));
    }
    if (what & DUMP_INTERRUPT) {
        /* Interrupt registers */
        if (what & DUMP_BASIC)
            fprintf(fd, "\n");
        fprintf(fd, "IMR: %08x S0 %08x S1 %08x S2 %08x S3 %08x S4 %08x\n"
            , OS_REG_READ(ah, AR_IMR)
            , OS_REG_READ(ah, AR_IMR_S0)
            , OS_REG_READ(ah, AR_IMR_S1)
            , OS_REG_READ(ah, AR_IMR_S2)
            , OS_REG_READ(ah, AR_IMR_S3)
            , OS_REG_READ(ah, AR_IMR_S4)
        );
        fprintf(fd, "ISR: %08x S0 %08x S1 %08x S2 %08x S3 %08x S4 %08x\n"
            , OS_REG_READ(ah, AR_ISR)
            , OS_REG_READ(ah, AR_ISR_S0)
            , OS_REG_READ(ah, AR_ISR_S1)
            , OS_REG_READ(ah, AR_ISR_S2)
            , OS_REG_READ(ah, AR_ISR_S3)
            , OS_REG_READ(ah, AR_ISR_S4)
        );
    }
    if (what & DUMP_QCU) {
        /* QCU registers */
        if (what & (DUMP_BASIC|DUMP_INTERRUPT))
            fprintf(fd, "\n");
        fprintf(fd, "%-8s %08x  %-8s %08x  %-8s %08x\n"
            , "Q_TXE", OS_REG_READ(ah, AR_Q_TXE)
            , "Q_TXD", OS_REG_READ(ah, AR_Q_TXD)
            , "Q_RDYTIMSHD", OS_REG_READ(ah, AR_Q_RDYTIMESHDN)
        );
        fprintf(fd, "Q_ONESHOTARM_SC %08x  Q_ONESHOTARM_CC %08x\n"
            , OS_REG_READ(ah, AR_Q_ONESHOTARM_SC)
            , OS_REG_READ(ah, AR_Q_ONESHOTARM_CC)
        );
        for (i = 0; i < 10; i++)
            fprintf(fd, "Q[%u] TXDP %08x CBR %08x RDYT %08x MISC %08x STS %08x\n"
                , i
                , OS_REG_READ(ah, AR_QTXDP(i))
                , OS_REG_READ(ah, AR_QCBRCFG(i))
                , OS_REG_READ(ah, AR_QRDYTIMECFG(i))
                , OS_REG_READ(ah, AR_QMISC(i))
                , OS_REG_READ(ah, AR_QSTS(i))
            );
    }
    if (what & DUMP_DCU) {
        /* DCU registers */
        if (what & (DUMP_BASIC|DUMP_INTERRUPT|DUMP_QCU))
            fprintf(fd, "\n");
        for (i = 0; i < 10; i++)
            fprintf(fd, "D[%u] MASK %08x IFS %08x RTRY %08x CHNT %08x MISC %06x\n"
                , i
                , OS_REG_READ(ah, AR_DQCUMASK(i))
                , OS_REG_READ(ah, AR_DLCL_IFS(i))
                , OS_REG_READ(ah, AR_DRETRY_LIMIT(i))
                , OS_REG_READ(ah, AR_DCHNTIME(i))
                , OS_REG_READ(ah, AR_DMISC(i))
            );
    }
    for (i = 0; i < 10; i++) {
        u_int32_t f0 = OS_REG_READ(ah, AR_D_TXBLK_DATA((i<<8)|0x00));
        u_int32_t f1 = OS_REG_READ(ah, AR_D_TXBLK_DATA((i<<8)|0x40));
        u_int32_t f2 = OS_REG_READ(ah, AR_D_TXBLK_DATA((i<<8)|0x80));
        u_int32_t f3 = OS_REG_READ(ah, AR_D_TXBLK_DATA((i<<8)|0xc0));
        if (f0 || f1 || f2 || f3)
            fprintf(fd,
                "D[%u] XMIT MASK %08x %08x %08x %08x\n",
                i, f0, f1, f2, f3);
    }
    if (what & DUMP_KEYCACHE)
        ath_hal_dumpkeycache(fd, 128,
            OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_CRPT_MIC_ENABLE);

    if (what & DUMP_BASEBAND) {
        int reg;
        if (what &~ DUMP_BASEBAND)
            fprintf(fd, "\n");

        for (reg = 0x9800; reg <= 0xa480; reg += 4) {
            printf("%X %.8X\n", reg, OS_REG_READ(ah, reg));
        }
#if 0
        ath_hal_dumprange(fd, 0x9800, 0x987c);
        ath_hal_dumprange(fd, 0x9900, 0x995c);
        ath_hal_dumprange(fd, 0x9c00, 0x9c1c);
        ath_hal_dumprange(fd, 0xa180, 0xa238);
#endif
    }

    if (what & DUMP_LA) {
        int reg;
        for (reg = AR_MAC_PCU_TRACE_REG_START, i = 0; reg < AR_MAC_PCU_TRACE_REG_END; reg += 16) {
            printf("0x%X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, 
                   OS_REG_READ(ah, reg + 0),
                   OS_REG_READ(ah, reg + 4),
                   OS_REG_READ(ah, reg + 8),
                   OS_REG_READ(ah, reg + 12));
        }
    }
    if (what & DUMP_DMADBG) {
        int reg;
        for (reg = AR_DMADBG_0, i = 0; reg <= AR_DMADBG_7; reg += 4) {
            printf("0x%X: 0x%.8X\n", reg, OS_REG_READ(ah, reg));
        }
    }
#undef N
}
Пример #7
0
//#define AR9300_EMULATION 1
#include "ar9300/ar9300reg.h"

static const HAL_REGRANGE ar9300PublicRegs[] = {
    /* NB: keep these sorted by address */
    { AR_CR, AR_IER },
    { AR_TXCFG, AR_RXCFG },
    { AR_MIBC, AR_MACMISC },
    { AR_Q0_TXDP, AR_QTXDP(9) },
    { AR_Q_TXE },
    { AR_Q_TXD },
    { AR_Q0_CBRCFG, AR_QCBRCFG(9) },
    { AR_Q0_RDYTIMECFG, AR_QRDYTIMECFG(9) },
    { AR_Q_ONESHOTARM_SC },
    { AR_Q_ONESHOTARM_CC },
    { AR_Q0_MISC, AR_QMISC(9) },
    { AR_Q0_STS, AR_QSTS(9) },
    { AR_Q_RDYTIMESHDN },
    { AR_D0_QCUMASK, AR_DQCUMASK(9) },
    { AR_D0_LCL_IFS, AR_DLCL_IFS(9) },
    { AR_D0_RETRY_LIMIT, AR_DRETRY_LIMIT(9) },
    { AR_D0_CHNTIME, AR_DCHNTIME(9) },
    { AR_D0_MISC, AR_DMISC(9) },
    { AR_D_SEQNUM },
    { AR_D_GBL_IFS_SIFS },
    { AR_D_GBL_IFS_SLOT },
    { AR_D_GBL_IFS_EIFS },
    { AR_D_GBL_IFS_MISC },
    { AR_D_TXPSE },
#ifdef notdef
    { AR_D_TXBLK_DATA(0),  /* XXX?? */ },