static int aic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, const u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_type) { struct irq_domain_chip_generic *dgc = d->gc; struct irq_chip_generic *gc; unsigned smr; int idx; int ret; if (!dgc) return -EINVAL; ret = aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize, out_hwirq, out_type); if (ret) return ret; idx = intspec[0] / dgc->irqs_per_chip; if (idx >= dgc->num_chips) return -EINVAL; gc = dgc->gc[idx]; irq_gc_lock(gc); smr = irq_reg_readl(gc, AT91_AIC_SMR(*out_hwirq)); ret = aic_common_set_priority(intspec[2], &smr); if (!ret) irq_reg_writel(gc, smr, AT91_AIC_SMR(*out_hwirq)); irq_gc_unlock(gc); return ret; }
static int at91_aic_set_type(struct irq_data *d, unsigned type) { unsigned int smr, srctype; switch (type) { case IRQ_TYPE_LEVEL_HIGH: srctype = AT91_AIC_SRCTYPE_HIGH; break; case IRQ_TYPE_EDGE_RISING: srctype = AT91_AIC_SRCTYPE_RISING; break; case IRQ_TYPE_LEVEL_LOW: if ((d->irq == AT91_ID_FIQ) || is_extern_irq(d->irq)) /* only supported on external interrupts */ srctype = AT91_AIC_SRCTYPE_LOW; else return -EINVAL; break; case IRQ_TYPE_EDGE_FALLING: if ((d->irq == AT91_ID_FIQ) || is_extern_irq(d->irq)) /* only supported on external interrupts */ srctype = AT91_AIC_SRCTYPE_FALLING; else return -EINVAL; break; default: return -EINVAL; } smr = at91_sys_read(AT91_AIC_SMR(d->irq)) & ~AT91_AIC_SRCTYPE; at91_sys_write(AT91_AIC_SMR(d->irq), smr | srctype); return 0; }
static int aic_set_type(struct irq_data *d, unsigned type) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); unsigned int smr; int ret; smr = irq_reg_readl(gc, AT91_AIC_SMR(d->hwirq)); ret = aic_common_set_type(d, type, &smr); if (ret) return ret; irq_reg_writel(gc, smr, AT91_AIC_SMR(d->hwirq)); return 0; }
/* * Initialize the AIC interrupt controller. */ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS]) { unsigned int i; /* * The IVR is used by macro get_irqnr_and_base to read and verify. * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred. */ for (i = 0; i < NR_AIC_IRQS; i++) { /* Put irq number in Source Vector Register: */ at91_sys_write(AT91_AIC_SVR(i), i); /* Active Low interrupt, with the specified priority */ at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */ if (i < 8) at91_sys_write(AT91_AIC_EOICR, 0); } /* * Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS * When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU */ at91_sys_write(AT91_AIC_SPU, NR_AIC_IRQS); /* No debugging in AIC: Debug (Protect) Control Register */ at91_sys_write(AT91_AIC_DCR, 0); /* Disable and clear all interrupts initially */ at91_sys_write(AT91_AIC_IDCR, 0xFFFFFFFF); at91_sys_write(AT91_AIC_ICCR, 0xFFFFFFFF); }
/* * Initialize the AIC interrupt controller. */ void at91_aic_init(rt_uint32_t *priority) { rt_uint32_t i; /* * The IVR is used by macro get_irqnr_and_base to read and verify. * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred. */ for (i = 0; i < AIC_IRQS; i++) { /* Put irq number in Source Vector Register: */ at91_sys_write(AT91_AIC_SVR(i), i); /* Active Low interrupt, with the specified priority */ at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); //AT91_AIC_SRCTYPE_FALLING /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */ if (i < 8) at91_sys_write(AT91_AIC_EOICR, 0); } /* * Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS * When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU */ at91_sys_write(AT91_AIC_SPU, AIC_IRQS); /* No debugging in AIC: Debug (Protect) Control Register */ at91_sys_write(AT91_AIC_DCR, 0); /* Disable and clear all interrupts initially */ at91_sys_write(AT91_AIC_IDCR, 0xFFFFFFFF); at91_sys_write(AT91_AIC_ICCR, 0xFFFFFFFF); }
static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq, irq_hw_number_t hw) { /* Put virq number in Source Vector Register */ at91_aic_write(AT91_AIC_SVR(hw), virq); /* Active Low interrupt, without priority */ at91_aic_write(AT91_AIC_SMR(hw), AT91_AIC_SRCTYPE_LOW); irq_set_chip_and_handler(virq, &at91_aic_chip, handle_level_irq); set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); return 0; }
/* * Initialize the AIC interrupt controller. */ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS]) { unsigned int i; int irq_base; at91_aic_base = ioremap(AT91_AIC, 512); if (!at91_aic_base) panic("Unable to ioremap AIC registers\n"); /* Add irq domain for AIC */ irq_base = irq_alloc_descs(-1, 0, NR_AIC_IRQS, 0); if (irq_base < 0) { WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n"); irq_base = 0; } at91_aic_domain = irq_domain_add_legacy(at91_aic_np, NR_AIC_IRQS, irq_base, 0, &irq_domain_simple_ops, NULL); if (!at91_aic_domain) panic("Unable to add AIC irq domain\n"); irq_set_default_host(at91_aic_domain); /* * The IVR is used by macro get_irqnr_and_base to read and verify. * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred. */ for (i = 0; i < NR_AIC_IRQS; i++) { /* Put hardware irq number in Source Vector Register: */ at91_aic_write(AT91_AIC_SVR(i), i); /* Active Low interrupt, with the specified priority */ at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } at91_aic_hw_init(NR_AIC_IRQS); }