void at91_pmc_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
u32 tmp;
/*
* while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
* so we need to slow down and configure MCKR accordingly.
* This is why we have a special flavor of the switching function.
*/
tmp = AT91_PMC_MCKR_PLLADIV_2 | \
AT91_PMC_MCKR_MDIV_3 | \
AT91_PMC_MCKR_CSS_MAIN;
at91_mck_init_down(tmp);
tmp = AT91_PMC_PLLAR_29 |
AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
AT91_PMC_PLLXR_MUL(82) |
AT91_PMC_PLLXR_DIV(1);
at91_plla_init(tmp);
writel(0x0 << 8, &pmc->pllicpr);
tmp = AT91_PMC_MCKR_H32MXDIV |
AT91_PMC_MCKR_PLLADIV_2 |
AT91_PMC_MCKR_MDIV_3 |
AT91_PMC_MCKR_CSS_PLLA;
at91_mck_init(tmp);
}
void at91_pmc_init(void)
{
u32 tmp;
tmp = AT91_PMC_PLLAR_29 |
AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
AT91_PMC_PLLXR_MUL(43) |
AT91_PMC_PLLXR_DIV(1);
at91_plla_init(tmp);
at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
tmp = AT91_PMC_MCKR_MDIV_4 |
AT91_PMC_MCKR_CSS_PLLA;
at91_mck_init(tmp);
}
void at91_pmc_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
u32 tmp;
tmp = AT91_PMC_PLLAR_29 |
AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
AT91_PMC_PLLXR_MUL(43) |
AT91_PMC_PLLXR_DIV(1);
at91_plla_init(tmp);
writel(0x3 << 8, &pmc->pllicpr);
tmp = AT91_PMC_MCKR_MDIV_4 |
AT91_PMC_MCKR_CSS_PLLA;
at91_mck_init(tmp);
}
void at91_pmc_init(void)
{
u32 tmp;
tmp = AT91_PMC_PLLAR_29 |
AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
AT91_PMC_PLLXR_MUL(87) |
AT91_PMC_PLLXR_DIV(1);
at91_plla_init(tmp);
at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
tmp = AT91_PMC_MCKR_H32MXDIV |
AT91_PMC_MCKR_PLLADIV_2 |
AT91_PMC_MCKR_MDIV_3 |
AT91_PMC_MCKR_CSS_PLLA;
at91_mck_init(tmp);
}
