void imx_irq_set_priority(unsigned char irq, unsigned char prio) { unsigned int temp; unsigned int mask = 0x0F << irq % 8 * 4; if (irq > 63) return; temp = __raw_readl(AVIC_NIPRIORITY(irq / 8)); temp &= ~mask; temp |= prio & mask; __raw_writel(temp, AVIC_NIPRIORITY(irq / 8)); }
static int avic_irq_set_priority(unsigned char irq, unsigned char prio) { unsigned int temp; unsigned int mask = 0x0F << irq % 8 * 4; if (irq >= MXC_INTERNAL_IRQS) return -EINVAL;; temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8)); temp &= ~mask; temp |= prio & mask; __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8)); return 0; }
int imx_irq_set_priority(unsigned char irq, unsigned char prio) { #ifdef CONFIG_MXC_IRQ_PRIOR unsigned int temp; unsigned int mask = 0x0F << irq % 8 * 4; if (irq >= MXC_INTERNAL_IRQS) return -EINVAL;; temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8)); temp &= ~mask; temp |= prio & mask; __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8)); return 0; #else return -ENOSYS; #endif }
/* * This function initializes the AVIC hardware and disables all the * interrupts. It registers the interrupt enable and disable functions * to the kernel for each interrupt source. */ void __init mxc_init_irq(void) { int i; avic_base = IO_ADDRESS(AVIC_BASE_ADDR); /* put the AVIC into the reset value with * all interrupts disabled */ __raw_writel(0, avic_base + AVIC_INTCNTL); __raw_writel(0x1f, avic_base + AVIC_NIMASK); /* disable all interrupts */ __raw_writel(0, avic_base + AVIC_INTENABLEH); __raw_writel(0, avic_base + AVIC_INTENABLEL); /* all IRQ no FIQ */ __raw_writel(0, avic_base + AVIC_INTTYPEH); __raw_writel(0, avic_base + AVIC_INTTYPEL); for (i = 0; i < MXC_INTERNAL_IRQS; i++) { set_irq_chip(i, &mxc_avic_chip); set_irq_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID); } /* Set default priority value (0) for all IRQ's */ for (i = 0; i < 8; i++) __raw_writel(0, avic_base + AVIC_NIPRIORITY(i)); #ifdef CONFIG_FIQ /* Initialize FIQ */ init_FIQ(); #endif if (MXC_INT_FORCE >= 32) __raw_writel(1 << (MXC_INT_FORCE & 31), avic_base + AVIC_INTFRCH); else if (MXC_INT_FORCE >= 0) __raw_writel(1 << MXC_INT_FORCE, avic_base + AVIC_INTFRCL); printk(KERN_INFO "MXC IRQ initialized\n"); }
/* * This function initializes the AVIC hardware and disables all the * interrupts. It registers the interrupt enable and disable functions * to the kernel for each interrupt source. */ void __init mxc_init_irq(void __iomem *irqbase) { int i; avic_base = irqbase; /* put the AVIC into the reset value with * all interrupts disabled */ __raw_writel(0, avic_base + AVIC_INTCNTL); __raw_writel(0x1f, avic_base + AVIC_NIMASK); /* disable all interrupts */ __raw_writel(0, avic_base + AVIC_INTENABLEH); __raw_writel(0, avic_base + AVIC_INTENABLEL); /* all IRQ no FIQ */ __raw_writel(0, avic_base + AVIC_INTTYPEH); __raw_writel(0, avic_base + AVIC_INTTYPEL); for (i = 0; i < MXC_INTERNAL_IRQS; i++) { set_irq_chip(i, &mxc_avic_chip); set_irq_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID); } /* Set default priority value (0) for all IRQ's */ for (i = 0; i < 8; i++) __raw_writel(0, avic_base + AVIC_NIPRIORITY(i)); /* init architectures chained interrupt handler */ mxc_register_gpios(); #ifdef CONFIG_FIQ /* Initialize FIQ */ init_FIQ(); #endif printk(KERN_INFO "MXC IRQ initialized\n"); }