ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Converts MiniAIG into GIA.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Gia_ObjFromMiniFanin0Copy( Gia_Man_t * pGia, Vec_Int_t * vCopies, Mini_Aig_t * p, int Id )
{
int Lit = Mini_AigNodeFanin0( p, Id );
return Abc_LitNotCond( Vec_IntEntry(vCopies, Abc_Lit2Var(Lit)), Abc_LitIsCompl(Lit) );
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Converts the network from the AIG manager into ABC.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Obj_t * Abc_NodeFanin0Copy( Abc_Ntk_t * pNtk, Vec_Int_t * vCopies, Mini_Aig_t * p, int Id )
{
int Lit = Mini_AigNodeFanin0( p, Id );
int AbcLit = Abc_LitNotCond( Vec_IntEntry(vCopies, Abc_Lit2Var(Lit)), Abc_LitIsCompl(Lit) );
return Abc_ObjFromLit( pNtk, AbcLit );
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
static inline int Gia_ObjChild0Copy( Aig_Obj_t * pObj ) { return Abc_LitNotCond( Aig_ObjFanin0(pObj)->iData, Aig_ObjFaninC0(pObj) ); }
static inline int Mpm_CutDup( Mpm_Man_t * p, Mpm_Cut_t * pCut, int fCompl )
{
Mpm_Cut_t * pCutNew;
int hCutNew = Mpm_CutAlloc( p, pCut->nLeaves, &pCutNew );
pCutNew->iFunc = Abc_LitNotCond( pCut->iFunc, fCompl );
pCutNew->fUseless = pCut->fUseless;
pCutNew->nLeaves = pCut->nLeaves;
memcpy( pCutNew->pLeaves, pCut->pLeaves, sizeof(int) * pCut->nLeaves );
return hCutNew;
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Transforms the decomposition graph into the AIG.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Kit_GraphToGiaInternal( Gia_Man_t * pMan, Kit_Graph_t * pGraph, int fHash )
{
Kit_Node_t * pNode = NULL;
int i, pAnd0, pAnd1;
// check for constant function
if ( Kit_GraphIsConst(pGraph) )
return Abc_LitNotCond( 1, Kit_GraphIsComplement(pGraph) );
// check for a literal
if ( Kit_GraphIsVar(pGraph) )
return Abc_LitNotCond( Kit_GraphVar(pGraph)->iFunc, Kit_GraphIsComplement(pGraph) );
// build the AIG nodes corresponding to the AND gates of the graph
Kit_GraphForEachNode( pGraph, pNode, i )
{
pAnd0 = Abc_LitNotCond( Kit_GraphNode(pGraph, pNode->eEdge0.Node)->iFunc, pNode->eEdge0.fCompl );
pAnd1 = Abc_LitNotCond( Kit_GraphNode(pGraph, pNode->eEdge1.Node)->iFunc, pNode->eEdge1.fCompl );
if ( fHash )
pNode->iFunc = Gia_ManHashAnd( pMan, pAnd0, pAnd1 );
else
pNode->iFunc = Gia_ManAppendAnd( pMan, pAnd0, pAnd1 );
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Create GIA for SOP.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Gia_ManGraphToAig( Gia_Man_t * p, Dec_Graph_t * pGraph )
{
Dec_Node_t * pNode = NULL; // Suppress "might be used uninitialized"
int i, iAnd0, iAnd1;
// check for constant function
if ( Dec_GraphIsConst(pGraph) )
return Abc_LitNotCond( 1, Dec_GraphIsComplement(pGraph) );
// check for a literal
if ( Dec_GraphIsVar(pGraph) )
return Abc_LitNotCond( Dec_GraphVar(pGraph)->iFunc, Dec_GraphIsComplement(pGraph) );
// build the AIG nodes corresponding to the AND gates of the graph
Dec_GraphForEachNode( pGraph, pNode, i )
{
iAnd0 = Abc_LitNotCond( Dec_GraphNode(pGraph, pNode->eEdge0.Node)->iFunc, pNode->eEdge0.fCompl );
iAnd1 = Abc_LitNotCond( Dec_GraphNode(pGraph, pNode->eEdge1.Node)->iFunc, pNode->eEdge1.fCompl );
pNode->iFunc = Gia_ManHashAnd( p, iAnd0, iAnd1 );
}
/**Function*************************************************************
Synopsis [Interface with the FPGA mapping package.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void If_ManComputeSwitching( If_Man_t * pIfMan )
{
abctime clk = Abc_Clock();
Gia_Man_t * pNew;
Vec_Int_t * vCopy;
If_Obj_t * pIfObj;
int i;
assert( pIfMan->vSwitching == NULL );
// create the new manager
pNew = Gia_ManStart( If_ManObjNum(pIfMan) );
vCopy = Vec_IntAlloc( If_ManObjNum(pIfMan) );
// constant and inputs
Vec_IntPush( vCopy, 1 );
If_ManForEachCi( pIfMan, pIfObj, i )
Vec_IntPush( vCopy, Gia_ManAppendCi(pNew) );
// internal nodes
If_ManForEachNode( pIfMan, pIfObj, i )
{
int iLit0 = Abc_LitNotCond( Vec_IntEntry(vCopy, If_ObjFanin0(pIfObj)->Id), If_ObjFaninC0(pIfObj) );
int iLit1 = Abc_LitNotCond( Vec_IntEntry(vCopy, If_ObjFanin1(pIfObj)->Id), If_ObjFaninC1(pIfObj) );
Vec_IntPush( vCopy, Gia_ManAppendAnd(pNew, iLit0, iLit1) );
}
/**Function*************************************************************
Synopsis [Remaps the AIG from the old manager into the new manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Gia_ManCleanupRemap( Gia_Man_t * p, Gia_Man_t * pGia )
{
Gia_Obj_t * pObj, * pObjGia;
int i, iPrev;
Gia_ManForEachObj1( p, pObj, i )
{
iPrev = Gia_ObjValue(pObj);
if ( iPrev == ~0 )
continue;
pObjGia = Gia_ManObj( pGia, Abc_Lit2Var(iPrev) );
if ( pObjGia->Value == ~0 )
Gia_ObjSetValue( pObj, pObjGia->Value );
else
Gia_ObjSetValue( pObj, Abc_LitNotCond(pObjGia->Value, Abc_LitIsCompl(iPrev)) );
}
/**Function*************************************************************
Synopsis [Derives GIA for the truth table.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Dau_DsdToGiaCompose_rec( Gia_Man_t * pGia, word Func, int * pFanins, int nVars )
{
int t0, t1;
if ( Func == 0 )
return 0;
if ( Func == ~(word)0 )
return 1;
assert( nVars > 0 );
if ( --nVars == 0 )
{
assert( Func == s_Truths6[0] || Func == s_Truths6Neg[0] );
return Abc_LitNotCond( pFanins[0], (int)(Func == s_Truths6Neg[0]) );
}
if ( !Abc_Tt6HasVar(Func, nVars) )
return Dau_DsdToGiaCompose_rec( pGia, Func, pFanins, nVars );
t0 = Dau_DsdToGiaCompose_rec( pGia, Abc_Tt6Cofactor0(Func, nVars), pFanins, nVars );
t1 = Dau_DsdToGiaCompose_rec( pGia, Abc_Tt6Cofactor1(Func, nVars), pFanins, nVars );
if ( pGia->pMuxes )
return Gia_ManHashMuxReal( pGia, pFanins[nVars], t1, t0 );
else
return Gia_ManHashMux( pGia, pFanins[nVars], t1, t0 );
}
/**Function*************************************************************
Synopsis [Computes CE-induced network.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Gia_Man_t * Bmc_CexBuildNetwork2( Gia_Man_t * p, Abc_Cex_t * pCex, int fStart )
{
Gia_Man_t * pNew, * pTemp;
Gia_Obj_t * pObj, * pObjRo, * pObjRi;
int fCompl0, fCompl1;
int i, k, iBit;
assert( pCex->nRegs == 0 );
assert( pCex->nPis == Gia_ManCiNum(p) );
assert( fStart <= pCex->iFrame );
// start the manager
pNew = Gia_ManStart( 1000 );
pNew->pName = Abc_UtilStrsav( "unate" );
// set const0
Gia_ManConst0(p)->fMark0 = 0; // value
Gia_ManConst0(p)->fMark1 = 1; // care
Gia_ManConst0(p)->Value = ~0;
// set init state
Gia_ManForEachRi( p, pObj, k )
{
pObj->fMark0 = Abc_InfoHasBit( pCex->pData, pCex->nRegs + fStart * Gia_ManCiNum(p) + Gia_ManPiNum(p) + k );
pObj->fMark1 = 0;
pObj->Value = Abc_LitNotCond( Gia_ManAppendCi(pNew), !pObj->fMark0 );
}
int Abc_NtkTestTimNodeStrash( Gia_Man_t * pGia, Abc_Obj_t * pNode )
{
Hop_Man_t * pMan;
Hop_Obj_t * pRoot;
Abc_Obj_t * pFanin;
int i;
assert( Abc_ObjIsNode(pNode) );
assert( Abc_NtkIsAigLogic(pNode->pNtk) );
// get the local AIG manager and the local root node
pMan = (Hop_Man_t *)pNode->pNtk->pManFunc;
pRoot = (Hop_Obj_t *)pNode->pData;
// check the constant case
if ( Abc_NodeIsConst(pNode) || Hop_Regular(pRoot) == Hop_ManConst1(pMan) )
return !Hop_IsComplement(pRoot);
// set elementary variables
Abc_ObjForEachFanin( pNode, pFanin, i )
Hop_IthVar(pMan, i)->iData = pFanin->iTemp;
// strash the AIG of this node
Abc_NtkTestTimNodeStrash_rec( pGia, Hop_Regular(pRoot) );
Hop_ConeUnmark_rec( Hop_Regular(pRoot) );
// return the final node with complement if needed
return Abc_LitNotCond( Hop_Regular(pRoot)->iData, Hop_IsComplement(pRoot) );
}
int Dau_DsdToGia_rec( Gia_Man_t * pGia, char * pStr, char ** p, int * pMatches, int * pLits, Vec_Int_t * vCover )
{
int fCompl = 0;
if ( **p == '!' )
(*p)++, fCompl = 1;
if ( **p >= 'a' && **p < 'a' + DAU_DSD_MAX_VAR ) // var
return Abc_LitNotCond( pLits[**p - 'a'], fCompl );
if ( **p == '(' ) // and/or
{
char * q = pStr + pMatches[ *p - pStr ];
int pFans[DAU_DSD_MAX_VAR], nFans = 0, Fan;
assert( **p == '(' && *q == ')' );
for ( (*p)++; *p < q; (*p)++ )
{
Fan = Dau_DsdToGia_rec( pGia, pStr, p, pMatches, pLits, vCover );
Dau_DsdAddToArray( pGia, pFans, nFans++, Fan );
}
Fan = Dau_DsdBalance( pGia, pFans, nFans, 1 );
assert( *p == q );
return Abc_LitNotCond( Fan, fCompl );
}
if ( **p == '[' ) // xor
{
char * q = pStr + pMatches[ *p - pStr ];
int pFans[DAU_DSD_MAX_VAR], nFans = 0, Fan;
assert( **p == '[' && *q == ']' );
for ( (*p)++; *p < q; (*p)++ )
{
Fan = Dau_DsdToGia_rec( pGia, pStr, p, pMatches, pLits, vCover );
Dau_DsdAddToArray( pGia, pFans, nFans++, Fan );
}
Fan = Dau_DsdBalance( pGia, pFans, nFans, 0 );
assert( *p == q );
return Abc_LitNotCond( Fan, fCompl );
}
if ( **p == '<' ) // mux
{
Gia_Obj_t * pObj;
int nVars = 0;
int Temp[3], * pTemp = Temp, Res;
int Fanins[DAU_DSD_MAX_VAR], * pLits2;
char * pOld = *p;
char * q = pStr + pMatches[ *p - pStr ];
// read fanins
if ( *(q+1) == '{' )
{
char * q2;
*p = q+1;
q2 = pStr + pMatches[ *p - pStr ];
assert( **p == '{' && *q2 == '}' );
for ( nVars = 0, (*p)++; *p < q2; (*p)++, nVars++ )
Fanins[nVars] = Dau_DsdToGia_rec( pGia, pStr, p, pMatches, pLits, vCover );
assert( *p == q2 );
pLits2 = Fanins;
}
else
pLits2 = pLits;
// read MUX
*p = pOld;
q = pStr + pMatches[ *p - pStr ];
assert( **p == '<' && *q == '>' );
// verify internal variables
if ( nVars )
for ( ; pOld < q; pOld++ )
if ( *pOld >= 'a' && *pOld <= 'z' )
assert( *pOld - 'a' < nVars );
// derive MUX components
for ( (*p)++; *p < q; (*p)++ )
*pTemp++ = Dau_DsdToGia_rec( pGia, pStr, p, pMatches, pLits2, vCover );
assert( pTemp == Temp + 3 );
assert( *p == q );
if ( *(q+1) == '{' ) // and/or
{
char * q = pStr + pMatches[ ++(*p) - pStr ];
assert( **p == '{' && *q == '}' );
*p = q;
}
if ( pGia->pMuxes )
Res = Gia_ManHashMuxReal( pGia, Temp[0], Temp[1], Temp[2] );
else
Res = Gia_ManHashMux( pGia, Temp[0], Temp[1], Temp[2] );
pObj = Gia_ManObj(pGia, Abc_Lit2Var(Res));
if ( Gia_ObjIsAnd(pObj) )
{
if ( pGia->pMuxes )
Gia_ObjSetMuxLevel( pGia, pObj );
else
{
if ( Gia_ObjIsAnd(Gia_ObjFanin0(pObj)) )
Gia_ObjSetAndLevel( pGia, Gia_ObjFanin0(pObj) );
if ( Gia_ObjIsAnd(Gia_ObjFanin1(pObj)) )
Gia_ObjSetAndLevel( pGia, Gia_ObjFanin1(pObj) );
Gia_ObjSetAndLevel( pGia, pObj );
}
}
return Abc_LitNotCond( Res, fCompl );
}
if ( (**p >= 'A' && **p <= 'F') || (**p >= '0' && **p <= '9') )
{
Vec_Int_t vLeaves; char * q;
word pFunc[DAU_DSD_MAX_VAR > 6 ? (1 << (DAU_DSD_MAX_VAR-6)) : 1];
int Fanins[DAU_DSD_MAX_VAR], Res, nObjOld;
int i, nVars = Abc_TtReadHex( pFunc, *p );
*p += Abc_TtHexDigitNum( nVars );
q = pStr + pMatches[ *p - pStr ];
assert( **p == '{' && *q == '}' );
for ( i = 0, (*p)++; *p < q; (*p)++, i++ )
Fanins[i] = Dau_DsdToGia_rec( pGia, pStr, p, pMatches, pLits, vCover );
assert( i == nVars );
assert( *p == q );
vLeaves.nCap = nVars;
vLeaves.nSize = nVars;
vLeaves.pArray = Fanins;
nObjOld = Gia_ManObjNum(pGia);
Res = Kit_TruthToGia( pGia, (unsigned *)pFunc, nVars, vCover, &vLeaves, 1 );
// assert( nVars <= 6 );
// Res = Dau_DsdToGiaCompose_rec( pGia, pFunc[0], Fanins, nVars );
for ( i = nObjOld; i < Gia_ManObjNum(pGia); i++ )
Gia_ObjSetGateLevel( pGia, Gia_ManObj(pGia, i) );
m_Non1Step++;
return Abc_LitNotCond( Res, fCompl );
}
assert( 0 );
return 0;
}
int Gia_ObjFromMiniFanin1Copy( Gia_Man_t * pGia, Vec_Int_t * vCopies, Mini_Aig_t * p, int Id )
{
int Lit = Mini_AigNodeFanin1( p, Id );
return Abc_LitNotCond( Vec_IntEntry(vCopies, Abc_Lit2Var(Lit)), Abc_LitIsCompl(Lit) );
}
Prio0 = Abc_Lit2Var(Gia_ObjFanin0(pObj)->Value);
Prio1 = Abc_Lit2Var(Gia_ObjFanin1(pObj)->Value);
Phase0 = Abc_LitIsCompl(Gia_ObjFanin0(pObj)->Value) ^ Gia_ObjFaninC0(pObj);
Phase1 = Abc_LitIsCompl(Gia_ObjFanin1(pObj)->Value) ^ Gia_ObjFaninC1(pObj);
if ( Phase0 && Phase1 )
Prio = (fGrow & 1) ? Abc_MinInt(Prio0, Prio1) : Abc_MaxInt(Prio0, Prio1);
else if ( Phase0 && !Phase1 )
Prio = Prio1;
else if ( !Phase0 && Phase1 )
Prio = Prio0;
else // if ( !Phase0 && !Phase1 )
Prio = (fGrow & 1) ? Abc_MaxInt(Prio0, Prio1) : Abc_MinInt(Prio0, Prio1);
pObj->Value = Abc_Var2Lit( Prio, Phase0 & Phase1 );
}
Gia_ManForEachCo( p, pObj, i )
pObj->Value = Abc_LitNotCond( Gia_ObjFanin0(pObj)->Value, Gia_ObjFaninC0(pObj) );
}
void Bmc_CexCarePropagateFwd( Gia_Man_t * p, Abc_Cex_t * pCex, int fGrow, Vec_Int_t * vPrios )
{
Gia_Obj_t * pObj, * pObjRo, * pObjRi;
int f, i;
Gia_ManConst0( p )->Value = 0;
Gia_ManForEachRi( p, pObj, i )
pObj->Value = 0;
Vec_IntClear( vPrios );
for ( f = 0; f <= pCex->iFrame; f++ )
{
Gia_ManForEachRiRo( p, pObjRi, pObjRo, i )
Vec_IntPush( vPrios, (pObjRo->Value = pObjRi->Value) );
Bmc_CexCarePropagateFwdOne( p, pCex, f, fGrow );
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Gia_Man_t * Ssc_PerformSweeping( Gia_Man_t * pAig, Gia_Man_t * pCare, Ssc_Pars_t * pPars )
{
Ssc_Man_t * p;
Gia_Man_t * pResult, * pTemp;
Gia_Obj_t * pObj, * pRepr;
abctime clk, clkTotal = Abc_Clock();
int i, fCompl, nRefined, status;
clk = Abc_Clock();
assert( Gia_ManRegNum(pCare) == 0 );
assert( Gia_ManCiNum(pAig) == Gia_ManCiNum(pCare) );
assert( Gia_ManIsNormalized(pAig) );
assert( Gia_ManIsNormalized(pCare) );
// reset random numbers
Gia_ManRandom( 1 );
// sweeping manager
p = Ssc_ManStart( pAig, pCare, pPars );
if ( p == NULL )
return Gia_ManDup( pAig );
if ( p->pPars->fVerbose )
printf( "Care set produced %d hits out of %d.\n", Ssc_GiaEstimateCare(p->pFraig, 5), 640 );
// perform simulation
while ( 1 )
{
// simulate care set
Ssc_GiaRandomPiPattern( p->pFraig, 5, NULL );
Ssc_GiaSimRound( p->pFraig );
// transfer care patterns to user's AIG
if ( !Ssc_GiaTransferPiPattern( pAig, p->pFraig, p->vPivot ) )
break;
// simulate the main AIG
Ssc_GiaSimRound( pAig );
nRefined = Ssc_GiaClassesRefine( pAig );
if ( pPars->fVerbose )
Gia_ManEquivPrintClasses( pAig, 0, 0 );
if ( nRefined <= Gia_ManCandNum(pAig) / 100 )
break;
}
p->timeSimInit += Abc_Clock() - clk;
// prepare user's AIG
Gia_ManFillValue(pAig);
Gia_ManConst0(pAig)->Value = 0;
Gia_ManForEachCi( pAig, pObj, i )
pObj->Value = Gia_Obj2Lit( p->pFraig, Gia_ManCi(p->pFraig, i) );
// Gia_ManLevelNum(pAig);
// prepare swept AIG (should be done after starting SAT solver in Ssc_ManStart)
Gia_ManHashStart( p->pFraig );
// perform sweeping
Ssc_GiaResetPiPattern( pAig, pPars->nWords );
Ssc_GiaSavePiPattern( pAig, p->vPivot );
Gia_ManForEachCand( pAig, pObj, i )
{
if ( pAig->iPatsPi == 64 * pPars->nWords )
{
clk = Abc_Clock();
Ssc_GiaSimRound( pAig );
Ssc_GiaClassesRefine( pAig );
if ( pPars->fVerbose )
Gia_ManEquivPrintClasses( pAig, 0, 0 );
Ssc_GiaClassesCheckPairs( pAig, p->vDisPairs );
Vec_IntClear( p->vDisPairs );
// prepare next patterns
Ssc_GiaResetPiPattern( pAig, pPars->nWords );
Ssc_GiaSavePiPattern( pAig, p->vPivot );
p->timeSimSat += Abc_Clock() - clk;
//printf( "\n" );
}
if ( Gia_ObjIsAnd(pObj) )
pObj->Value = Gia_ManHashAnd( p->pFraig, Gia_ObjFanin0Copy(pObj), Gia_ObjFanin1Copy(pObj) );
if ( !Gia_ObjHasRepr(pAig, i) )
continue;
pRepr = Gia_ObjReprObj(pAig, i);
if ( (int)pObj->Value == Abc_LitNotCond( pRepr->Value, pRepr->fPhase ^ pObj->fPhase ) )
{
Gia_ObjSetProved( pAig, i );
continue;
}
assert( Abc_Lit2Var(pRepr->Value) != Abc_Lit2Var(pObj->Value) );
fCompl = pRepr->fPhase ^ pObj->fPhase ^ Abc_LitIsCompl(pRepr->Value) ^ Abc_LitIsCompl(pObj->Value);
// perform SAT call
clk = Abc_Clock();
p->nSatCalls++;
status = Ssc_ManCheckEquivalence( p, Abc_Lit2Var(pRepr->Value), Abc_Lit2Var(pObj->Value), fCompl );
if ( status == l_False )
{
p->nSatCallsUnsat++;
pObj->Value = Abc_LitNotCond( pRepr->Value, pRepr->fPhase ^ pObj->fPhase );
Gia_ObjSetProved( pAig, i );
}
else if ( status == l_True )
{
p->nSatCallsSat++;
Ssc_GiaSavePiPattern( pAig, p->vPattern );
Vec_IntPush( p->vDisPairs, Gia_ObjRepr(p->pAig, i) );
Vec_IntPush( p->vDisPairs, i );
// printf( "Try %2d and %2d: ", Gia_ObjRepr(p->pAig, i), i );
// Vec_IntPrint( p->vPattern );
if ( Gia_ObjRepr(p->pAig, i) > 0 )
Ssc_GiaResimulateOneClass( p, Gia_ObjRepr(p->pAig, i), i );
}
else if ( status == l_Undef )
p->nSatCallsUndec++;
else assert( 0 );
p->timeSat += Abc_Clock() - clk;
}
if ( pAig->iPatsPi > 1 )
{
clk = Abc_Clock();
while ( pAig->iPatsPi < 64 * pPars->nWords )
Ssc_GiaSavePiPattern( pAig, p->vPivot );
Ssc_GiaSimRound( pAig );
Ssc_GiaClassesRefine( pAig );
if ( pPars->fVerbose )
Gia_ManEquivPrintClasses( pAig, 0, 0 );
Ssc_GiaClassesCheckPairs( pAig, p->vDisPairs );
Vec_IntClear( p->vDisPairs );
p->timeSimSat += Abc_Clock() - clk;
}
// Gia_ManEquivPrintClasses( pAig, 1, 0 );
// Gia_ManPrint( pAig );
// generate the resulting AIG
pResult = Gia_ManEquivReduce( pAig, 0, 0, 1, 0 );
if ( pResult == NULL )
{
printf( "There is no equivalences.\n" );
ABC_FREE( pAig->pReprs );
ABC_FREE( pAig->pNexts );
pResult = Gia_ManDup( pAig );
}
pResult = Gia_ManCleanup( pTemp = pResult );
Gia_ManStop( pTemp );
p->timeTotal = Abc_Clock() - clkTotal;
if ( pPars->fVerbose )
Ssc_ManPrintStats( p );
Ssc_ManStop( p );
// count the number of representatives
if ( pPars->fVerbose )
{
Abc_Print( 1, "Reduction in AIG nodes:%8d ->%8d (%6.2f %%). ",
Gia_ManAndNum(pAig), Gia_ManAndNum(pResult),
100.0 - 100.0 * Gia_ManAndNum(pResult) / Gia_ManAndNum(pAig) );
Abc_PrintTime( 1, "Time", Abc_Clock() - clkTotal );
}
return pResult;
}
static inline int Gia_ObjChild1Copy( Aig_Obj_t * pObj ) { return Abc_LitNotCond( Aig_ObjFanin1(pObj)->iData, Aig_ObjFaninC1(pObj) ); }
/**Function*************************************************************
Synopsis [Addes clauses to the solver.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static void Gia_ManAddClausesMux( Ssc_Man_t * p, Gia_Obj_t * pNode )
{
Gia_Obj_t * pNodeI, * pNodeT, * pNodeE;
int pLits[4], LitF, LitI, LitT, LitE, RetValue;
assert( !Gia_IsComplement( pNode ) );
assert( Gia_ObjIsMuxType( pNode ) );
// get nodes (I = if, T = then, E = else)
pNodeI = Gia_ObjRecognizeMux( pNode, &pNodeT, &pNodeE );
// get the Litiable numbers
LitF = Ssc_ObjSatLit( p, Gia_Obj2Lit(p->pFraig,pNode) );
LitI = Ssc_ObjSatLit( p, Gia_Obj2Lit(p->pFraig,pNodeI) );
LitT = Ssc_ObjSatLit( p, Gia_Obj2Lit(p->pFraig,pNodeT) );
LitE = Ssc_ObjSatLit( p, Gia_Obj2Lit(p->pFraig,pNodeE) );
// f = ITE(i, t, e)
// i' + t' + f
// i' + t + f'
// i + e' + f
// i + e + f'
// create four clauses
pLits[0] = Abc_LitNotCond(LitI, 1);
pLits[1] = Abc_LitNotCond(LitT, 1);
pLits[2] = Abc_LitNotCond(LitF, 0);
RetValue = sat_solver_addclause( p->pSat, pLits, pLits + 3 );
assert( RetValue );
pLits[0] = Abc_LitNotCond(LitI, 1);
pLits[1] = Abc_LitNotCond(LitT, 0);
pLits[2] = Abc_LitNotCond(LitF, 1);
RetValue = sat_solver_addclause( p->pSat, pLits, pLits + 3 );
assert( RetValue );
pLits[0] = Abc_LitNotCond(LitI, 0);
pLits[1] = Abc_LitNotCond(LitE, 1);
pLits[2] = Abc_LitNotCond(LitF, 0);
RetValue = sat_solver_addclause( p->pSat, pLits, pLits + 3 );
assert( RetValue );
pLits[0] = Abc_LitNotCond(LitI, 0);
pLits[1] = Abc_LitNotCond(LitE, 0);
pLits[2] = Abc_LitNotCond(LitF, 1);
RetValue = sat_solver_addclause( p->pSat, pLits, pLits + 3 );
assert( RetValue );
// two additional clauses
// t' & e' -> f'
// t & e -> f
// t + e + f'
// t' + e' + f
if ( LitT == LitE )
{
// assert( fCompT == !fCompE );
return;
}
pLits[0] = Abc_LitNotCond(LitT, 0);
pLits[1] = Abc_LitNotCond(LitE, 0);
pLits[2] = Abc_LitNotCond(LitF, 1);
RetValue = sat_solver_addclause( p->pSat, pLits, pLits + 3 );
assert( RetValue );
pLits[0] = Abc_LitNotCond(LitT, 1);
pLits[1] = Abc_LitNotCond(LitE, 1);
pLits[2] = Abc_LitNotCond(LitF, 0);
RetValue = sat_solver_addclause( p->pSat, pLits, pLits + 3 );
assert( RetValue );
}
/**Function*************************************************************
Synopsis [Derives GIA for the DSD formula.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Dau_DsdToGia2_rec( Gia_Man_t * pGia, char * pStr, char ** p, int * pMatches, int * pLits, Vec_Int_t * vCover )
{
int fCompl = 0;
if ( **p == '!' )
(*p)++, fCompl = 1;
if ( **p >= 'a' && **p < 'a' + DAU_DSD_MAX_VAR ) // var
return Abc_LitNotCond( pLits[**p - 'a'], fCompl );
if ( **p == '(' ) // and/or
{
char * q = pStr + pMatches[ *p - pStr ];
int Res = 1, Lit;
assert( **p == '(' && *q == ')' );
for ( (*p)++; *p < q; (*p)++ )
{
Lit = Dau_DsdToGia2_rec( pGia, pStr, p, pMatches, pLits, vCover );
Res = Gia_ManHashAnd( pGia, Res, Lit );
}
assert( *p == q );
return Abc_LitNotCond( Res, fCompl );
}
if ( **p == '[' ) // xor
{
char * q = pStr + pMatches[ *p - pStr ];
int Res = 0, Lit;
assert( **p == '[' && *q == ']' );
for ( (*p)++; *p < q; (*p)++ )
{
Lit = Dau_DsdToGia2_rec( pGia, pStr, p, pMatches, pLits, vCover );
if ( pGia->pMuxes )
Res = Gia_ManHashXorReal( pGia, Res, Lit );
else
Res = Gia_ManHashXor( pGia, Res, Lit );
}
assert( *p == q );
return Abc_LitNotCond( Res, fCompl );
}
if ( **p == '<' ) // mux
{
int nVars = 0;
int Temp[3], * pTemp = Temp, Res;
int Fanins[DAU_DSD_MAX_VAR], * pLits2;
char * pOld = *p;
char * q = pStr + pMatches[ *p - pStr ];
// read fanins
if ( *(q+1) == '{' )
{
char * q2;
*p = q+1;
q2 = pStr + pMatches[ *p - pStr ];
assert( **p == '{' && *q2 == '}' );
for ( nVars = 0, (*p)++; *p < q2; (*p)++, nVars++ )
Fanins[nVars] = Dau_DsdToGia2_rec( pGia, pStr, p, pMatches, pLits, vCover );
assert( *p == q2 );
pLits2 = Fanins;
}
else
pLits2 = pLits;
// read MUX
*p = pOld;
q = pStr + pMatches[ *p - pStr ];
assert( **p == '<' && *q == '>' );
// verify internal variables
if ( nVars )
for ( ; pOld < q; pOld++ )
if ( *pOld >= 'a' && *pOld <= 'z' )
assert( *pOld - 'a' < nVars );
// derive MUX components
for ( (*p)++; *p < q; (*p)++ )
*pTemp++ = Dau_DsdToGia2_rec( pGia, pStr, p, pMatches, pLits2, vCover );
assert( pTemp == Temp + 3 );
assert( *p == q );
if ( *(q+1) == '{' ) // and/or
{
char * q = pStr + pMatches[ ++(*p) - pStr ];
assert( **p == '{' && *q == '}' );
*p = q;
}
if ( pGia->pMuxes )
Res = Gia_ManHashMuxReal( pGia, Temp[0], Temp[1], Temp[2] );
else
Res = Gia_ManHashMux( pGia, Temp[0], Temp[1], Temp[2] );
return Abc_LitNotCond( Res, fCompl );
}
if ( (**p >= 'A' && **p <= 'F') || (**p >= '0' && **p <= '9') )
{
Vec_Int_t vLeaves; char * q;
word pFunc[DAU_DSD_MAX_VAR > 6 ? (1 << (DAU_DSD_MAX_VAR-6)) : 1];
int Fanins[DAU_DSD_MAX_VAR], Res;
int i, nVars = Abc_TtReadHex( pFunc, *p );
*p += Abc_TtHexDigitNum( nVars );
q = pStr + pMatches[ *p - pStr ];
assert( **p == '{' && *q == '}' );
for ( i = 0, (*p)++; *p < q; (*p)++, i++ )
Fanins[i] = Dau_DsdToGia2_rec( pGia, pStr, p, pMatches, pLits, vCover );
assert( i == nVars );
assert( *p == q );
// Res = Dau_DsdToGia2Compose_rec( pGia, Func, Fanins, nVars );
vLeaves.nCap = nVars;
vLeaves.nSize = nVars;
vLeaves.pArray = Fanins;
Res = Kit_TruthToGia( pGia, (unsigned *)pFunc, nVars, vCover, &vLeaves, 1 );
m_Non1Step++;
return Abc_LitNotCond( Res, fCompl );
}
assert( 0 );
return 0;
}
int Abc_NodeFanin1Copy2( Abc_Obj_t * pObj )
{
return Abc_LitNotCond( Abc_ObjFanin1(pObj)->iTemp, Abc_ObjFaninC1(pObj) );
}
// outputs
If_ManForEachCo( pIfMan, pIfObj, i )
{
int iLit0 = Abc_LitNotCond( Vec_IntEntry(vCopy, If_ObjFanin0(pIfObj)->Id), If_ObjFaninC0(pIfObj) );
Vec_IntPush( vCopy, Gia_ManAppendCo(pNew, iLit0) );
}
Abc_Obj_t * Abc_NodeFanin1Copy( Abc_Ntk_t * pNtk, Vec_Int_t * vCopies, Mini_Aig_t * p, int Id )
{
int Lit = Mini_AigNodeFanin1( p, Id );
int AbcLit = Abc_LitNotCond( Vec_IntEntry(vCopies, Abc_Lit2Var(Lit)), Abc_LitIsCompl(Lit) );
return Abc_ObjFromLit( pNtk, AbcLit );
}
/**Function*************************************************************
Synopsis [Performs AIG shrinking using the current mapping.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Gia_Man_t * Gia_ManMapShrink4( Gia_Man_t * p, int fKeepLevel, int fVerbose )
{
Vec_Int_t * vLeaves, * vTruth, * vVisited, * vLeavesBest;
Gia_Man_t * pNew, * pTemp;
Gia_Obj_t * pObj, * pFanin;
unsigned * pTruth;
int i, k, iFan;
abctime clk = Abc_Clock();
// int ClassCounts[222] = {0};
int * pLutClass, Counter = 0;
assert( p->pMapping != NULL );
if ( Gia_ManLutSizeMax( p ) > 4 )
{
printf( "Resynthesis is not performed when nodes have more than 4 inputs.\n" );
return NULL;
}
pLutClass = ABC_CALLOC( int, Gia_ManObjNum(p) );
vLeaves = Vec_IntAlloc( 0 );
vTruth = Vec_IntAlloc( (1<<16) );
vVisited = Vec_IntAlloc( 0 );
vLeavesBest = Vec_IntAlloc( 4 );
// prepare the library
Dar_LibPrepare( 5 );
// clean the old manager
Gia_ManCleanTruth( p );
Gia_ManSetPhase( p );
Gia_ManFillValue( p );
Gia_ManConst0(p)->Value = 0;
// start the new manager
pNew = Gia_ManStart( Gia_ManObjNum(p) );
pNew->pName = Abc_UtilStrsav( p->pName );
pNew->pSpec = Abc_UtilStrsav( p->pSpec );
Gia_ManHashAlloc( pNew );
Gia_ManCleanLevels( pNew, Gia_ManObjNum(p) );
Gia_ManForEachObj1( p, pObj, i )
{
if ( Gia_ObjIsCi(pObj) )
{
pObj->Value = Gia_ManAppendCi( pNew );
if ( p->vLevels )
Gia_ObjSetLevel( pNew, Gia_ObjFromLit(pNew, Gia_ObjValue(pObj)), Gia_ObjLevel(p, pObj) );
}
else if ( Gia_ObjIsCo(pObj) )
{
pObj->Value = Gia_ManAppendCo( pNew, Gia_ObjFanin0Copy(pObj) );
}
else if ( Gia_ObjIsLut(p, i) )
{
Counter++;
// collect leaves of this gate
Vec_IntClear( vLeaves );
Gia_LutForEachFanin( p, i, iFan, k )
Vec_IntPush( vLeaves, iFan );
for ( ; k < 4; k++ )
Vec_IntPush( vLeaves, 0 );
//.compute the truth table
pTruth = Gia_ManConvertAigToTruth( p, pObj, vLeaves, vTruth, vVisited );
// change from node IDs to their literals
Gia_ManForEachObjVec( vLeaves, p, pFanin, k )
{
assert( Gia_ObjValue(pFanin) != ~0 );
Vec_IntWriteEntry( vLeaves, k, Gia_ObjValue(pFanin) );
}
// derive new structre
if ( Gia_ManTruthIsConst0(pTruth, Vec_IntSize(vLeaves)) )
pObj->Value = 0;
else if ( Gia_ManTruthIsConst1(pTruth, Vec_IntSize(vLeaves)) )
pObj->Value = 1;
else
{
pObj->Value = Dar_LibEvalBuild( pNew, vLeaves, 0xffff & *pTruth, fKeepLevel, vLeavesBest );
pObj->Value = Abc_LitNotCond( pObj->Value, Gia_ObjPhaseRealLit(pNew, pObj->Value) ^ pObj->fPhase );
}
}
}
