/**Function*************************************************************
Synopsis [Creates the dual output miter.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Man_t * Aig_ManCreateDualOutputMiter( Aig_Man_t * p1, Aig_Man_t * p2 )
{
Aig_Man_t * pNew;
Aig_Obj_t * pObj;
int i;
assert( Aig_ManPiNum(p1) == Aig_ManPiNum(p2) );
assert( Aig_ManPoNum(p1) == Aig_ManPoNum(p2) );
pNew = Aig_ManStart( Aig_ManObjNumMax(p1) + Aig_ManObjNumMax(p2) );
// add first AIG
Aig_ManConst1(p1)->pData = Aig_ManConst1(pNew);
Aig_ManForEachPi( p1, pObj, i )
pObj->pData = Aig_ObjCreatePi( pNew );
Aig_ManForEachNode( p1, pObj, i )
pObj->pData = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
// add second AIG
Aig_ManConst1(p2)->pData = Aig_ManConst1(pNew);
Aig_ManForEachPi( p2, pObj, i )
pObj->pData = Aig_ManPi( pNew, i );
Aig_ManForEachNode( p2, pObj, i )
pObj->pData = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
// add the outputs
for ( i = 0; i < Aig_ManPoNum(p1); i++ )
{
Aig_ObjCreatePo( pNew, Aig_ObjChild0Copy(Aig_ManPo(p1, i)) );
Aig_ObjCreatePo( pNew, Aig_ObjChild0Copy(Aig_ManPo(p2, i)) );
}
Aig_ManCleanup( pNew );
return pNew;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Man_t * Saig_ManTemporDecompose( Aig_Man_t * pAig, int nFrames )
{
Aig_Man_t * pAigNew, * pFrames;
Aig_Obj_t * pObj, * pReset;
int i;
if ( pAig->nConstrs > 0 )
{
printf( "The AIG manager should have no constraints.\n" );
return NULL;
}
// create initialized timeframes
pFrames = Saig_ManTemporFrames( pAig, nFrames );
assert( Aig_ManPoNum(pFrames) == Aig_ManRegNum(pAig) );
// start the new manager
Aig_ManCleanData( pAig );
pAigNew = Aig_ManStart( Aig_ManNodeNum(pAig) );
pAigNew->pName = Aig_UtilStrsav( pAig->pName );
// map the constant node and primary inputs
Aig_ManConst1(pAig)->pData = Aig_ManConst1( pAigNew );
Saig_ManForEachPi( pAig, pObj, i )
pObj->pData = Aig_ObjCreatePi( pAigNew );
// insert initialization logic
Aig_ManConst1(pFrames)->pData = Aig_ManConst1( pAigNew );
Aig_ManForEachPi( pFrames, pObj, i )
pObj->pData = Aig_ObjCreatePi( pAigNew );
Aig_ManForEachNode( pFrames, pObj, i )
pObj->pData = Aig_And( pAigNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
Aig_ManForEachPo( pFrames, pObj, i )
pObj->pData = Aig_ObjChild0Copy(pObj);
// create reset latch (the first one among the latches)
pReset = Aig_ObjCreatePi( pAigNew );
// create flop output values
Saig_ManForEachLo( pAig, pObj, i )
pObj->pData = Aig_Mux( pAigNew, pReset, Aig_ObjCreatePi(pAigNew), (Aig_Obj_t *)Aig_ManPo(pFrames, i)->pData );
Aig_ManStop( pFrames );
// add internal nodes of this frame
Aig_ManForEachNode( pAig, pObj, i )
pObj->pData = Aig_And( pAigNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
// create primary outputs
Saig_ManForEachPo( pAig, pObj, i )
Aig_ObjCreatePo( pAigNew, Aig_ObjChild0Copy(pObj) );
// create reset latch (the first one among the latches)
Aig_ObjCreatePo( pAigNew, Aig_ManConst1(pAigNew) );
// create latch inputs
Saig_ManForEachLi( pAig, pObj, i )
Aig_ObjCreatePo( pAigNew, Aig_ObjChild0Copy(pObj) );
// finalize
Aig_ManCleanup( pAigNew );
Aig_ManSetRegNum( pAigNew, Aig_ManRegNum(pAig)+1 ); // + reset latch (011111...)
return pAigNew;
}
/**Function*************************************************************
Synopsis [Duplicates while ORing the POs of sequential circuit.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Man_t * Saig_ManCreateEquivMiter( Aig_Man_t * pAig, Vec_Int_t * vPairs )
{
Aig_Man_t * pAigNew;
Aig_Obj_t * pObj, * pObj2, * pMiter;
int i;
if ( pAig->nConstrs > 0 )
{
printf( "The AIG manager should have no constraints.\n" );
return NULL;
}
// start the new manager
pAigNew = Aig_ManStart( Aig_ManNodeNum(pAig) );
pAigNew->pName = Aig_UtilStrsav( pAig->pName );
pAigNew->nConstrs = pAig->nConstrs;
// map the constant node
Aig_ManConst1(pAig)->pData = Aig_ManConst1( pAigNew );
// create variables for PIs
Aig_ManForEachPi( pAig, pObj, i )
pObj->pData = Aig_ObjCreatePi( pAigNew );
// add internal nodes of this frame
Aig_ManForEachNode( pAig, pObj, i )
pObj->pData = Aig_And( pAigNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
// create POs
assert( Vec_IntSize(vPairs) % 2 == 0 );
Aig_ManForEachNodeVec( pAig, vPairs, pObj, i )
{
pObj2 = Aig_ManObj( pAig, Vec_IntEntry(vPairs, ++i) );
pMiter = Aig_Exor( pAigNew, (Aig_Obj_t *)pObj->pData, (Aig_Obj_t *)pObj2->pData );
pMiter = Aig_NotCond( pMiter, pObj->fPhase ^ pObj2->fPhase );
Aig_ObjCreatePo( pAigNew, pMiter );
}
/**Function*************************************************************
Synopsis [Performs ternary simulation for one design.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Saig_ManSimDataInit( Aig_Man_t * p, Abc_Cex_t * pCex, Vec_Ptr_t * vSimInfo, Vec_Int_t * vRes )
{
Aig_Obj_t * pObj, * pObjLi, * pObjLo;
int i, f, Entry, iBit = 0;
Saig_ManForEachLo( p, pObj, i )
Saig_ManSimInfoSet( vSimInfo, pObj, 0, Abc_InfoHasBit(pCex->pData, iBit++)?SAIG_ONE:SAIG_ZER );
for ( f = 0; f <= pCex->iFrame; f++ )
{
Saig_ManSimInfoSet( vSimInfo, Aig_ManConst1(p), f, SAIG_ONE );
Saig_ManForEachPi( p, pObj, i )
Saig_ManSimInfoSet( vSimInfo, pObj, f, Abc_InfoHasBit(pCex->pData, iBit++)?SAIG_ONE:SAIG_ZER );
if ( vRes )
Vec_IntForEachEntry( vRes, Entry, i )
Saig_ManSimInfoSet( vSimInfo, Aig_ManCi(p, Entry), f, SAIG_UND );
Aig_ManForEachNode( p, pObj, i )
Saig_ManExtendOneEval( vSimInfo, pObj, f );
Aig_ManForEachCo( p, pObj, i )
Saig_ManExtendOneEval( vSimInfo, pObj, f );
if ( f == pCex->iFrame )
break;
Saig_ManForEachLiLo( p, pObjLi, pObjLo, i )
Saig_ManSimInfoSet( vSimInfo, pObjLo, f+1, Saig_ManSimInfoGet(vSimInfo, pObjLi, f) );
}
// make sure the output of the property failed
pObj = Aig_ManCo( p, pCex->iPo );
return Saig_ManSimInfoGet( vSimInfo, pObj, pCex->iFrame );
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Unroll the circuit the given number of timeframes.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Man_t * Inter_ManFramesBmc( Aig_Man_t * pAig, int nFrames )
{
Aig_Man_t * pFrames;
Aig_Obj_t * pObj, * pObjLi, * pObjLo;
int i, f;
assert( Saig_ManRegNum(pAig) > 0 );
assert( Saig_ManPoNum(pAig) == 1 );
pFrames = Aig_ManStart( Aig_ManNodeNum(pAig) * nFrames );
// map the constant node
Aig_ManConst1(pAig)->pData = Aig_ManConst1( pFrames );
// create variables for register outputs
Saig_ManForEachLo( pAig, pObj, i )
pObj->pData = Aig_ManConst0( pFrames );
// add timeframes
for ( f = 0; f < nFrames; f++ )
{
// create PI nodes for this frame
Saig_ManForEachPi( pAig, pObj, i )
pObj->pData = Aig_ObjCreateCi( pFrames );
// add internal nodes of this frame
Aig_ManForEachNode( pAig, pObj, i )
pObj->pData = Aig_And( pFrames, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
if ( f == nFrames - 1 )
break;
// transfer to register outputs
Saig_ManForEachLiLo( pAig, pObjLi, pObjLo, i )
pObjLi->pData = Aig_ObjChild0Copy(pObjLi);
// transfer to register outputs
Saig_ManForEachLiLo( pAig, pObjLi, pObjLo, i )
pObjLo->pData = pObjLi->pData;
}
// create POs for the output of the last frame
pObj = Aig_ManCo( pAig, 0 );
Aig_ObjCreateCo( pFrames, Aig_ObjChild0Copy(pObj) );
Aig_ManCleanup( pFrames );
return pFrames;
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Duplicates while ORing the POs of sequential circuit.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Man_t * Saig_ManDupOrpos( Aig_Man_t * pAig )
{
Aig_Man_t * pAigNew;
Aig_Obj_t * pObj, * pMiter;
int i;
if ( pAig->nConstrs > 0 )
{
printf( "The AIG manager should have no constraints.\n" );
return NULL;
}
// start the new manager
pAigNew = Aig_ManStart( Aig_ManNodeNum(pAig) );
pAigNew->pName = Aig_UtilStrsav( pAig->pName );
pAigNew->nConstrs = pAig->nConstrs;
// map the constant node
Aig_ManConst1(pAig)->pData = Aig_ManConst1( pAigNew );
// create variables for PIs
Aig_ManForEachPi( pAig, pObj, i )
pObj->pData = Aig_ObjCreatePi( pAigNew );
// add internal nodes of this frame
Aig_ManForEachNode( pAig, pObj, i )
pObj->pData = Aig_And( pAigNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
// create PO of the circuit
pMiter = Aig_ManConst0( pAigNew );
Saig_ManForEachPo( pAig, pObj, i )
pMiter = Aig_Or( pAigNew, pMiter, Aig_ObjChild0Copy(pObj) );
Aig_ObjCreatePo( pAigNew, pMiter );
// transfer to register outputs
Saig_ManForEachLi( pAig, pObj, i )
Aig_ObjCreatePo( pAigNew, Aig_ObjChild0Copy(pObj) );
Aig_ManCleanup( pAigNew );
Aig_ManSetRegNum( pAigNew, Aig_ManRegNum(pAig) );
return pAigNew;
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Creates initialized timeframes for temporal decomposition.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Man_t * Saig_ManTemporFrames( Aig_Man_t * pAig, int nFrames )
{
Aig_Man_t * pFrames;
Aig_Obj_t * pObj, * pObjLi, * pObjLo;
int i, f;
// start the frames package
Aig_ManCleanData( pAig );
pFrames = Aig_ManStart( Aig_ManObjNumMax(pAig) * nFrames );
pFrames->pName = Aig_UtilStrsav( pAig->pName );
// initiliaze the flops
Saig_ManForEachLo( pAig, pObj, i )
pObj->pData = Aig_ManConst0(pFrames);
// for each timeframe
for ( f = 0; f < nFrames; f++ )
{
Aig_ManConst1(pAig)->pData = Aig_ManConst1(pFrames);
Saig_ManForEachPi( pAig, pObj, i )
pObj->pData = Aig_ObjCreatePi(pFrames);
Aig_ManForEachNode( pAig, pObj, i )
pObj->pData = Aig_And( pFrames, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
Aig_ManForEachPo( pAig, pObj, i )
pObj->pData = Aig_ObjChild0Copy(pObj);
Saig_ManForEachLiLo( pAig, pObjLi, pObjLo, i )
pObjLo->pData = pObjLi->pData;
}
// create POs for the flop inputs
Saig_ManForEachLi( pAig, pObj, i )
Aig_ObjCreatePo( pFrames, (Aig_Obj_t *)pObj->pData );
Aig_ManCleanup( pFrames );
return pFrames;
}
/**Function*************************************************************
Synopsis [Duplicate the AIG w/o POs and transforms to transit into init state.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Man_t * Inter_ManStartOneOutput( Aig_Man_t * p, int fAddFirstPo )
{
Aig_Man_t * pNew;
Aig_Obj_t * pObj, * pObjLi, * pObjLo;
Aig_Obj_t * pCtrl = NULL; // Suppress "might be used uninitialized"
int i;
assert( Aig_ManRegNum(p) > 0 );
// create the new manager
pNew = Aig_ManStart( Aig_ManObjNumMax(p) );
pNew->pName = Abc_UtilStrsav( p->pName );
pNew->pSpec = Abc_UtilStrsav( p->pSpec );
// create the PIs
Aig_ManCleanData( p );
Aig_ManConst1(p)->pData = Aig_ManConst1(pNew);
Aig_ManForEachCi( p, pObj, i )
{
if ( i == Saig_ManPiNum(p) )
pCtrl = Aig_ObjCreateCi( pNew );
pObj->pData = Aig_ObjCreateCi( pNew );
}
// set registers
pNew->nRegs = fAddFirstPo? 0 : p->nRegs;
pNew->nTruePis = fAddFirstPo? Aig_ManCiNum(p) + 1 : p->nTruePis + 1;
pNew->nTruePos = fAddFirstPo + Saig_ManConstrNum(p);
// duplicate internal nodes
Aig_ManForEachNode( p, pObj, i )
pObj->pData = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
// create constraint outputs
Saig_ManForEachPo( p, pObj, i )
{
if ( i < Saig_ManPoNum(p)-Saig_ManConstrNum(p) )
continue;
Aig_ObjCreateCo( pNew, Aig_Not( Aig_ObjChild0Copy(pObj) ) );
}
// add the PO
if ( fAddFirstPo )
{
pObj = Aig_ManCo( p, 0 );
Aig_ObjCreateCo( pNew, Aig_ObjChild0Copy(pObj) );
}
else
{
// create register inputs with MUXes
Saig_ManForEachLiLo( p, pObjLi, pObjLo, i )
{
pObj = Aig_Mux( pNew, pCtrl, (Aig_Obj_t *)pObjLo->pData, Aig_ObjChild0Copy(pObjLi) );
// pObj = Aig_Mux( pNew, pCtrl, Aig_ManConst0(pNew), Aig_ObjChild0Copy(pObjLi) );
Aig_ObjCreateCo( pNew, pObj );
}
}
/**Function*************************************************************
Synopsis [Duplicates AIG while mapping PIs into the given array.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Aig_ManAppend( Aig_Man_t * pBase, Aig_Man_t * pNew )
{
Aig_Obj_t * pObj;
int i;
assert( Aig_ManCoNum(pNew) == 1 );
assert( Aig_ManCiNum(pNew) == Aig_ManCiNum(pBase) );
// create the PIs
Aig_ManCleanData( pNew );
Aig_ManConst1(pNew)->pData = Aig_ManConst1(pBase);
Aig_ManForEachCi( pNew, pObj, i )
pObj->pData = Aig_IthVar(pBase, i);
// duplicate internal nodes
Aig_ManForEachNode( pNew, pObj, i )
pObj->pData = Aig_And( pBase, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
// add one PO to base
pObj = Aig_ManCo( pNew, 0 );
Aig_ObjCreateCo( pBase, Aig_ObjChild0Copy(pObj) );
}
/**Function*************************************************************
Synopsis [Cycles the circuit to create a new initial state.]
Description [Simulates the circuit with random input for the given
number of timeframes to get a better initial state.]
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Aig_ManTernarySimulate( Aig_Man_t * p, int fVerbose )
{
Aig_Tsi_t * pTsi;
Vec_Ptr_t * vMap;
Aig_Obj_t * pObj, * pObjLi, * pObjLo;
unsigned * pState, * pPrev;
int i, k, f, fConstants, Value, nCounter;
// allocate the simulation manager
pTsi = Aig_TsiStart( p );
// initialize the values
Aig_ObjSetXsim( Aig_ManConst1(p), AIG_XVS1 );
Aig_ManForEachPiSeq( p, pObj, i )
Aig_ObjSetXsim( pObj, AIG_XVSX );
Aig_ManForEachLoSeq( p, pObj, i )
Aig_ObjSetXsim( pObj, AIG_XVS0 );
// simulate for the given number of timeframes
for ( f = 0; f < TSI_MAX_ROUNDS; f++ )
{
// collect this state
pState = Aig_TsiStateNew( pTsi );
Aig_ManForEachLiLoSeq( p, pObjLi, pObjLo, i )
{
Value = Aig_ObjGetXsim(pObjLo);
if ( Value & 1 )
Aig_InfoSetBit( pState, 2 * i );
if ( Value & 2 )
Aig_InfoSetBit( pState, 2 * i + 1 );
}
// Aig_TsiStatePrint( pTsi, pState );
// check if this state exists
if ( Aig_TsiStateLookup( pTsi, pState, pTsi->nWords ) )
break;
// insert this state
Aig_TsiStateInsert( pTsi, pState, pTsi->nWords );
// simulate internal nodes
Aig_ManForEachNode( p, pObj, i )
Aig_ObjSetXsim( pObj, Aig_XsimAnd(Aig_ObjGetXsimFanin0(pObj), Aig_ObjGetXsimFanin1(pObj)) );
// transfer the latch values
Aig_ManForEachLiSeq( p, pObj, i )
Aig_ObjSetXsim( pObj, Aig_ObjGetXsimFanin0(pObj) );
Aig_ManForEachLiLoSeq( p, pObjLi, pObjLo, i )
Aig_ObjSetXsim( pObjLo, Aig_ObjGetXsim(pObjLi) );
}
/**Function*************************************************************
Synopsis [Duplicate the AIG w/o POs.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Man_t * Inter_ManStartDuplicated( Aig_Man_t * p )
{
Aig_Man_t * pNew;
Aig_Obj_t * pObj;
int i;
assert( Aig_ManRegNum(p) > 0 );
// create the new manager
pNew = Aig_ManStart( Aig_ManObjNumMax(p) );
pNew->pName = Abc_UtilStrsav( p->pName );
pNew->pSpec = Abc_UtilStrsav( p->pSpec );
// create the PIs
Aig_ManCleanData( p );
Aig_ManConst1(p)->pData = Aig_ManConst1(pNew);
Aig_ManForEachCi( p, pObj, i )
pObj->pData = Aig_ObjCreateCi( pNew );
// set registers
pNew->nTruePis = p->nTruePis;
pNew->nTruePos = Saig_ManConstrNum(p);
pNew->nRegs = p->nRegs;
// duplicate internal nodes
Aig_ManForEachNode( p, pObj, i )
pObj->pData = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
// create constraint outputs
Saig_ManForEachPo( p, pObj, i )
{
if ( i < Saig_ManPoNum(p)-Saig_ManConstrNum(p) )
continue;
Aig_ObjCreateCo( pNew, Aig_Not( Aig_ObjChild0Copy(pObj) ) );
}
// create register inputs with MUXes
Saig_ManForEachLi( p, pObj, i )
Aig_ObjCreateCo( pNew, Aig_ObjChild0Copy(pObj) );
Aig_ManCleanup( pNew );
return pNew;
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Constructs initialized timeframes with constraints as POs.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Man_t * Ssw_FramesWithConstraints( Aig_Man_t * p, int nFrames )
{
Aig_Man_t * pFrames;
Aig_Obj_t * pObj, * pObjLi, * pObjLo;
int i, f;
// assert( Saig_ManConstrNum(p) > 0 );
assert( Aig_ManRegNum(p) > 0 );
assert( Aig_ManRegNum(p) < Aig_ManCiNum(p) );
// start the fraig package
pFrames = Aig_ManStart( Aig_ManObjNumMax(p) * nFrames );
// create latches for the first frame
Saig_ManForEachLo( p, pObj, i )
Aig_ObjSetCopy( pObj, Aig_ManConst0(pFrames) );
// add timeframes
for ( f = 0; f < nFrames; f++ )
{
// map constants and PIs
Aig_ObjSetCopy( Aig_ManConst1(p), Aig_ManConst1(pFrames) );
Saig_ManForEachPi( p, pObj, i )
Aig_ObjSetCopy( pObj, Aig_ObjCreateCi(pFrames) );
// add internal nodes of this frame
Aig_ManForEachNode( p, pObj, i )
Aig_ObjSetCopy( pObj, Aig_And( pFrames, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) ) );
// transfer to the primary output
Aig_ManForEachCo( p, pObj, i )
Aig_ObjSetCopy( pObj, Aig_ObjChild0Copy(pObj) );
// create constraint outputs
Saig_ManForEachPo( p, pObj, i )
{
if ( i < Saig_ManPoNum(p) - Saig_ManConstrNum(p) )
continue;
Aig_ObjCreateCo( pFrames, Aig_Not( Aig_ObjCopy(pObj) ) );
}
// transfer latch inputs to the latch outputs
Saig_ManForEachLiLo( p, pObjLi, pObjLo, i )
Aig_ObjSetCopy( pObjLo, Aig_ObjCopy(pObjLi) );
}
// remove dangling nodes
Aig_ManCleanup( pFrames );
return pFrames;
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Create timeframes of the manager for interpolation.]
Description [The resulting manager is combinational. The primary inputs
corresponding to register outputs are ordered first. The only POs of the
manager is the property output of the last timeframe.]
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Man_t * Inter_ManFramesInter( Aig_Man_t * pAig, int nFrames, int fAddRegOuts )
{
Aig_Man_t * pFrames;
Aig_Obj_t * pObj, * pObjLi, * pObjLo;
int i, f;
assert( Saig_ManRegNum(pAig) > 0 );
assert( Saig_ManPoNum(pAig)-Saig_ManConstrNum(pAig) == 1 );
pFrames = Aig_ManStart( Aig_ManNodeNum(pAig) * nFrames );
// map the constant node
Aig_ManConst1(pAig)->pData = Aig_ManConst1( pFrames );
// create variables for register outputs
if ( fAddRegOuts )
{
Saig_ManForEachLo( pAig, pObj, i )
pObj->pData = Aig_ManConst0( pFrames );
}
else
{
Saig_ManForEachLo( pAig, pObj, i )
pObj->pData = Aig_ObjCreatePi( pFrames );
}
// add timeframes
for ( f = 0; f < nFrames; f++ )
{
// create PI nodes for this frame
Saig_ManForEachPi( pAig, pObj, i )
pObj->pData = Aig_ObjCreatePi( pFrames );
// add internal nodes of this frame
Aig_ManForEachNode( pAig, pObj, i )
pObj->pData = Aig_And( pFrames, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
// add outputs for constraints
Saig_ManForEachPo( pAig, pObj, i )
{
if ( i < Saig_ManPoNum(pAig)-Saig_ManConstrNum(pAig) )
continue;
Aig_ObjCreatePo( pFrames, Aig_Not( Aig_ObjChild0Copy(pObj) ) );
}
if ( f == nFrames - 1 )
break;
// save register inputs
Saig_ManForEachLi( pAig, pObj, i )
pObj->pData = Aig_ObjChild0Copy(pObj);
// transfer to register outputs
Saig_ManForEachLiLo( pAig, pObjLi, pObjLo, i )
pObjLo->pData = pObjLi->pData;
}
// create POs for each register output
if ( fAddRegOuts )
{
Saig_ManForEachLi( pAig, pObj, i )
Aig_ObjCreatePo( pFrames, Aig_ObjChild0Copy(pObj) );
}
// create the only PO of the manager
else
{
pObj = Aig_ManPo( pAig, 0 );
Aig_ObjCreatePo( pFrames, Aig_ObjChild0Copy(pObj) );
}
Aig_ManCleanup( pFrames );
return pFrames;
}