/**Function*************************************************************
Synopsis [Checks if node with the given attributes is in the hash table.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_TableLookup( Aig_Man_t * p, Aig_Obj_t * pGhost )
{
Aig_Obj_t * pEntry;
assert( !Aig_IsComplement(pGhost) );
if ( pGhost->Type == AIG_OBJ_LATCH )
{
assert( Aig_ObjChild0(pGhost) && Aig_ObjChild1(pGhost) == NULL );
if ( !Aig_ObjRefs(Aig_ObjFanin0(pGhost)) )
return NULL;
}
else
{
assert( pGhost->Type == AIG_OBJ_AND );
assert( Aig_ObjChild0(pGhost) && Aig_ObjChild1(pGhost) );
assert( Aig_ObjFanin0(pGhost)->Id < Aig_ObjFanin1(pGhost)->Id );
if ( !Aig_ObjRefs(Aig_ObjFanin0(pGhost)) || !Aig_ObjRefs(Aig_ObjFanin1(pGhost)) )
return NULL;
}
for ( pEntry = p->pTable[Aig_Hash(pGhost, p->nTableSize)]; pEntry; pEntry = pEntry->pNext )
{
if ( Aig_ObjChild0(pEntry) == Aig_ObjChild0(pGhost) &&
Aig_ObjChild1(pEntry) == Aig_ObjChild1(pGhost) &&
Aig_ObjType(pEntry) == Aig_ObjType(pGhost) )
return pEntry;
}
return NULL;
}
/**Function*************************************************************
Synopsis [Replaces node with a buffer fanin by a node without them.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Aig_NodeFixBufferFanins( Aig_Man_t * p, Aig_Obj_t * pObj, int fNodesOnly, int fUpdateLevel )
{
Aig_Obj_t * pFanReal0, * pFanReal1, * pResult;
p->nBufFixes++;
if ( Aig_ObjIsPo(pObj) )
{
assert( Aig_ObjIsBuf(Aig_ObjFanin0(pObj)) );
pFanReal0 = Aig_ObjReal_rec( Aig_ObjChild0(pObj) );
assert( Aig_ObjPhaseReal(Aig_ObjChild0(pObj)) == Aig_ObjPhaseReal(pFanReal0) );
Aig_ObjPatchFanin0( p, pObj, pFanReal0 );
return;
}
assert( Aig_ObjIsNode(pObj) );
assert( Aig_ObjIsBuf(Aig_ObjFanin0(pObj)) || Aig_ObjIsBuf(Aig_ObjFanin1(pObj)) );
// get the real fanins
pFanReal0 = Aig_ObjReal_rec( Aig_ObjChild0(pObj) );
pFanReal1 = Aig_ObjReal_rec( Aig_ObjChild1(pObj) );
// get the new node
if ( Aig_ObjIsNode(pObj) )
pResult = Aig_Oper( p, pFanReal0, pFanReal1, Aig_ObjType(pObj) );
// else if ( Aig_ObjIsLatch(pObj) )
// pResult = Aig_Latch( p, pFanReal0, Aig_ObjInit(pObj) );
else
assert( 0 );
// replace the node with buffer by the node without buffer
Aig_ObjReplace( p, pObj, pResult, fNodesOnly, fUpdateLevel );
}
/**Function*************************************************************
Synopsis [Creates the canonical form of the node.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_CanonPair_rec( Aig_Man_t * p, Aig_Obj_t * pGhost )
{
Aig_Obj_t * pResult, * pLat0, * pLat1;
int fCompl0, fCompl1;
Aig_Type_t Type;
assert( Aig_ObjIsNode(pGhost) );
// consider the case when the pair is canonical
if ( !Aig_ObjIsLatch(Aig_ObjFanin0(pGhost)) || !Aig_ObjIsLatch(Aig_ObjFanin1(pGhost)) )
{
if ( (pResult = Aig_TableLookup( p, pGhost )) )
return pResult;
return Aig_ObjCreate( p, pGhost );
}
/// remember the latches
pLat0 = Aig_ObjFanin0(pGhost);
pLat1 = Aig_ObjFanin1(pGhost);
// remember type and compls
Type = Aig_ObjType(pGhost);
fCompl0 = Aig_ObjFaninC0(pGhost);
fCompl1 = Aig_ObjFaninC1(pGhost);
// call recursively
pResult = Aig_Oper( p, Aig_NotCond(Aig_ObjChild0(pLat0), fCompl0), Aig_NotCond(Aig_ObjChild0(pLat1), fCompl1), Type );
// build latch on top of this
return Aig_Latch( p, pResult, (Type == AIG_OBJ_AND)? fCompl0 & fCompl1 : fCompl0 ^ fCompl1 );
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Detects multi-input AND gate rooted at this node.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Aig_ManFindImplications_rec( Aig_Obj_t * pObj, Vec_Ptr_t * vImplics )
{
if ( Aig_IsComplement(pObj) || Aig_ObjIsCi(pObj) )
{
Vec_PtrPushUnique( vImplics, pObj );
return;
}
Aig_ManFindImplications_rec( Aig_ObjChild0(pObj), vImplics );
Aig_ManFindImplications_rec( Aig_ObjChild1(pObj), vImplics );
}
// add fanouts
Aig_ManForEachObj( p, pObj, i )
{
if ( Aig_ObjChild0(pObj) )
Aig_ObjSetFanoutStatic( Aig_ObjFanin0(pObj), pObj );
if ( Aig_ObjChild1(pObj) )
Aig_ObjSetFanoutStatic( Aig_ObjFanin1(pObj), pObj );
}
/**Function*************************************************************
Synopsis [Checks if node with the given attributes is in the hash table.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_TableLookup( Aig_Man_t * p, Aig_Obj_t * pGhost )
{
Aig_Obj_t * pEntry;
assert( !Aig_IsComplement(pGhost) );
assert( Aig_ObjIsNode(pGhost) );
assert( Aig_ObjChild0(pGhost) && Aig_ObjChild1(pGhost) );
assert( Aig_ObjFanin0(pGhost)->Id < Aig_ObjFanin1(pGhost)->Id );
if ( p->pTable == NULL || !Aig_ObjRefs(Aig_ObjFanin0(pGhost)) || !Aig_ObjRefs(Aig_ObjFanin1(pGhost)) )
return NULL;
for ( pEntry = p->pTable[Aig_Hash(pGhost, p->nTableSize)]; pEntry; pEntry = pEntry->pNext )
{
if ( Aig_ObjChild0(pEntry) == Aig_ObjChild0(pGhost) &&
Aig_ObjChild1(pEntry) == Aig_ObjChild1(pGhost) &&
Aig_ObjType(pEntry) == Aig_ObjType(pGhost) )
return pEntry;
}
return NULL;
}
/**Function*************************************************************
Synopsis [Checks the consistency of phase assignment.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Aig_ManCheckPhase( Aig_Man_t * p )
{
Aig_Obj_t * pObj;
int i;
Aig_ManForEachObj( p, pObj, i )
if ( Aig_ObjIsCi(pObj) )
assert( (int)pObj->fPhase == 0 );
else
assert( (int)pObj->fPhase == (Aig_ObjPhaseReal(Aig_ObjChild0(pObj)) & Aig_ObjPhaseReal(Aig_ObjChild1(pObj))) );
}
/**Function*************************************************************
Synopsis [Collects the supergate.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Saig_DetectConstrCollectSuper( Aig_Obj_t * pObj )
{
Vec_Ptr_t * vSuper;
assert( !Aig_IsComplement(pObj) );
assert( Aig_ObjIsAnd(pObj) );
vSuper = Vec_PtrAlloc( 4 );
Saig_DetectConstrCollectSuper_rec( Aig_ObjChild0(pObj), vSuper );
Saig_DetectConstrCollectSuper_rec( Aig_ObjChild1(pObj), vSuper );
return vSuper;
}
/**Function*************************************************************
Synopsis [Collects the nodes of the supergate.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Dar_BalanceCone_rec( Aig_Obj_t * pRoot, Aig_Obj_t * pObj, Vec_Ptr_t * vSuper )
{
if ( pObj != pRoot && (Aig_IsComplement(pObj) || Aig_ObjType(pObj) != Aig_ObjType(pRoot) || Aig_ObjRefs(pObj) > 1 || Vec_PtrSize(vSuper) > 10000) )
Vec_PtrPush( vSuper, pObj );
else
{
assert( !Aig_IsComplement(pObj) );
assert( Aig_ObjIsNode(pObj) );
// go through the branches
Dar_BalanceCone_rec( pRoot, Aig_ObjReal_rec( Aig_ObjChild0(pObj) ), vSuper );
Dar_BalanceCone_rec( pRoot, Aig_ObjReal_rec( Aig_ObjChild1(pObj) ), vSuper );
}
}
// procedure to detect an EXOR gate
static inline int Aig_ObjIsExorType( Aig_Obj_t * p0, Aig_Obj_t * p1, Aig_Obj_t ** ppFan0, Aig_Obj_t ** ppFan1 )
{
if ( !Aig_IsComplement(p0) || !Aig_IsComplement(p1) )
return 0;
p0 = Aig_Regular(p0);
p1 = Aig_Regular(p1);
if ( !Aig_ObjIsAnd(p0) || !Aig_ObjIsAnd(p1) )
return 0;
if ( Aig_ObjFanin0(p0) != Aig_ObjFanin0(p1) || Aig_ObjFanin1(p0) != Aig_ObjFanin1(p1) )
return 0;
if ( Aig_ObjFaninC0(p0) == Aig_ObjFaninC0(p1) || Aig_ObjFaninC1(p0) == Aig_ObjFaninC1(p1) )
return 0;
*ppFan0 = Aig_ObjChild0(p0);
*ppFan1 = Aig_ObjChild1(p0);
return 1;
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Performs one retiming step forward.]
Description [Returns the pointer to the register output after retiming.]
SideEffects [Remember to run Aig_ManSetCioIds() in advance.]
SeeAlso []
***********************************************************************/
Aig_Obj_t * Saig_ManRetimeNodeFwd( Aig_Man_t * p, Aig_Obj_t * pObj, int fMakeBug )
{
Aig_Obj_t * pFanin0, * pFanin1;
Aig_Obj_t * pInput0, * pInput1;
Aig_Obj_t * pObjNew, * pObjLi, * pObjLo;
int fCompl;
assert( Saig_ManRegNum(p) > 0 );
assert( Aig_ObjIsNode(pObj) );
// get the fanins
pFanin0 = Aig_ObjFanin0(pObj);
pFanin1 = Aig_ObjFanin1(pObj);
// skip of they are not primary inputs
if ( !Aig_ObjIsCi(pFanin0) || !Aig_ObjIsCi(pFanin1) )
return NULL;
// skip of they are not register outputs
if ( !Saig_ObjIsLo(p, pFanin0) || !Saig_ObjIsLo(p, pFanin1) )
return NULL;
assert( Aig_ObjCioId(pFanin0) > 0 );
assert( Aig_ObjCioId(pFanin1) > 0 );
// skip latch guns
if ( !Aig_ObjIsTravIdCurrent(p, pFanin0) && !Aig_ObjIsTravIdCurrent(p, pFanin1) )
return NULL;
// get the inputs of these registers
pInput0 = Saig_ManLi( p, Aig_ObjCioId(pFanin0) - Saig_ManPiNum(p) );
pInput1 = Saig_ManLi( p, Aig_ObjCioId(pFanin1) - Saig_ManPiNum(p) );
pInput0 = Aig_ObjChild0( pInput0 );
pInput1 = Aig_ObjChild0( pInput1 );
pInput0 = Aig_NotCond( pInput0, Aig_ObjFaninC0(pObj) );
pInput1 = Aig_NotCond( pInput1, Aig_ObjFaninC1(pObj) );
// get the condition when the register should be complemetned
fCompl = Aig_ObjFaninC0(pObj) && Aig_ObjFaninC1(pObj);
if ( fMakeBug )
{
printf( "Introducing bug during retiming.\n" );
pInput1 = Aig_Not( pInput1 );
}
// create new node
pObjNew = Aig_And( p, pInput0, pInput1 );
// create new register input
pObjLi = Aig_ObjCreateCo( p, Aig_NotCond(pObjNew, fCompl) );
pObjLi->CioId = Aig_ManCoNum(p) - 1;
// create new register output
pObjLo = Aig_ObjCreateCi( p );
pObjLo->CioId = Aig_ManCiNum(p) - 1;
p->nRegs++;
// make sure the register is retimable.
Aig_ObjSetTravIdCurrent(p, pObjLo);
//printf( "Reg = %4d. Reg = %4d. Compl = %d. Phase = %d.\n",
// pFanin0->PioNum, pFanin1->PioNum, Aig_IsComplement(pObjNew), fCompl );
// return register output
return Aig_NotCond( pObjLo, fCompl );
}
/**Function*************************************************************
Synopsis [Interplates while the number of conflicts is not exceeded.]
Description [Returns 1 if proven. 0 if failed. -1 if undecided.]
SideEffects [Does not check the property in 0-th frame.]
SeeAlso []
***********************************************************************/
int Inter_ManPerformInterpolation( Aig_Man_t * pAig, Inter_ManParams_t * pPars, int * piFrame )
{
extern int Inter_ManCheckInductiveContainment( Aig_Man_t * pTrans, Aig_Man_t * pInter, int nSteps, int fBackward );
Inter_Man_t * p;
Inter_Check_t * pCheck = NULL;
Aig_Man_t * pAigTemp;
int s, i, RetValue, Status;
abctime clk, clk2, clkTotal = Abc_Clock(), timeTemp = 0;
abctime nTimeNewOut = pPars->nSecLimit ? pPars->nSecLimit * CLOCKS_PER_SEC + Abc_Clock() : 0;
// enable ORing of the interpolants, if containment check is performed inductively with K > 1
if ( pPars->nFramesK > 1 )
pPars->fTransLoop = 1;
// sanity checks
assert( Saig_ManRegNum(pAig) > 0 );
assert( Saig_ManPiNum(pAig) > 0 );
assert( Saig_ManPoNum(pAig)-Saig_ManConstrNum(pAig) == 1 );
if ( pPars->fVerbose && Saig_ManConstrNum(pAig) )
printf( "Performing interpolation with %d constraints...\n", Saig_ManConstrNum(pAig) );
if ( Inter_ManCheckInitialState(pAig) )
{
*piFrame = -1;
printf( "Property trivially fails in the initial state.\n" );
return 0;
}
/*
if ( Inter_ManCheckAllStates(pAig) )
{
printf( "Property trivially holds in all states.\n" );
return 1;
}
*/
// create interpolation manager
// can perform SAT sweeping and/or rewriting of this AIG...
p = Inter_ManCreate( pAig, pPars );
if ( pPars->fTransLoop )
p->pAigTrans = Inter_ManStartOneOutput( pAig, 0 );
else
p->pAigTrans = Inter_ManStartDuplicated( pAig );
// derive CNF for the transformed AIG
clk = Abc_Clock();
p->pCnfAig = Cnf_Derive( p->pAigTrans, Aig_ManRegNum(p->pAigTrans) );
p->timeCnf += Abc_Clock() - clk;
if ( pPars->fVerbose )
{
printf( "AIG: PI/PO/Reg = %d/%d/%d. And = %d. Lev = %d. CNF: Var/Cla = %d/%d.\n",
Saig_ManPiNum(pAig), Saig_ManPoNum(pAig), Saig_ManRegNum(pAig),
Aig_ManAndNum(pAig), Aig_ManLevelNum(pAig),
p->pCnfAig->nVars, p->pCnfAig->nClauses );
}
// derive interpolant
*piFrame = -1;
p->nFrames = 1;
for ( s = 0; ; s++ )
{
Cnf_Dat_t * pCnfInter2;
clk2 = Abc_Clock();
// initial state
if ( pPars->fUseBackward )
p->pInter = Inter_ManStartOneOutput( pAig, 1 );
else
p->pInter = Inter_ManStartInitState( Aig_ManRegNum(pAig) );
assert( Aig_ManCoNum(p->pInter) == 1 );
clk = Abc_Clock();
p->pCnfInter = Cnf_Derive( p->pInter, 0 );
p->timeCnf += Abc_Clock() - clk;
// timeframes
p->pFrames = Inter_ManFramesInter( pAig, p->nFrames, pPars->fUseBackward, pPars->fUseTwoFrames );
clk = Abc_Clock();
if ( pPars->fRewrite )
{
p->pFrames = Dar_ManRwsat( pAigTemp = p->pFrames, 1, 0 );
Aig_ManStop( pAigTemp );
// p->pFrames = Fra_FraigEquivence( pAigTemp = p->pFrames, 100, 0 );
// Aig_ManStop( pAigTemp );
}
p->timeRwr += Abc_Clock() - clk;
// can also do SAT sweeping on the timeframes...
clk = Abc_Clock();
if ( pPars->fUseBackward )
p->pCnfFrames = Cnf_Derive( p->pFrames, Aig_ManCoNum(p->pFrames) );
else
// p->pCnfFrames = Cnf_Derive( p->pFrames, 0 );
p->pCnfFrames = Cnf_DeriveSimple( p->pFrames, 0 );
p->timeCnf += Abc_Clock() - clk;
// report statistics
if ( pPars->fVerbose )
{
printf( "Step = %2d. Frames = 1 + %d. And = %5d. Lev = %5d. ",
s+1, p->nFrames, Aig_ManNodeNum(p->pFrames), Aig_ManLevelNum(p->pFrames) );
ABC_PRT( "Time", Abc_Clock() - clk2 );
}
//////////////////////////////////////////
// start containment checking
if ( !(pPars->fTransLoop || pPars->fUseBackward || pPars->nFramesK > 1) )
{
pCheck = Inter_CheckStart( p->pAigTrans, pPars->nFramesK );
// try new containment check for the initial state
clk = Abc_Clock();
pCnfInter2 = Cnf_Derive( p->pInter, 1 );
p->timeCnf += Abc_Clock() - clk;
clk = Abc_Clock();
RetValue = Inter_CheckPerform( pCheck, pCnfInter2, nTimeNewOut );
p->timeEqu += Abc_Clock() - clk;
// assert( RetValue == 0 );
Cnf_DataFree( pCnfInter2 );
if ( p->vInters )
Vec_PtrPush( p->vInters, Aig_ManDupSimple(p->pInter) );
}
//////////////////////////////////////////
// iterate the interpolation procedure
for ( i = 0; ; i++ )
{
if ( pPars->nFramesMax && p->nFrames + i >= pPars->nFramesMax )
{
if ( pPars->fVerbose )
printf( "Reached limit (%d) on the number of timeframes.\n", pPars->nFramesMax );
p->timeTotal = Abc_Clock() - clkTotal;
Inter_ManStop( p, 0 );
Inter_CheckStop( pCheck );
return -1;
}
// perform interpolation
clk = Abc_Clock();
#ifdef ABC_USE_LIBRARIES
if ( pPars->fUseMiniSat )
{
assert( !pPars->fUseBackward );
RetValue = Inter_ManPerformOneStepM114p( p, pPars->fUsePudlak, pPars->fUseOther );
}
else
#endif
RetValue = Inter_ManPerformOneStep( p, pPars->fUseBias, pPars->fUseBackward, nTimeNewOut );
if ( pPars->fVerbose )
{
printf( " I = %2d. Bmc =%3d. IntAnd =%6d. IntLev =%5d. Conf =%6d. ",
i+1, i + 1 + p->nFrames, Aig_ManNodeNum(p->pInter), Aig_ManLevelNum(p->pInter), p->nConfCur );
ABC_PRT( "Time", Abc_Clock() - clk );
}
// remember the number of timeframes completed
pPars->iFrameMax = i - 1 + p->nFrames;
if ( RetValue == 0 ) // found a (spurious?) counter-example
{
if ( i == 0 ) // real counterexample
{
if ( pPars->fVerbose )
printf( "Found a real counterexample in frame %d.\n", p->nFrames );
p->timeTotal = Abc_Clock() - clkTotal;
*piFrame = p->nFrames;
// pAig->pSeqModel = (Abc_Cex_t *)Inter_ManGetCounterExample( pAig, p->nFrames+1, pPars->fVerbose );
{
int RetValue;
Saig_ParBmc_t ParsBmc, * pParsBmc = &ParsBmc;
Saig_ParBmcSetDefaultParams( pParsBmc );
pParsBmc->nConfLimit = 100000000;
pParsBmc->nStart = p->nFrames;
pParsBmc->fVerbose = pPars->fVerbose;
RetValue = Saig_ManBmcScalable( pAig, pParsBmc );
if ( RetValue == 1 )
printf( "Error: The problem should be SAT but it is UNSAT.\n" );
else if ( RetValue == -1 )
printf( "Error: The problem timed out.\n" );
}
Inter_ManStop( p, 0 );
Inter_CheckStop( pCheck );
return 0;
}
// likely spurious counter-example
p->nFrames += i;
Inter_ManClean( p );
break;
}
else if ( RetValue == -1 )
{
if ( pPars->nSecLimit && Abc_Clock() > nTimeNewOut ) // timed out
{
if ( pPars->fVerbose )
printf( "Reached timeout (%d seconds).\n", pPars->nSecLimit );
}
else
{
assert( p->nConfCur >= p->nConfLimit );
if ( pPars->fVerbose )
printf( "Reached limit (%d) on the number of conflicts.\n", p->nConfLimit );
}
p->timeTotal = Abc_Clock() - clkTotal;
Inter_ManStop( p, 0 );
Inter_CheckStop( pCheck );
return -1;
}
assert( RetValue == 1 ); // found new interpolant
// compress the interpolant
clk = Abc_Clock();
if ( p->pInterNew )
{
// save the timeout value
p->pInterNew->Time2Quit = nTimeNewOut;
// Ioa_WriteAiger( p->pInterNew, "interpol.aig", 0, 0 );
p->pInterNew = Dar_ManRwsat( pAigTemp = p->pInterNew, 1, 0 );
// p->pInterNew = Dar_ManRwsat( pAigTemp = p->pInterNew, 0, 0 );
Aig_ManStop( pAigTemp );
if ( p->pInterNew == NULL )
{
printf( "Reached timeout (%d seconds) during rewriting.\n", pPars->nSecLimit );
p->timeTotal = Abc_Clock() - clkTotal;
Inter_ManStop( p, 1 );
Inter_CheckStop( pCheck );
return -1;
}
}
p->timeRwr += Abc_Clock() - clk;
// check if interpolant is trivial
if ( p->pInterNew == NULL || Aig_ObjChild0(Aig_ManCo(p->pInterNew,0)) == Aig_ManConst0(p->pInterNew) )
{
// printf( "interpolant is constant 0\n" );
if ( pPars->fVerbose )
printf( "The problem is trivially true for all states.\n" );
p->timeTotal = Abc_Clock() - clkTotal;
Inter_ManStop( p, 1 );
Inter_CheckStop( pCheck );
return 1;
}
// check containment of interpolants
clk = Abc_Clock();
if ( pPars->fCheckKstep ) // k-step unique-state induction
{
if ( Aig_ManCiNum(p->pInterNew) == Aig_ManCiNum(p->pInter) )
{
if ( pPars->fTransLoop || pPars->fUseBackward || pPars->nFramesK > 1 )
{
clk2 = Abc_Clock();
Status = Inter_ManCheckInductiveContainment( p->pAigTrans, p->pInterNew, Abc_MinInt(i + 1, pPars->nFramesK), pPars->fUseBackward );
timeTemp = Abc_Clock() - clk2;
}
else
{ // new containment check
clk2 = Abc_Clock();
pCnfInter2 = Cnf_Derive( p->pInterNew, 1 );
p->timeCnf += Abc_Clock() - clk2;
timeTemp = Abc_Clock() - clk2;
Status = Inter_CheckPerform( pCheck, pCnfInter2, nTimeNewOut );
Cnf_DataFree( pCnfInter2 );
if ( p->vInters )
Vec_PtrPush( p->vInters, Aig_ManDupSimple(p->pInterNew) );
}
}
else
Status = 0;
}
else // combinational containment
{
if ( Aig_ManCiNum(p->pInterNew) == Aig_ManCiNum(p->pInter) )
Status = Inter_ManCheckContainment( p->pInterNew, p->pInter );
else
Status = 0;
}
p->timeEqu += Abc_Clock() - clk - timeTemp;
if ( Status ) // contained
{
if ( pPars->fVerbose )
printf( "Proved containment of interpolants.\n" );
p->timeTotal = Abc_Clock() - clkTotal;
Inter_ManStop( p, 1 );
Inter_CheckStop( pCheck );
return 1;
}
if ( pPars->nSecLimit && Abc_Clock() > nTimeNewOut )
{
printf( "Reached timeout (%d seconds).\n", pPars->nSecLimit );
p->timeTotal = Abc_Clock() - clkTotal;
Inter_ManStop( p, 1 );
Inter_CheckStop( pCheck );
return -1;
}
// save interpolant and convert it into CNF
if ( pPars->fTransLoop )
{
Aig_ManStop( p->pInter );
p->pInter = p->pInterNew;
}
else
{
if ( pPars->fUseBackward )
{
p->pInter = Aig_ManCreateMiter( pAigTemp = p->pInter, p->pInterNew, 2 );
Aig_ManStop( pAigTemp );
Aig_ManStop( p->pInterNew );
// compress the interpolant
clk = Abc_Clock();
p->pInter = Dar_ManRwsat( pAigTemp = p->pInter, 1, 0 );
Aig_ManStop( pAigTemp );
p->timeRwr += Abc_Clock() - clk;
}
else // forward with the new containment checking (using only the frontier)
{
Aig_ManStop( p->pInter );
p->pInter = p->pInterNew;
}
}
p->pInterNew = NULL;
Cnf_DataFree( p->pCnfInter );
clk = Abc_Clock();
p->pCnfInter = Cnf_Derive( p->pInter, 0 );
p->timeCnf += Abc_Clock() - clk;
}
// start containment checking
Inter_CheckStop( pCheck );
}
assert( 0 );
return RetValue;
}
/**Function*************************************************************
Synopsis [Performs canonicization step.]
Description [The argument nodes can be complemented.]
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_And( Aig_Man_t * p, Aig_Obj_t * p0, Aig_Obj_t * p1 )
{
Aig_Obj_t * pGhost, * pResult;
// Aig_Obj_t * pFan0, * pFan1;
// check trivial cases
if ( p0 == p1 )
return p0;
if ( p0 == Aig_Not(p1) )
return Aig_Not(p->pConst1);
if ( Aig_Regular(p0) == p->pConst1 )
return p0 == p->pConst1 ? p1 : Aig_Not(p->pConst1);
if ( Aig_Regular(p1) == p->pConst1 )
return p1 == p->pConst1 ? p0 : Aig_Not(p->pConst1);
// check not so trivial cases
if ( p->fAddStrash && (Aig_ObjIsNode(Aig_Regular(p0)) || Aig_ObjIsNode(Aig_Regular(p1))) )
{ // http://fmv.jku.at/papers/BrummayerBiere-MEMICS06.pdf
Aig_Obj_t * pFanA, * pFanB, * pFanC, * pFanD;
pFanA = Aig_ObjChild0(Aig_Regular(p0));
pFanB = Aig_ObjChild1(Aig_Regular(p0));
pFanC = Aig_ObjChild0(Aig_Regular(p1));
pFanD = Aig_ObjChild1(Aig_Regular(p1));
if ( Aig_IsComplement(p0) )
{
if ( pFanA == Aig_Not(p1) || pFanB == Aig_Not(p1) )
return p1;
if ( pFanB == p1 )
return Aig_And( p, Aig_Not(pFanA), pFanB );
if ( pFanA == p1 )
return Aig_And( p, Aig_Not(pFanB), pFanA );
}
else
{
if ( pFanA == Aig_Not(p1) || pFanB == Aig_Not(p1) )
return Aig_Not(p->pConst1);
if ( pFanA == p1 || pFanB == p1 )
return p0;
}
if ( Aig_IsComplement(p1) )
{
if ( pFanC == Aig_Not(p0) || pFanD == Aig_Not(p0) )
return p0;
if ( pFanD == p0 )
return Aig_And( p, Aig_Not(pFanC), pFanD );
if ( pFanC == p0 )
return Aig_And( p, Aig_Not(pFanD), pFanC );
}
else
{
if ( pFanC == Aig_Not(p0) || pFanD == Aig_Not(p0) )
return Aig_Not(p->pConst1);
if ( pFanC == p0 || pFanD == p0 )
return p1;
}
if ( !Aig_IsComplement(p0) && !Aig_IsComplement(p1) )
{
if ( pFanA == Aig_Not(pFanC) || pFanA == Aig_Not(pFanD) || pFanB == Aig_Not(pFanC) || pFanB == Aig_Not(pFanD) )
return Aig_Not(p->pConst1);
if ( pFanA == pFanC || pFanB == pFanC )
return Aig_And( p, p0, pFanD );
if ( pFanB == pFanC || pFanB == pFanD )
return Aig_And( p, pFanA, p1 );
if ( pFanA == pFanD || pFanB == pFanD )
return Aig_And( p, p0, pFanC );
if ( pFanA == pFanC || pFanA == pFanD )
return Aig_And( p, pFanB, p1 );
}
else if ( Aig_IsComplement(p0) && !Aig_IsComplement(p1) )
{
if ( pFanA == Aig_Not(pFanC) || pFanA == Aig_Not(pFanD) || pFanB == Aig_Not(pFanC) || pFanB == Aig_Not(pFanD) )
return p1;
if ( pFanB == pFanC || pFanB == pFanD )
return Aig_And( p, Aig_Not(pFanA), p1 );
if ( pFanA == pFanC || pFanA == pFanD )
return Aig_And( p, Aig_Not(pFanB), p1 );
}
else if ( !Aig_IsComplement(p0) && Aig_IsComplement(p1) )
{
if ( pFanC == Aig_Not(pFanA) || pFanC == Aig_Not(pFanB) || pFanD == Aig_Not(pFanA) || pFanD == Aig_Not(pFanB) )
return p0;
if ( pFanD == pFanA || pFanD == pFanB )
return Aig_And( p, Aig_Not(pFanC), p0 );
if ( pFanC == pFanA || pFanC == pFanB )
return Aig_And( p, Aig_Not(pFanD), p0 );
}
else // if ( Aig_IsComplement(p0) && Aig_IsComplement(p1) )
{
if ( pFanA == pFanD && pFanB == Aig_Not(pFanC) )
return Aig_Not(pFanA);
if ( pFanB == pFanC && pFanA == Aig_Not(pFanD) )
return Aig_Not(pFanB);
if ( pFanA == pFanC && pFanB == Aig_Not(pFanD) )
return Aig_Not(pFanA);
if ( pFanB == pFanD && pFanA == Aig_Not(pFanC) )
return Aig_Not(pFanB);
}
}
// check if it can be an EXOR gate
// if ( Aig_ObjIsExorType( p0, p1, &pFan0, &pFan1 ) )
// return Aig_Exor( p, pFan0, pFan1 );
pGhost = Aig_ObjCreateGhost( p, p0, p1, AIG_OBJ_AND );
pResult = Aig_CanonPair_rec( p, pGhost );
return pResult;
}
ABC_NAMESPACE_IMPL_START
/*
Property holds iff it is const 0.
Constraint holds iff it is const 0.
The following structure is used for folding constraints:
- the output of OR gate is 0 as long as all constraints hold
- as soon as one constraint fail, the property output becomes 0 forever
because the flop becomes 1 and it stays 1 forever
property output
|
|-----|
| and |
|-----|
| |
| / \
| /inv\
| -----
____| |_________________________
| | |
/ \ ----------- |
/ \ | or | |
/ \ ----------- |
/ logic \ | | | |
/ cone \ | | | |
/___________\ | | | |
| | ------ |
| | |flop| (init=0) |
| | ------ |
| | | |
| | |______________|
| |
c1 c2
*/
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Collects the supergate.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Saig_DetectConstrCollectSuper_rec( Aig_Obj_t * pObj, Vec_Ptr_t * vSuper )
{
// if the new node is complemented or a PI, another gate begins
if ( Aig_IsComplement(pObj) || !Aig_ObjIsNode(pObj) )//|| (Aig_ObjRefs(pObj) > 1) )
{
Vec_PtrPushUnique( vSuper, Aig_Not(pObj) );
return;
}
// go through the branches
Saig_DetectConstrCollectSuper_rec( Aig_ObjChild0(pObj), vSuper );
Saig_DetectConstrCollectSuper_rec( Aig_ObjChild1(pObj), vSuper );
}
/**Function*************************************************************
Synopsis [Detects constraints using structural methods.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Saig_ManDetectConstr( Aig_Man_t * p, int iOut, Vec_Ptr_t ** pvOuts, Vec_Ptr_t ** pvCons )
{
Vec_Ptr_t * vSuper, * vSuper2 = NULL, * vUnique;
Aig_Obj_t * pObj, * pObj2, * pFlop;
int i, nFlops, RetValue;
assert( iOut >= 0 && iOut < Saig_ManPoNum(p) );
*pvOuts = NULL;
*pvCons = NULL;
pObj = Aig_ObjChild0( Aig_ManCo(p, iOut) );
if ( Aig_IsComplement(pObj) || !Aig_ObjIsNode(pObj) )
{
printf( "The output is not an AND.\n" );
return 0;
}
vSuper = Saig_DetectConstrCollectSuper( pObj );
assert( Vec_PtrSize(vSuper) >= 2 );
nFlops = 0;
Vec_PtrForEachEntry( Aig_Obj_t *, vSuper, pObj, i )
nFlops += Saig_ObjIsLo( p, Aig_Regular(pObj) );
if ( nFlops == 0 )
{
printf( "There is no flop outputs.\n" );
Vec_PtrFree( vSuper );
return 0;
}
// try flops
vUnique = NULL;
Vec_PtrForEachEntry( Aig_Obj_t *, vSuper, pObj, i )
{
pFlop = Aig_Regular( pObj );
if ( !Saig_ObjIsLo(p, pFlop) )
continue;
pFlop = Saig_ObjLoToLi( p, pFlop );
pObj2 = Aig_ObjChild0( pFlop );
if ( !Aig_IsComplement(pObj2) || !Aig_ObjIsNode(Aig_Regular(pObj2)) )
continue;
vSuper2 = Saig_DetectConstrCollectSuper( Aig_Regular(pObj2) );
// every node in vSuper2 should appear in vSuper
vUnique = Saig_ManDetectConstrCheckCont( vSuper, vSuper2 );
if ( vUnique != NULL )
{
/// assert( !Aig_IsComplement(pObj) );
// assert( Vec_PtrFind( vSuper2, pObj ) >= 0 );
if ( Aig_IsComplement(pObj) )
{
printf( "Special flop input is complemented.\n" );
Vec_PtrFreeP( &vUnique );
Vec_PtrFree( vSuper2 );
break;
}
if ( Vec_PtrFind( vSuper2, pObj ) == -1 )
{
printf( "Cannot find special flop about the inputs of OR gate.\n" );
Vec_PtrFreeP( &vUnique );
Vec_PtrFree( vSuper2 );
break;
}
// remove the flop output
Vec_PtrRemove( vSuper2, pObj );
break;
}
Vec_PtrFree( vSuper2 );
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
/*
Speculating reduction in the sequential case leads to an interesting
situation when a counter-ex may not refine any classes. This happens
for non-constant equivalence classes. In such cases the representative
of the class (proved by simulation to be non-constant) may be reduced
to a constant during the speculative reduction. The fraig-representative
of this representative node is a constant node, even though this is a
non-constant class. Experiments have shown that this situation happens
very often at the beginning of the refinement iteration when there are
many spurious candidate equivalence classes (especially if heavy-duty
simulatation of BMC was node used at the beginning). As a result, the
SAT solver run may return a counter-ex that distinguishes the given
representative node from the constant-1 node but this counter-ex
does not distinguish the nodes in the non-costant class... This is why
there is no check of refinement after a counter-ex in the sequential case.
*/
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Reports the status of the miter.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Fra_FraigMiterStatus( Aig_Man_t * p )
{
Aig_Obj_t * pObj, * pChild;
int i, CountConst0 = 0, CountNonConst0 = 0, CountUndecided = 0;
if ( p->pData )
return 0;
Aig_ManForEachPoSeq( p, pObj, i )
{
pChild = Aig_ObjChild0(pObj);
// check if the output is constant 0
if ( pChild == Aig_ManConst0(p) )
{
CountConst0++;
continue;
}
// check if the output is constant 1
if ( pChild == Aig_ManConst1(p) )
{
CountNonConst0++;
continue;
}
// check if the output is a primary input
if ( p->nRegs == 0 && Aig_ObjIsPi(Aig_Regular(pChild)) )
{
CountNonConst0++;
continue;
}
// check if the output can be not constant 0
if ( Aig_Regular(pChild)->fPhase != (unsigned)Aig_IsComplement(pChild) )
{
CountNonConst0++;
continue;
}
CountUndecided++;
}
