/**Function*************************************************************
Synopsis [Duplicates AIG in the DFS order.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Gia_Man_t * Gia_ManFromAigSimple( Aig_Man_t * p )
{
Gia_Man_t * pNew;
Aig_Obj_t * pObj;
int i;
// create the new manager
pNew = Gia_ManStart( Aig_ManObjNum(p) );
pNew->pName = Gia_UtilStrsav( p->pName );
pNew->nConstrs = p->nConstrs;
// create the PIs
Aig_ManCleanData( p );
Aig_ManForEachObj( p, pObj, i )
{
if ( Aig_ObjIsAnd(pObj) )
pObj->iData = Gia_ManAppendAnd( pNew, Gia_ObjChild0Copy(pObj), Gia_ObjChild1Copy(pObj) );
else if ( Aig_ObjIsPi(pObj) )
pObj->iData = Gia_ManAppendCi( pNew );
else if ( Aig_ObjIsPo(pObj) )
pObj->iData = Gia_ManAppendCo( pNew, Gia_ObjChild0Copy(pObj) );
else if ( Aig_ObjIsConst1(pObj) )
pObj->iData = 1;
else
assert( 0 );
}
Gia_ManSetRegNum( pNew, Aig_ManRegNum(p) );
return pNew;
}
/**Function*************************************************************
Synopsis [Returns the number of LIs with binary ternary info.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Saig_ManBmcTerSimCount01( Aig_Man_t * p, unsigned * pInfo )
{
Aig_Obj_t * pObj;
int i, Counter = 0;
if ( pInfo == NULL )
return Saig_ManRegNum(p);
Saig_ManForEachLi( p, pObj, i )
if ( !Aig_ObjIsConst1(Aig_ObjFanin0(pObj)) )
Counter += (Saig_ManBmcSimInfoGet(pInfo, pObj) != SAIG_TER_UND);
return Counter;
}
/**Function*************************************************************
Synopsis [Returns 1 if the cone of the node overlaps with the vector.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Obj_t * Aig_ManDeriveNewCone( Aig_Man_t * p, Vec_Ptr_t * vImplics, Aig_Obj_t * pNode )
{
Aig_Obj_t * pTemp;
int i;
assert( !Aig_IsComplement(pNode) );
assert( !Aig_ObjIsConst1(pNode) );
Aig_ManIncrementTravId( p );
Vec_PtrForEachEntry( Aig_Obj_t *, vImplics, pTemp, i )
{
Aig_ObjSetTravIdCurrent( p, Aig_Regular(pTemp) );
Aig_Regular(pTemp)->pData = Aig_NotCond( Aig_ManConst1(p), Aig_IsComplement(pTemp) );
}
/**Function*************************************************************
Synopsis [Returns 1 if the cone of the node overlaps with the vector.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Aig_ManFindConeOverlap( Aig_Man_t * p, Vec_Ptr_t * vImplics, Aig_Obj_t * pNode )
{
Aig_Obj_t * pTemp;
int i;
assert( !Aig_IsComplement(pNode) );
assert( !Aig_ObjIsConst1(pNode) );
Aig_ManIncrementTravId( p );
Vec_PtrForEachEntry( Aig_Obj_t *, vImplics, pTemp, i )
Aig_ObjSetTravIdCurrent( p, Aig_Regular(pTemp) );
Aig_ManIncrementTravId( p );
return Aig_ManFindConeOverlap_rec( p, pNode );
}
/**Function*************************************************************
Synopsis [Sets variable activities in the cone.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Fra_SetActivityFactors( Fra_Man_t * p, Aig_Obj_t * pOld, Aig_Obj_t * pNew )
{
int clk, LevelMin, LevelMax;
assert( pOld || pNew );
clk = clock();
// reset the active variables
veci_resize(&p->pSat->act_vars, 0);
// prepare for traversal
Aig_ManIncrementTravId( p->pManFraig );
// determine the min and max level to visit
assert( p->pPars->dActConeRatio > 0 && p->pPars->dActConeRatio < 1 );
LevelMax = AIG_MAX( (pNew ? pNew->Level : 0), (pOld ? pOld->Level : 0) );
LevelMin = (int)(LevelMax * (1.0 - p->pPars->dActConeRatio));
// traverse
if ( pOld && !Aig_ObjIsConst1(pOld) )
Fra_SetActivityFactors_rec( p, pOld, LevelMin, LevelMax );
if ( pNew && !Aig_ObjIsConst1(pNew) )
Fra_SetActivityFactors_rec( p, pNew, LevelMin, LevelMax );
//Fra_PrintActivity( p );
p->timeTrav += clock() - clk;
return 1;
}
/**Function*************************************************************
Synopsis [Returns affective support size.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Aig_BaseSize( Aig_Man_t * p, Aig_Obj_t * pObj, int nLutSize )
{
int nBaseSize;
pObj = Aig_Regular(pObj);
if ( Aig_ObjIsConst1(pObj) )
return 0;
if ( Aig_ObjLevel(pObj) >= nLutSize )
return 1;
nBaseSize = Aig_SupportSize( p, pObj );
if ( nBaseSize >= nLutSize )
return 1;
return nBaseSize;
}
/**Function*************************************************************
Synopsis [Deletes the MFFC of the node.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Aig_ObjDelete_rec( Aig_Man_t * p, Aig_Obj_t * pObj, int fFreeTop )
{
Aig_Obj_t * pFanin0, * pFanin1;
assert( !Aig_IsComplement(pObj) );
if ( Aig_ObjIsConst1(pObj) || Aig_ObjIsPi(pObj) )
return;
assert( !Aig_ObjIsPo(pObj) );
pFanin0 = Aig_ObjFanin0(pObj);
pFanin1 = Aig_ObjFanin1(pObj);
Aig_ObjDisconnect( p, pObj );
if ( fFreeTop )
Aig_ObjDelete( p, pObj );
if ( pFanin0 && !Aig_ObjIsNone(pFanin0) && Aig_ObjRefs(pFanin0) == 0 )
Aig_ObjDelete_rec( p, pFanin0, 1 );
if ( pFanin1 && !Aig_ObjIsNone(pFanin1) && Aig_ObjRefs(pFanin1) == 0 )
Aig_ObjDelete_rec( p, pFanin1, 1 );
}
/**Function*************************************************************
Synopsis [Converts AIG from Aig_Man_t into Hop_Obj_t.]
Description [Assumes that Aig_Man_t has exactly one primary outputs.
Returns the pointer to the root node (Hop_Obj_t) in Hop_Man_t.]
SideEffects []
SeeAlso []
***********************************************************************/
Hop_Obj_t * Abc_MfsConvertAigToHop( Aig_Man_t * pMan, Hop_Man_t * pHop )
{
Aig_Obj_t * pRoot, * pObj;
int i;
assert( Aig_ManPoNum(pMan) == 1 );
pRoot = Aig_ManPo( pMan, 0 );
// check the case of a constant
if ( Aig_ObjIsConst1( Aig_ObjFanin0(pRoot) ) )
return Hop_NotCond( Hop_ManConst1(pHop), Aig_ObjFaninC0(pRoot) );
// set the PI mapping
Aig_ManCleanData( pMan );
Aig_ManForEachPi( pMan, pObj, i )
pObj->pData = Hop_IthVar( pHop, i );
// construct the AIG
Abc_MfsConvertAigToHop_rec( Aig_ObjFanin0(pRoot), pHop );
return Hop_NotCond( (Hop_Obj_t *)Aig_ObjFanin0(pRoot)->pData, Aig_ObjFaninC0(pRoot) );
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Computes area, references, and nodes used in the mapping.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Aig_ManScanMapping_rec( Cnf_Man_t * p, Aig_Obj_t * pObj, Vec_Ptr_t * vMapped )
{
Aig_Obj_t * pLeaf;
Dar_Cut_t * pCutBest;
int aArea, i;
if ( pObj->nRefs++ || Aig_ObjIsCi(pObj) || Aig_ObjIsConst1(pObj) )
return 0;
assert( Aig_ObjIsAnd(pObj) );
// collect the node first to derive pre-order
if ( vMapped )
Vec_PtrPush( vMapped, pObj );
// visit the transitive fanin of the selected cut
if ( pObj->fMarkB )
{
Vec_Ptr_t * vSuper = Vec_PtrAlloc( 100 );
Aig_ObjCollectSuper( pObj, vSuper );
aArea = Vec_PtrSize(vSuper) + 1;
Vec_PtrForEachEntry( Aig_Obj_t *, vSuper, pLeaf, i )
aArea += Aig_ManScanMapping_rec( p, Aig_Regular(pLeaf), vMapped );
Vec_PtrFree( vSuper );
////////////////////////////
pObj->fMarkB = 1;
}
/**Function*************************************************************
Synopsis [Replaces the first fanin of the node by the new fanin.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Aig_ObjPatchFanin0( Aig_Man_t * p, Aig_Obj_t * pObj, Aig_Obj_t * pFaninNew )
{
Aig_Obj_t * pFaninOld;
assert( !Aig_IsComplement(pObj) );
assert( Aig_ObjIsPo(pObj) );
pFaninOld = Aig_ObjFanin0(pObj);
// decrement ref and remove fanout
if ( p->pFanData )
Aig_ObjRemoveFanout( p, pFaninOld, pObj );
Aig_ObjDeref( pFaninOld );
// update the fanin
pObj->pFanin0 = pFaninNew;
// increment ref and add fanout
if ( p->pFanData )
Aig_ObjAddFanout( p, Aig_ObjFanin0(pObj), pObj );
Aig_ObjRef( Aig_ObjFanin0(pObj) );
// get rid of old fanin
if ( !Aig_ObjIsPi(pFaninOld) && !Aig_ObjIsConst1(pFaninOld) && Aig_ObjRefs(pFaninOld) == 0 )
Aig_ObjDelete_rec( p, pFaninOld, 1 );
}
/**Function*************************************************************
Synopsis [Drive implications of the given node towards primary outputs.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Saig_ManSetAndDriveImplications_rec( Aig_Man_t * p, Aig_Obj_t * pObj, int f, int fMax, Vec_Ptr_t * vSimInfo )
{
Aig_Obj_t * pFanout;
int k, iFanout = -1, Value0, Value1;
int Value = Saig_ManSimInfo2Get( vSimInfo, pObj, f );
assert( !Saig_ManSimInfo2IsOld( Value ) );
Saig_ManSimInfo2Set( vSimInfo, pObj, f, Saig_ManSimInfo2SetOld(Value) );
if ( (Aig_ObjIsCo(pObj) && f == fMax) || Saig_ObjIsPo(p, pObj) )
return;
if ( Saig_ObjIsLi( p, pObj ) )
{
assert( f < fMax );
pFanout = Saig_ObjLiToLo(p, pObj);
Value = Saig_ManSimInfo2Get( vSimInfo, pFanout, f+1 );
if ( !Saig_ManSimInfo2IsOld( Value ) )
Saig_ManSetAndDriveImplications_rec( p, pFanout, f+1, fMax, vSimInfo );
return;
}
assert( Aig_ObjIsCi(pObj) || Aig_ObjIsNode(pObj) || Aig_ObjIsConst1(pObj) );
Aig_ObjForEachFanout( p, pObj, pFanout, iFanout, k )
{
Value = Saig_ManSimInfo2Get( vSimInfo, pFanout, f );
if ( Saig_ManSimInfo2IsOld( Value ) )
continue;
if ( Aig_ObjIsCo(pFanout) )
{
Saig_ManSetAndDriveImplications_rec( p, pFanout, f, fMax, vSimInfo );
continue;
}
assert( Aig_ObjIsNode(pFanout) );
Value0 = Saig_ManSimInfo2Get( vSimInfo, Aig_ObjFanin0(pFanout), f );
Value1 = Saig_ManSimInfo2Get( vSimInfo, Aig_ObjFanin1(pFanout), f );
if ( Aig_ObjFaninC0(pFanout) )
Value0 = Saig_ManSimInfo2Not( Value0 );
if ( Aig_ObjFaninC1(pFanout) )
Value1 = Saig_ManSimInfo2Not( Value1 );
if ( Value0 == SAIG_ZER_OLD || Value1 == SAIG_ZER_OLD ||
(Value0 == SAIG_ONE_OLD && Value1 == SAIG_ONE_OLD) )
Saig_ManSetAndDriveImplications_rec( p, pFanout, f, fMax, vSimInfo );
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
char * Saig_ObjName( Aig_Man_t * p, Aig_Obj_t * pObj )
{
static char Buffer[16];
if ( Aig_ObjIsNode(pObj) || Aig_ObjIsConst1(pObj) )
sprintf( Buffer, "n%0*d", Aig_Base10Log(Aig_ManObjNumMax(p)), Aig_ObjId(pObj) );
else if ( Saig_ObjIsPi(p, pObj) )
sprintf( Buffer, "pi%0*d", Aig_Base10Log(Saig_ManPiNum(p)), Aig_ObjPioNum(pObj) );
else if ( Saig_ObjIsPo(p, pObj) )
sprintf( Buffer, "po%0*d", Aig_Base10Log(Saig_ManPoNum(p)), Aig_ObjPioNum(pObj) );
else if ( Saig_ObjIsLo(p, pObj) )
sprintf( Buffer, "lo%0*d", Aig_Base10Log(Saig_ManRegNum(p)), Aig_ObjPioNum(pObj) - Saig_ManPiNum(p) );
else if ( Saig_ObjIsLi(p, pObj) )
sprintf( Buffer, "li%0*d", Aig_Base10Log(Saig_ManRegNum(p)), Aig_ObjPioNum(pObj) - Saig_ManPoNum(p) );
else
assert( 0 );
return Buffer;
}
// pNtk->nLatches = Aig_ManRegNum(p);
// pNtk->nTruePis = Nwk_ManCiNum(pNtk) - pNtk->nLatches;
// pNtk->nTruePos = Nwk_ManCoNum(pNtk) - pNtk->nLatches;
Aig_ManForEachObj( p, pObj, i )
{
pIfObj = (If_Obj_t *)Vec_PtrEntry( vAigToIf, i );
if ( pIfObj->nRefs == 0 && !If_ObjIsTerm(pIfObj) )
continue;
if ( Aig_ObjIsNode(pObj) )
{
pCutBest = If_ObjCutBest( pIfObj );
nLeaves = If_CutLeaveNum( pCutBest );
ppLeaves = If_CutLeaves( pCutBest );
// create node
pObjNew = Nwk_ManCreateNode( pNtk, nLeaves, pIfObj->nRefs );
for ( k = 0; k < nLeaves; k++ )
{
pObjRepr = (Aig_Obj_t *)Vec_PtrEntry( vIfToAig, ppLeaves[k] );
Nwk_ObjAddFanin( pObjNew, (Nwk_Obj_t *)pObjRepr->pData );
}
// get the functionality
pObjNew->pFunc = Nwk_NodeIfToHop( pNtk->pManHop, pIfMan, pIfObj );
}
else if ( Aig_ObjIsCi(pObj) )
pObjNew = Nwk_ManCreateCi( pNtk, pIfObj->nRefs );
else if ( Aig_ObjIsCo(pObj) )
{
pObjNew = Nwk_ManCreateCo( pNtk );
pObjNew->fInvert = Aig_ObjFaninC0(pObj);
Nwk_ObjAddFanin( pObjNew, (Nwk_Obj_t *)Aig_ObjFanin0(pObj)->pData );
//printf( "%d ", pObjNew->Id );
}
else if ( Aig_ObjIsConst1(pObj) )
{
pObjNew = Nwk_ManCreateNode( pNtk, 0, pIfObj->nRefs );
pObjNew->pFunc = Hop_ManConst1( pNtk->pManHop );
}
else
assert( 0 );
pObj->pData = pObjNew;
}
/**Function*************************************************************
Synopsis [Load the network into FPGA manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
If_Man_t * Nwk_ManToIf( Aig_Man_t * p, If_Par_t * pPars, Vec_Ptr_t * vAigToIf )
{
extern Vec_Int_t * Saig_ManComputeSwitchProbs( Aig_Man_t * p, int nFrames, int nPref, int fProbOne );
Vec_Int_t * vSwitching = NULL, * vSwitching2 = NULL;
float * pSwitching = NULL, * pSwitching2 = NULL;
If_Man_t * pIfMan;
If_Obj_t * pIfObj;
Aig_Obj_t * pNode, * pFanin, * pPrev;
int i;
abctime clk = Abc_Clock();
// set the number of registers (switch activity will be combinational)
Aig_ManSetRegNum( p, 0 );
if ( pPars->fPower )
{
vSwitching = Saig_ManComputeSwitchProbs( p, 48, 16, 0 );
if ( pPars->fVerbose )
{
ABC_PRT( "Computing switching activity", Abc_Clock() - clk );
}
pSwitching = (float *)vSwitching->pArray;
vSwitching2 = Vec_IntStart( Aig_ManObjNumMax(p) );
pSwitching2 = (float *)vSwitching2->pArray;
}
// start the mapping manager and set its parameters
pIfMan = If_ManStart( pPars );
pIfMan->vSwitching = vSwitching2;
// load the AIG into the mapper
Aig_ManForEachObj( p, pNode, i )
{
if ( Aig_ObjIsAnd(pNode) )
{
pIfObj = If_ManCreateAnd( pIfMan,
If_NotCond( (If_Obj_t *)Aig_ObjFanin0(pNode)->pData, Aig_ObjFaninC0(pNode) ),
If_NotCond( (If_Obj_t *)Aig_ObjFanin1(pNode)->pData, Aig_ObjFaninC1(pNode) ) );
// printf( "no%d=%d\n ", If_ObjId(pIfObj), If_ObjLevel(pIfObj) );
}
else if ( Aig_ObjIsCi(pNode) )
{
pIfObj = If_ManCreateCi( pIfMan );
If_ObjSetLevel( pIfObj, Aig_ObjLevel(pNode) );
// printf( "pi%d=%d\n ", If_ObjId(pIfObj), If_ObjLevel(pIfObj) );
if ( pIfMan->nLevelMax < (int)pIfObj->Level )
pIfMan->nLevelMax = (int)pIfObj->Level;
}
else if ( Aig_ObjIsCo(pNode) )
{
pIfObj = If_ManCreateCo( pIfMan, If_NotCond( (If_Obj_t *)Aig_ObjFanin0(pNode)->pData, Aig_ObjFaninC0(pNode) ) );
// printf( "po%d=%d\n ", If_ObjId(pIfObj), If_ObjLevel(pIfObj) );
}
else if ( Aig_ObjIsConst1(pNode) )
pIfObj = If_ManConst1( pIfMan );
else // add the node to the mapper
assert( 0 );
// save the result
assert( Vec_PtrEntry(vAigToIf, i) == NULL );
Vec_PtrWriteEntry( vAigToIf, i, pIfObj );
pNode->pData = pIfObj;
if ( vSwitching2 )
pSwitching2[pIfObj->Id] = pSwitching[pNode->Id];
// set up the choice node
if ( Aig_ObjIsChoice( p, pNode ) )
{
for ( pPrev = pNode, pFanin = Aig_ObjEquiv(p, pNode); pFanin; pPrev = pFanin, pFanin = Aig_ObjEquiv(p, pFanin) )
If_ObjSetChoice( (If_Obj_t *)pPrev->pData, (If_Obj_t *)pFanin->pData );
If_ManCreateChoice( pIfMan, (If_Obj_t *)pNode->pData );
}
// assert( If_ObjLevel(pIfObj) == Aig_ObjLevel(pNode) );
}
if ( vSwitching )
Vec_IntFree( vSwitching );
return pIfMan;
}
/**Function*************************************************************
Synopsis [Returns array of NS variables.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Int_t * Llb_DriverCollectNs( Aig_Man_t * pAig, Vec_Int_t * vDriRefs )
{
Vec_Int_t * vVars;
Aig_Obj_t * pObj, * pDri;
int i;
vVars = Vec_IntAlloc( Aig_ManRegNum(pAig) );
Saig_ManForEachLi( pAig, pObj, i )
{
pDri = Aig_ObjFanin0(pObj);
if ( Vec_IntEntry( vDriRefs, Aig_ObjId(pDri) ) != 1 || Saig_ObjIsPi(pAig, pDri) || Aig_ObjIsConst1(pDri) )
Vec_IntPush( vVars, Aig_ObjId(pObj) );
else
Vec_IntPush( vVars, Aig_ObjId(pDri) );
}
