/**
Initialize IDT to setup exception handlers for SMM.
**/
VOID
InitializeSmmIdt (
VOID
)
{
EFI_STATUS Status;
BOOLEAN InterruptState;
IA32_DESCRIPTOR DxeIdtr;
//
// Disable Interrupt and save DXE IDT table
//
InterruptState = SaveAndDisableInterrupts ();
AsmReadIdtr (&DxeIdtr);
//
// Load SMM temporary IDT table
//
AsmWriteIdtr (&gcSmiIdtr);
//
// Setup SMM default exception handlers, SMM IDT table
// will be updated and saved in gcSmiIdtr
//
Status = InitializeCpuExceptionHandlers (NULL);
ASSERT_EFI_ERROR (Status);
//
// Restore DXE IDT table and CPU interrupt
//
AsmWriteIdtr ((IA32_DESCRIPTOR *) &DxeIdtr);
SetInterruptState (InterruptState);
}
/**
Initialize IDT to setup exception handlers for SMM.
**/
VOID
InitializeSmmIdt (
VOID
)
{
EFI_STATUS Status;
BOOLEAN InterruptState;
IA32_DESCRIPTOR DxeIdtr;
//
// There are 32 (not 255) entries in it since only processor
// generated exceptions will be handled.
//
gcSmiIdtr.Limit = (sizeof(IA32_IDT_GATE_DESCRIPTOR) * 32) - 1;
//
// Allocate page aligned IDT, because it might be set as read only.
//
gcSmiIdtr.Base = (UINTN)AllocateCodePages (EFI_SIZE_TO_PAGES(gcSmiIdtr.Limit + 1));
ASSERT (gcSmiIdtr.Base != 0);
ZeroMem ((VOID *)gcSmiIdtr.Base, gcSmiIdtr.Limit + 1);
//
// Disable Interrupt and save DXE IDT table
//
InterruptState = SaveAndDisableInterrupts ();
AsmReadIdtr (&DxeIdtr);
//
// Load SMM temporary IDT table
//
AsmWriteIdtr (&gcSmiIdtr);
//
// Setup SMM default exception handlers, SMM IDT table
// will be updated and saved in gcSmiIdtr
//
Status = InitializeCpuExceptionHandlers (NULL);
ASSERT_EFI_ERROR (Status);
//
// Restore DXE IDT table and CPU interrupt
//
AsmWriteIdtr ((IA32_DESCRIPTOR *) &DxeIdtr);
SetInterruptState (InterruptState);
}
/**
C function for SMI handler. To change all processor's SMMBase Register.
**/
VOID
EFIAPI
SmmInitHandler (
VOID
)
{
UINT32 ApicId;
UINTN Index;
//
// Update SMM IDT entries' code segment and load IDT
//
AsmWriteIdtr (&gcSmiIdtr);
ApicId = GetApicId ();
ASSERT (mNumberOfCpus <= mMaxNumberOfCpus);
for (Index = 0; Index < mNumberOfCpus; Index++) {
if (ApicId == (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) {
//
// Initialize SMM specific features on the currently executing CPU
//
SmmCpuFeaturesInitializeProcessor (
Index,
mIsBsp,
gSmmCpuPrivate->ProcessorInfo,
&mCpuHotPlugData
);
if (!mSmmS3Flag) {
//
// Check XD and BTS features on each processor on normal boot
//
CheckFeatureSupported ();
}
if (mIsBsp) {
//
// BSP rebase is already done above.
// Initialize private data during S3 resume
//
InitializeMpSyncData ();
}
//
// Hook return after RSM to set SMM re-based flag
//
SemaphoreHook (Index, &mRebased[Index]);
return;
}
}
ASSERT (FALSE);
}
/**
Jump to OS waking vector.
The function will install boot script done PPI, report S3 resume status code, and then jump to OS waking vector.
@param AcpiS3Context a pointer to a structure of ACPI_S3_CONTEXT
@param PeiS3ResumeState a pointer to a structure of PEI_S3_RESUME_STATE
**/
VOID
EFIAPI
S3ResumeBootOs (
IN ACPI_S3_CONTEXT *AcpiS3Context,
IN PEI_S3_RESUME_STATE *PeiS3ResumeState
)
{
EFI_STATUS Status;
EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *Facs;
ASM_TRANSFER_CONTROL AsmTransferControl;
UINTN TempStackTop;
UINTN TempStack[0x10];
//
// Restore IDT
//
AsmWriteIdtr (&PeiS3ResumeState->Idtr);
//
// Install BootScriptDonePpi
//
Status = PeiServicesInstallPpi (&mPpiListPostScriptTable);
ASSERT_EFI_ERROR (Status);
//
// Get ACPI Table Address
//
Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) ((UINTN) (AcpiS3Context->AcpiFacsTable));
if ((Facs == NULL) ||
(Facs->Signature != EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) ||
((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0)) ) {
CpuDeadLoop ();
return ;
}
//
// report status code on S3 resume
//
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEI_PC_OS_WAKE);
//
// Install EndOfPeiPpi
//
Status = PeiServicesInstallPpi (&mPpiListEndOfPeiTable);
ASSERT_EFI_ERROR (Status);
PERF_CODE (
WriteToOsS3PerformanceData ();
);
/**
Initialize Global Descriptor Table.
**/
VOID
SetLinuxDescriptorTables (
VOID
)
{
IA32_DESCRIPTOR GdtPtr;
IA32_DESCRIPTOR IdtPtr;
//
// Write GDT register
//
GdtPtr.Base = (UINT32)(UINTN)(VOID*) mGdt;
GdtPtr.Limit = (UINT16) (sizeof (GdtTemplate) - 1);
AsmWriteGdtr (&GdtPtr);
IdtPtr.Base = (UINT32) 0;
IdtPtr.Limit = (UINT16) 0;
AsmWriteIdtr (&IdtPtr);
}
/**
Wrapper for a thunk to transition from long mode to compatibility mode to execute 32-bit code and then transit back to
long mode.
@param[in] Function The 32bit code entry to be executed.
@param[in] Param1 The first parameter to pass to 32bit code.
@return EFI_STATUS.
**/
EFI_STATUS
Execute32BitCode (
IN UINT64 Function,
IN UINT64 Param1
)
{
EFI_STATUS Status;
IA32_DESCRIPTOR Idtr;
//
// Idtr might be changed inside of FSP. 32bit FSP only knows the <4G address.
// If IDTR.Base is >4G, FSP can not handle. So we need save/restore IDTR here for X64 only.
// Interrupt is already disabled here, so it is safety to update IDTR.
//
AsmReadIdtr (&Idtr);
Status = AsmExecute32BitCode (Function, Param1, 0, &mGdt);
AsmWriteIdtr (&Idtr);
return Status;
}
/**
Set a IDT entry for interrupt vector 3 for debug purpose.
@param AcpiS3Context a pointer to a structure of ACPI_S3_CONTEXT
**/
VOID
SetIdtEntry (
IN ACPI_S3_CONTEXT *AcpiS3Context
)
{
INTERRUPT_GATE_DESCRIPTOR *IdtEntry;
IA32_DESCRIPTOR *IdtDescriptor;
UINTN S3DebugBuffer;
//
// Restore IDT for debug
//
IdtDescriptor = (IA32_DESCRIPTOR *) (UINTN) (AcpiS3Context->IdtrProfile);
IdtEntry = (INTERRUPT_GATE_DESCRIPTOR *)(IdtDescriptor->Base + (3 * sizeof (INTERRUPT_GATE_DESCRIPTOR)));
S3DebugBuffer = (UINTN) (AcpiS3Context->S3DebugBufferAddress);
IdtEntry->OffsetLow = (UINT16)S3DebugBuffer;
IdtEntry->SegmentSelector = (UINT16)AsmReadCs ();
IdtEntry->Attributes = (UINT16)INTERRUPT_GATE_ATTRIBUTE;
IdtEntry->OffsetHigh = (UINT16)(S3DebugBuffer >> 16);
AsmWriteIdtr (IdtDescriptor);
}
/**
Perform CPU specific actions required to migrate the PEI Services Table
pointer from temporary RAM to permanent RAM.
For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes
immediately preceding the Interrupt Descriptor Table (IDT) in memory.
For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes
immediately preceding the Interrupt Descriptor Table (IDT) in memory.
For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in
a dedicated CPU register. This means that there is no memory storage
associated with storing the PEI Services Table pointer, so no additional
migration actions are required for Itanium or ARM CPUs.
If The cached PEI Services Table pointer is NULL, then ASSERT().
If the permanent memory is allocated failed, then ASSERT().
**/
VOID
EFIAPI
MigratePeiServicesTablePointer (
VOID
)
{
EFI_STATUS Status;
IA32_DESCRIPTOR Idtr;
EFI_PHYSICAL_ADDRESS IdtBase;
CONST EFI_PEI_SERVICES **PeiServices;
//
// Get PEI Services Table pointer
//
AsmReadIdtr (&Idtr);
PeiServices = (CONST EFI_PEI_SERVICES **) (*(UINTN*)(Idtr.Base - sizeof (UINTN)));
ASSERT (PeiServices != NULL);
//
// Allocate the permanent memory.
//
Status = (*PeiServices)->AllocatePages (
PeiServices,
EfiBootServicesCode,
EFI_SIZE_TO_PAGES(Idtr.Limit + 1 + sizeof (UINTN)),
&IdtBase
);
ASSERT_EFI_ERROR (Status);
//
// Idt table needs to be migrated into memory.
//
CopyMem ((VOID *) (UINTN) IdtBase, (VOID *) (Idtr.Base - sizeof (UINTN)), Idtr.Limit + 1 + sizeof (UINTN));
Idtr.Base = (UINTN) IdtBase + sizeof (UINTN);
AsmWriteIdtr (&Idtr);
return;
}
/**
The X64 entrypoint is used to process capsule in long mode then
return to 32-bit protected mode.
@param EntrypointContext Pointer to the context of long mode.
@param ReturnContext Pointer to the context of 32-bit protected mode.
@retval This function should never return actually.
**/
EFI_STATUS
EFIAPI
_ModuleEntryPoint (
SWITCH_32_TO_64_CONTEXT *EntrypointContext,
SWITCH_64_TO_32_CONTEXT *ReturnContext
)
{
EFI_STATUS Status;
IA32_DESCRIPTOR Ia32Idtr;
IA32_DESCRIPTOR X64Idtr;
IA32_IDT_GATE_DESCRIPTOR IdtEntryTable[EXCEPTION_VECTOR_NUMBER];
//
// Save the IA32 IDT Descriptor
//
AsmReadIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr);
//
// Setup X64 IDT table
//
ZeroMem (IdtEntryTable, sizeof (IA32_IDT_GATE_DESCRIPTOR) * EXCEPTION_VECTOR_NUMBER);
X64Idtr.Base = (UINTN) IdtEntryTable;
X64Idtr.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * EXCEPTION_VECTOR_NUMBER - 1);
AsmWriteIdtr ((IA32_DESCRIPTOR *) &X64Idtr);
//
// Setup the default CPU exception handlers
//
Status = InitializeCpuExceptionHandlers (NULL);
ASSERT_EFI_ERROR (Status);
//
// Initialize Debug Agent to support source level debug
//
InitializeDebugAgent (DEBUG_AGENT_INIT_THUNK_PEI_IA32TOX64, (VOID *) &Ia32Idtr, NULL);
//
// Call CapsuleDataCoalesce to process capsule.
//
Status = CapsuleDataCoalesce (
NULL,
(EFI_PHYSICAL_ADDRESS *) (UINTN) EntrypointContext->BlockListAddr,
(VOID **) (UINTN) EntrypointContext->MemoryBase64Ptr,
(UINTN *) (UINTN) EntrypointContext->MemorySize64Ptr
);
ReturnContext->ReturnStatus = Status;
//
// Disable interrupt of Debug timer, since the new IDT table cannot work in long mode
//
SaveAndSetDebugTimerInterrupt (FALSE);
//
// Restore IA32 IDT table
//
AsmWriteIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr);
//
// Finish to coalesce capsule, and return to 32-bit mode.
//
AsmDisablePaging64 (
ReturnContext->ReturnCs,
(UINT32) ReturnContext->ReturnEntryPoint,
(UINT32) (UINTN) EntrypointContext,
(UINT32) (UINTN) ReturnContext,
(UINT32) (EntrypointContext->StackBufferBase + EntrypointContext->StackBufferLength)
);
//
// Should never be here.
//
ASSERT (FALSE);
return EFI_SUCCESS;
}
/**
Initialize debug agent.
This function is used to set up debug enviroment for source level debug
in SMM code.
If InitFlag is DEBUG_AGENT_INIT_SMM, it will overirde IDT table entries
and initialize debug port. It will get debug agent Mailbox from GUIDed HOB,
it it exists, debug agent wiil copied it into the local Mailbox in SMM space.
it will overirde IDT table entries and initialize debug port. Context will be
NULL.
If InitFlag is DEBUG_AGENT_INIT_ENTER_SMI, debug agent will save Debug
Registers and get local Mailbox in SMM space. Context will be NULL.
If InitFlag is DEBUG_AGENT_INIT_EXIT_SMI, debug agent will restore Debug
Registers. Context will be NULL.
@param[in] InitFlag Init flag is used to decide initialize process.
@param[in] Context Context needed according to InitFlag.
@param[in] Function Continue function called by debug agent library; it was
optional.
**/
VOID
EFIAPI
InitializeDebugAgent (
IN UINT32 InitFlag,
IN VOID *Context, OPTIONAL
IN DEBUG_AGENT_CONTINUE Function OPTIONAL
)
{
EFI_STATUS Status;
UINT64 DebugPortHandle;
IA32_IDT_GATE_DESCRIPTOR IdtEntry[33];
IA32_DESCRIPTOR IdtDescriptor;
IA32_DESCRIPTOR *Ia32Idtr;
IA32_IDT_ENTRY *Ia32IdtEntry;
IA32_DESCRIPTOR Idtr;
UINT16 IdtEntryCount;
DEBUG_AGENT_MAILBOX *Mailbox;
UINT64 *MailboxLocation;
UINT32 DebugTimerFrequency;
BOOLEAN PeriodicMode;
UINTN TimerCycle;
switch (InitFlag) {
case DEBUG_AGENT_INIT_SMM:
//
// Install configuration table for persisted vector handoff info
//
Status = gSmst->SmmInstallConfigurationTable (
gSmst,
&gEfiVectorHandoffTableGuid,
(VOID *) &mVectorHandoffInfoDebugAgent[0],
sizeof (EFI_VECTOR_HANDOFF_INFO) * mVectorHandoffInfoCount
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "DebugAgent: Cannot install configuration table for persisted vector handoff info!\n"));
CpuDeadLoop ();
}
//
// Check if Debug Agent initialized in DXE phase
//
Status = EfiGetSystemConfigurationTable (&gEfiDebugAgentGuid, (VOID **) &Mailbox);
if (Status == EFI_SUCCESS && Mailbox != NULL) {
VerifyMailboxChecksum (Mailbox);
mMailboxPointer = Mailbox;
break;
}
//
// Check if Debug Agent initialized in SEC/PEI phase
//
Mailbox = GetMailboxFromHob ();
if (Mailbox != NULL) {
mMailboxPointer = Mailbox;
break;
}
//
// Debug Agent was not initialized before, use the local mailbox.
//
ZeroMem (&mLocalMailbox, sizeof (DEBUG_AGENT_MAILBOX));
Mailbox = &mLocalMailbox;
//
// Save original IDT entries
//
AsmReadIdtr (&IdtDescriptor);
CopyMem (&IdtEntry, (VOID *)IdtDescriptor.Base, 33 * sizeof(IA32_IDT_GATE_DESCRIPTOR));
//
// Initialized Debug Agent
//
InitializeDebugIdt ();
//
// Initialize Debug Timer hardware and save its frequency
//
InitializeDebugTimer (&DebugTimerFrequency, TRUE);
UpdateMailboxContent (Mailbox, DEBUG_MAILBOX_DEBUG_TIMER_FREQUENCY, DebugTimerFrequency);
DebugPortHandle = (UINT64) (UINTN)DebugPortInitialize ((DEBUG_PORT_HANDLE) (UINTN)Mailbox->DebugPortHandle, NULL);
UpdateMailboxContent (Mailbox, DEBUG_MAILBOX_DEBUG_PORT_HANDLE_INDEX, DebugPortHandle);
mMailboxPointer = Mailbox;
//
// Trigger one software interrupt to inform HOST
//
TriggerSoftInterrupt (SYSTEM_RESET_SIGNATURE);
SetDebugFlag (DEBUG_AGENT_FLAG_MEMORY_READY, 1);
//
// Memory has been ready
//
if (IsHostAttached ()) {
//
// Trigger one software interrupt to inform HOST
//
TriggerSoftInterrupt (MEMORY_READY_SIGNATURE);
}
//
// Find and report PE/COFF image info to HOST
//
FindAndReportModuleImageInfo (SIZE_4KB);
//
// Restore saved IDT entries
//
CopyMem ((VOID *)IdtDescriptor.Base, &IdtEntry, 33 * sizeof(IA32_IDT_GATE_DESCRIPTOR));
break;
case DEBUG_AGENT_INIT_ENTER_SMI:
SaveDebugRegister ();
if (!mSmmDebugIdtInitFlag) {
//
// We only need to initialize Debug IDT table at first SMI entry
// after SMM relocation.
//
InitializeDebugIdt ();
mSmmDebugIdtInitFlag = TRUE;
}
//
// Check if CPU APIC Timer is working, otherwise initialize it.
//
InitializeLocalApicSoftwareEnable (TRUE);
GetApicTimerState (NULL, &PeriodicMode, NULL);
TimerCycle = GetApicTimerInitCount ();
if (!PeriodicMode || TimerCycle == 0) {
InitializeDebugTimer (NULL, FALSE);
}
Mailbox = GetMailboxPointer ();
if (GetDebugFlag (DEBUG_AGENT_FLAG_AGENT_IN_PROGRESS) == 1) {
//
// If Debug Agent has been communicaton state with HOST, we need skip
// any break points set in SMM, set Skip Breakpoint flag
//
mSkipBreakpoint = TRUE;
}
if (GetDebugFlag (DEBUG_AGENT_FLAG_BREAK_ON_NEXT_SMI) == 1) {
if (mSkipBreakpoint) {
//
// Print warning message if ignore smm entry break
//
DebugPortWriteBuffer ((DEBUG_PORT_HANDLE) (UINTN)Mailbox->DebugPortHandle,
(UINT8 *)mWarningMsgIgnoreSmmEntryBreak,
AsciiStrLen (mWarningMsgIgnoreSmmEntryBreak)
);
} else {
//
// If SMM entry break is set, SMM code will be break at here.
//
CpuBreakpoint ();
}
}
break;
case DEBUG_AGENT_INIT_EXIT_SMI:
Mailbox = GetMailboxPointer ();
//
// Clear Skip Breakpoint flag
//
mSkipBreakpoint = FALSE;
RestoreDebugRegister ();
break;
case DEBUG_AGENT_INIT_THUNK_PEI_IA32TOX64:
if (Context == NULL) {
DEBUG ((EFI_D_ERROR, "DebugAgent: Input parameter Context cannot be NULL!\n"));
CpuDeadLoop ();
} else {
Ia32Idtr = (IA32_DESCRIPTOR *) Context;
Ia32IdtEntry = (IA32_IDT_ENTRY *)(Ia32Idtr->Base);
MailboxLocation = (UINT64 *) (UINTN) (Ia32IdtEntry[DEBUG_MAILBOX_VECTOR].Bits.OffsetLow +
(UINT32) (Ia32IdtEntry[DEBUG_MAILBOX_VECTOR].Bits.OffsetHigh << 16));
mMailboxPointer = (DEBUG_AGENT_MAILBOX *)(UINTN)(*MailboxLocation);
VerifyMailboxChecksum (mMailboxPointer);
//
// Get original IDT address and size.
//
AsmReadIdtr ((IA32_DESCRIPTOR *) &Idtr);
IdtEntryCount = (UINT16) ((Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR));
if (IdtEntryCount < 33) {
Idtr.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 33 - 1);
Idtr.Base = (UINTN) &mIdtEntryTable;
ZeroMem (&mIdtEntryTable, Idtr.Limit + 1);
AsmWriteIdtr ((IA32_DESCRIPTOR *) &Idtr);
}
InitializeDebugIdt ();
//
// Initialize Debug Timer hardware and save its frequency
//
InitializeDebugTimer (&DebugTimerFrequency, TRUE);
UpdateMailboxContent (mMailboxPointer, DEBUG_MAILBOX_DEBUG_TIMER_FREQUENCY, DebugTimerFrequency);
//
// Enable Debug Timer interrupt and CPU interrupt
//
SaveAndSetDebugTimerInterrupt (TRUE);
EnableInterrupts ();
FindAndReportModuleImageInfo (SIZE_4KB);
}
break;
default:
//
// Only DEBUG_AGENT_INIT_PREMEM_SEC and DEBUG_AGENT_INIT_POSTMEM_SEC are allowed for this
// Debug Agent library instance.
//
DEBUG ((EFI_D_ERROR, "Debug Agent: The InitFlag value is not allowed!\n"));
CpuDeadLoop ();
break;
}
}
/**
Entry point to the C language phase of SEC. After the SEC assembly
code has initialized some temporary memory and set up the stack,
the control is transferred to this function.
@param[in] SizeOfRam Size of the temporary memory available for use.
@param[in] TempRamBase Base address of tempory ram
@param[in] BootFirmwareVolume Base address of the Boot Firmware Volume.
@param[in] PeiCore PeiCore entry point.
@param[in] BootLoaderStack BootLoader stack.
@param[in] ApiIdx the index of API.
@return This function never returns.
**/
VOID
EFIAPI
SecStartup (
IN UINT32 SizeOfRam,
IN UINT32 TempRamBase,
IN VOID *BootFirmwareVolume,
IN PEI_CORE_ENTRY PeiCore,
IN UINT32 BootLoaderStack,
IN UINT32 ApiIdx
)
{
EFI_SEC_PEI_HAND_OFF SecCoreData;
IA32_DESCRIPTOR IdtDescriptor;
SEC_IDT_TABLE IdtTableInStack;
UINT32 Index;
FSP_GLOBAL_DATA PeiFspData;
UINT64 ExceptionHandler;
//
// Process all libraries constructor function linked to SecCore.
//
ProcessLibraryConstructorList ();
//
// Initialize floating point operating environment
// to be compliant with UEFI spec.
//
InitializeFloatingPointUnits ();
// |-------------------|---->
// |Idt Table |
// |-------------------|
// |PeiService Pointer | PeiStackSize
// |-------------------|
// | |
// | Stack |
// |-------------------|---->
// | |
// | |
// | Heap | PeiTemporayRamSize
// | |
// | |
// |-------------------|----> TempRamBase
IdtTableInStack.PeiService = NULL;
ExceptionHandler = FspGetExceptionHandler(mIdtEntryTemplate);
for (Index = 0; Index < SEC_IDT_ENTRY_COUNT; Index ++) {
CopyMem ((VOID*)&IdtTableInStack.IdtTable[Index], (VOID*)&ExceptionHandler, sizeof (UINT64));
}
IdtDescriptor.Base = (UINTN) &IdtTableInStack.IdtTable;
IdtDescriptor.Limit = (UINT16)(sizeof (IdtTableInStack.IdtTable) - 1);
AsmWriteIdtr (&IdtDescriptor);
//
// Initialize the global FSP data region
//
FspGlobalDataInit (&PeiFspData, BootLoaderStack, (UINT8)ApiIdx);
//
// Update the base address and length of Pei temporary memory
//
SecCoreData.DataSize = sizeof (EFI_SEC_PEI_HAND_OFF);
SecCoreData.BootFirmwareVolumeBase = BootFirmwareVolume;
SecCoreData.BootFirmwareVolumeSize = (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *)BootFirmwareVolume)->FvLength;
SecCoreData.TemporaryRamBase = (VOID*)(UINTN) TempRamBase;
SecCoreData.TemporaryRamSize = SizeOfRam;
SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;
SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize * PcdGet8 (PcdFspHeapSizePercentage) / 100;
SecCoreData.StackBase = (VOID*)(UINTN)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);
SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;
DEBUG ((DEBUG_INFO, "Fsp BootFirmwareVolumeBase - 0x%x\n", SecCoreData.BootFirmwareVolumeBase));
DEBUG ((DEBUG_INFO, "Fsp BootFirmwareVolumeSize - 0x%x\n", SecCoreData.BootFirmwareVolumeSize));
DEBUG ((DEBUG_INFO, "Fsp TemporaryRamBase - 0x%x\n", SecCoreData.TemporaryRamBase));
DEBUG ((DEBUG_INFO, "Fsp TemporaryRamSize - 0x%x\n", SecCoreData.TemporaryRamSize));
DEBUG ((DEBUG_INFO, "Fsp PeiTemporaryRamBase - 0x%x\n", SecCoreData.PeiTemporaryRamBase));
DEBUG ((DEBUG_INFO, "Fsp PeiTemporaryRamSize - 0x%x\n", SecCoreData.PeiTemporaryRamSize));
DEBUG ((DEBUG_INFO, "Fsp StackBase - 0x%x\n", SecCoreData.StackBase));
DEBUG ((DEBUG_INFO, "Fsp StackSize - 0x%x\n", SecCoreData.StackSize));
//
// Call PeiCore Entry
//
PeiCore (&SecCoreData, mPeiSecPlatformInformationPpi);
//
// Should never be here
//
CpuDeadLoop ();
}
/**
This service of the TEMPORARY_RAM_SUPPORT_PPI that migrates temporary RAM into
permanent memory.
@param[in] PeiServices Pointer to the PEI Services Table.
@param[in] TemporaryMemoryBase Source Address in temporary memory from which the SEC or PEIM will copy the
Temporary RAM contents.
@param[in] PermanentMemoryBase Destination Address in permanent memory into which the SEC or PEIM will copy the
Temporary RAM contents.
@param[in] CopySize Amount of memory to migrate from temporary to permanent memory.
@retval EFI_SUCCESS The data was successfully returned.
@retval EFI_INVALID_PARAMETER PermanentMemoryBase + CopySize > TemporaryMemoryBase when
TemporaryMemoryBase > PermanentMemoryBase.
**/
EFI_STATUS
EFIAPI
SecTemporaryRamSupport (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
IN UINTN CopySize
)
{
IA32_DESCRIPTOR IdtDescriptor;
VOID* OldHeap;
VOID* NewHeap;
VOID* OldStack;
VOID* NewStack;
UINTN HeapSize;
UINTN StackSize;
HeapSize = CopySize * PcdGet8 (PcdFspHeapSizePercentage) / 100 ;
StackSize = CopySize - HeapSize;
OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;
NewHeap = (VOID*)((UINTN)PermanentMemoryBase + StackSize);
OldStack = (VOID*)((UINTN)TemporaryMemoryBase + HeapSize);
NewStack = (VOID*)(UINTN)PermanentMemoryBase;
//
// Migrate Heap
//
CopyMem (NewHeap, OldHeap, HeapSize);
//
// Migrate Stack
//
CopyMem (NewStack, OldStack, StackSize);
//
// We need *not* fix the return address because currently,
// The PeiCore is executed in flash.
//
//
// Rebase IDT table in permanent memory
//
AsmReadIdtr (&IdtDescriptor);
IdtDescriptor.Base = IdtDescriptor.Base - (UINTN)OldStack + (UINTN)NewStack;
AsmWriteIdtr (&IdtDescriptor);
//
// Fixed the FSP data pointer
//
FspDataPointerFixUp ((UINTN)NewStack - (UINTN)OldStack);
//
// SecSwitchStack function must be invoked after the memory migration
// immediatly, also we need fixup the stack change caused by new call into
// permenent memory.
//
SecSwitchStack (
(UINT32) (UINTN) OldStack,
(UINT32) (UINTN) NewStack
);
return EFI_SUCCESS;
}
/**
Initialize debug agent.
This function is used to set up debug enviroment for DXE phase.
If this function is called by DXE Core, Context must be the pointer
to HOB list which will be used to get GUIDed HOB. It will enable
interrupt to support break-in feature.
If this function is called by DXE module, Context must be NULL. It
will enable interrupt to support break-in feature.
@param[in] InitFlag Init flag is used to decide initialize process.
@param[in] Context Context needed according to InitFlag.
@param[in] Function Continue function called by debug agent library; it was
optional.
**/
VOID
EFIAPI
InitializeDebugAgent (
IN UINT32 InitFlag,
IN VOID *Context, OPTIONAL
IN DEBUG_AGENT_CONTINUE Function OPTIONAL
)
{
UINT64 *MailboxLocation;
DEBUG_AGENT_MAILBOX *Mailbox;
BOOLEAN InterruptStatus;
VOID *HobList;
IA32_DESCRIPTOR IdtDescriptor;
IA32_DESCRIPTOR *Ia32Idtr;
IA32_IDT_ENTRY *Ia32IdtEntry;
if (InitFlag == DEBUG_AGENT_INIT_DXE_AP) {
//
// Invoked by AP, enable interrupt to let AP could receive IPI from other processors
//
EnableInterrupts ();
return ;
}
//
// Disable Debug Timer interrupt
//
SaveAndSetDebugTimerInterrupt (FALSE);
//
// Save and disable original interrupt status
//
InterruptStatus = SaveAndDisableInterrupts ();
//
// Try to get mailbox firstly
//
HobList = NULL;
Mailbox = NULL;
MailboxLocation = NULL;
switch (InitFlag) {
case DEBUG_AGENT_INIT_DXE_LOAD:
//
// Check if Debug Agent has been initialized before
//
if (IsDebugAgentInitialzed ()) {
DEBUG ((EFI_D_INFO, "Debug Agent: The former agent will be overwritten by the new one!\n"));
}
mMultiProcessorDebugSupport = TRUE;
//
// Save original IDT table
//
AsmReadIdtr (&IdtDescriptor);
mSaveIdtTableSize = IdtDescriptor.Limit + 1;
mSavedIdtTable = AllocateCopyPool (mSaveIdtTableSize, (VOID *) IdtDescriptor.Base);
//
// Initialize Debug Timer hardware and save its initial count
//
mDebugMpContext.DebugTimerInitCount = InitializeDebugTimer ();
//
// Check if Debug Agent initialized in DXE phase
//
Mailbox = GetMailboxFromConfigurationTable ();
if (Mailbox == NULL) {
//
// Try to get mailbox from GUIDed HOB build in PEI
//
HobList = GetHobList ();
Mailbox = GetMailboxFromHob (HobList);
}
//
// Set up IDT table and prepare for IDT entries
//
SetupDebugAgentEnviroment (Mailbox);
//
// For DEBUG_AGENT_INIT_S3, needn't to install configuration table and EFI Serial IO protocol
// For DEBUG_AGENT_INIT_DXE_CORE, InternalConstructorWorker() will invoked in Constructor()
//
InternalConstructorWorker ();
//
// Enable interrupt to receive Debug Timer interrupt
//
EnableInterrupts ();
mDebugAgentInitialized = TRUE;
FindAndReportModuleImageInfo (SIZE_4KB);
*(EFI_STATUS *)Context = EFI_SUCCESS;
if (gST->ConOut != NULL) {
Print (L"Debug Agent: Initialized successfully!\r\n");
Print (L"If the Debug Port is serial port, please make sure this serial port isn't connected by ISA Serial driver\r\n");
Print (L"You could do the following steps to disconnect the serial port:\r\n");
Print (L"1: Shell> drivers\r\n");
Print (L" ...\r\n");
Print (L" V VERSION E G G #D #C DRIVER NAME IMAGE NAME\r\n");
Print (L" == ======== = = = == == =================================== ===================\r\n");
Print (L" 8F 0000000A B - - 1 14 PCI Bus Driver PciBusDxe\r\n");
Print (L" 91 00000010 ? - - - - ATA Bus Driver AtaBusDxe\r\n");
Print (L" ...\r\n");
Print (L" A7 0000000A B - - 1 1 ISA Serial Driver IsaSerialDxe\r\n");
Print (L" ...\r\n");
Print (L"2: Shell> dh -d A7\r\n");
Print (L" A7: Image(IsaSerialDxe) ImageDevPath (..9FB3-11D4-9A3A-0090273FC14D))DriverBinding ComponentName ComponentName2\r\n");
Print (L" Driver Name : ISA Serial Driver\r\n");
Print (L" Image Name : FvFile(93B80003-9FB3-11D4-9A3A-0090273FC14D)\r\n");
Print (L" Driver Version : 0000000A\r\n");
Print (L" Driver Type : BUS\r\n");
Print (L" Configuration : NO\r\n");
Print (L" Diagnostics : NO\r\n");
Print (L" Managing :\r\n");
Print (L" Ctrl[EA] : PciRoot(0x0)/Pci(0x1F,0x0)/Serial(0x0)\r\n");
Print (L" Child[EB] : PciRoot(0x0)/Pci(0x1F,0x0)/Serial(0x0)/Uart(115200,8,N,1)\r\n");
Print (L"3: Shell> disconnect EA\r\n");
Print (L"4: Shell> load -nc DebugAgentDxe.efi\r\n\r\n");
}
break;
case DEBUG_AGENT_INIT_DXE_UNLOAD:
if (mDebugAgentInitialized) {
if (IsHostAttached ()) {
Print (L"Debug Agent: Host is still connected, please de-attach TARGET firstly!\r\n");
*(EFI_STATUS *)Context = EFI_ACCESS_DENIED;
//
// Enable Debug Timer interrupt again
//
SaveAndSetDebugTimerInterrupt (TRUE);
} else {
//
// Restore original IDT table
//
AsmReadIdtr (&IdtDescriptor);
IdtDescriptor.Limit = (UINT16) (mSaveIdtTableSize - 1);
CopyMem ((VOID *) IdtDescriptor.Base, mSavedIdtTable, mSaveIdtTableSize);
AsmWriteIdtr (&IdtDescriptor);
FreePool (mSavedIdtTable);
mDebugAgentInitialized = FALSE;
*(EFI_STATUS *)Context = EFI_SUCCESS;
}
} else {
Print (L"Debug Agent: It hasn't been initialized, cannot unload it!\r\n");
*(EFI_STATUS *)Context = EFI_NOT_STARTED;
}
//
// Restore interrupt state.
//
SetInterruptState (InterruptStatus);
break;
case DEBUG_AGENT_INIT_DXE_CORE:
mDxeCoreFlag = TRUE;
mMultiProcessorDebugSupport = TRUE;
//
// Initialize Debug Timer hardware and its initial count
//
mDebugMpContext.DebugTimerInitCount = InitializeDebugTimer ();
//
// Try to get mailbox from GUIDed HOB build in PEI
//
HobList = Context;
Mailbox = GetMailboxFromHob (HobList);
//
// Set up IDT table and prepare for IDT entries
//
SetupDebugAgentEnviroment (Mailbox);
//
// Enable interrupt to receive Debug Timer interrupt
//
EnableInterrupts ();
break;
case DEBUG_AGENT_INIT_S3:
if (Context != NULL) {
Ia32Idtr = (IA32_DESCRIPTOR *) Context;
Ia32IdtEntry = (IA32_IDT_ENTRY *)(Ia32Idtr->Base);
MailboxLocation = (UINT64 *) (UINTN) (Ia32IdtEntry[DEBUG_MAILBOX_VECTOR].Bits.OffsetLow +
(Ia32IdtEntry[DEBUG_MAILBOX_VECTOR].Bits.OffsetHigh << 16));
Mailbox = (DEBUG_AGENT_MAILBOX *)(UINTN)(*MailboxLocation);
VerifyMailboxChecksum (Mailbox);
}
//
// Save Mailbox pointer in global variable
//
mMailboxPointer = Mailbox;
//
// Set up IDT table and prepare for IDT entries
//
SetupDebugAgentEnviroment (Mailbox);
//
// Disable interrupt
//
DisableInterrupts ();
FindAndReportModuleImageInfo (SIZE_4KB);
if (GetDebugFlag (DEBUG_AGENT_FLAG_BREAK_BOOT_SCRIPT) == 1) {
//
// If Boot Script entry break is set, code will be break at here.
//
CpuBreakpoint ();
}
break;
default:
//
// Only DEBUG_AGENT_INIT_PREMEM_SEC and DEBUG_AGENT_INIT_POSTMEM_SEC are allowed for this
// Debug Agent library instance.
//
DEBUG ((EFI_D_ERROR, "Debug Agent: The InitFlag value is not allowed!\n"));
CpuDeadLoop ();
break;
}
}
/**
Perform SMM initialization for all processors in the S3 boot path.
For a native platform, MP initialization in the S3 boot path is also performed in this function.
**/
VOID
EFIAPI
SmmRestoreCpu (
VOID
)
{
SMM_S3_RESUME_STATE *SmmS3ResumeState;
IA32_DESCRIPTOR Ia32Idtr;
IA32_DESCRIPTOR X64Idtr;
IA32_IDT_GATE_DESCRIPTOR IdtEntryTable[EXCEPTION_VECTOR_NUMBER];
EFI_STATUS Status;
DEBUG ((EFI_D_INFO, "SmmRestoreCpu()\n"));
mSmmS3Flag = TRUE;
InitializeSpinLock (mMemoryMappedLock);
//
// See if there is enough context to resume PEI Phase
//
if (mSmmS3ResumeState == NULL) {
DEBUG ((EFI_D_ERROR, "No context to return to PEI Phase\n"));
CpuDeadLoop ();
}
SmmS3ResumeState = mSmmS3ResumeState;
ASSERT (SmmS3ResumeState != NULL);
if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) {
//
// Save the IA32 IDT Descriptor
//
AsmReadIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr);
//
// Setup X64 IDT table
//
ZeroMem (IdtEntryTable, sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32);
X64Idtr.Base = (UINTN) IdtEntryTable;
X64Idtr.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32 - 1);
AsmWriteIdtr ((IA32_DESCRIPTOR *) &X64Idtr);
//
// Setup the default exception handler
//
Status = InitializeCpuExceptionHandlers (NULL);
ASSERT_EFI_ERROR (Status);
//
// Initialize Debug Agent to support source level debug
//
InitializeDebugAgent (DEBUG_AGENT_INIT_THUNK_PEI_IA32TOX64, (VOID *)&Ia32Idtr, NULL);
}
//
// Skip initialization if mAcpiCpuData is not valid
//
if (mAcpiCpuData.NumberOfCpus > 0) {
//
// First time microcode load and restore MTRRs
//
InitializeCpuBeforeRebase ();
}
//
// Restore SMBASE for BSP and all APs
//
SmmRelocateBases ();
//
// Skip initialization if mAcpiCpuData is not valid
//
if (mAcpiCpuData.NumberOfCpus > 0) {
//
// Restore MSRs for BSP and all APs
//
InitializeCpuAfterRebase ();
}
//
// Set a flag to restore SMM configuration in S3 path.
//
mRestoreSmmConfigurationInS3 = TRUE;
DEBUG (( EFI_D_INFO, "SMM S3 Return CS = %x\n", SmmS3ResumeState->ReturnCs));
DEBUG (( EFI_D_INFO, "SMM S3 Return Entry Point = %x\n", SmmS3ResumeState->ReturnEntryPoint));
DEBUG (( EFI_D_INFO, "SMM S3 Return Context1 = %x\n", SmmS3ResumeState->ReturnContext1));
DEBUG (( EFI_D_INFO, "SMM S3 Return Context2 = %x\n", SmmS3ResumeState->ReturnContext2));
DEBUG (( EFI_D_INFO, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState->ReturnStackPointer));
//
// If SMM is in 32-bit mode, then use SwitchStack() to resume PEI Phase
//
if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_32) {
DEBUG ((EFI_D_INFO, "Call SwitchStack() to return to S3 Resume in PEI Phase\n"));
SwitchStack (
(SWITCH_STACK_ENTRY_POINT)(UINTN)SmmS3ResumeState->ReturnEntryPoint,
(VOID *)(UINTN)SmmS3ResumeState->ReturnContext1,
(VOID *)(UINTN)SmmS3ResumeState->ReturnContext2,
(VOID *)(UINTN)SmmS3ResumeState->ReturnStackPointer
);
}
//
// If SMM is in 64-bit mode, then use AsmDisablePaging64() to resume PEI Phase
//
if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) {
DEBUG ((EFI_D_INFO, "Call AsmDisablePaging64() to return to S3 Resume in PEI Phase\n"));
//
// Disable interrupt of Debug timer, since new IDT table is for IA32 and will not work in long mode.
//
SaveAndSetDebugTimerInterrupt (FALSE);
//
// Restore IA32 IDT table
//
AsmWriteIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr);
AsmDisablePaging64 (
SmmS3ResumeState->ReturnCs,
(UINT32)SmmS3ResumeState->ReturnEntryPoint,
(UINT32)SmmS3ResumeState->ReturnContext1,
(UINT32)SmmS3ResumeState->ReturnContext2,
(UINT32)SmmS3ResumeState->ReturnStackPointer
);
}
//
// Can not resume PEI Phase
//
DEBUG ((EFI_D_ERROR, "No context to return to PEI Phase\n"));
CpuDeadLoop ();
}
/**
Transfers control to DxeCore.
This function performs a CPU architecture specific operations to execute
the entry point of DxeCore with the parameters of HobList.
It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
@param DxeCoreEntryPoint The entry point of DxeCore.
@param HobList The start of HobList passed to DxeCore.
**/
VOID
HandOffToDxeCore (
IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
IN EFI_PEI_HOB_POINTERS HobList
)
{
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS BaseOfStack;
EFI_PHYSICAL_ADDRESS TopOfStack;
UINTN PageTables;
X64_IDT_GATE_DESCRIPTOR *IdtTable;
UINTN SizeOfTemplate;
VOID *TemplateBase;
EFI_PHYSICAL_ADDRESS VectorAddress;
UINT32 Index;
X64_IDT_TABLE *IdtTableForX64;
EFI_VECTOR_HANDOFF_INFO *VectorInfo;
EFI_PEI_VECTOR_HANDOFF_INFO_PPI *VectorHandoffInfoPpi;
BOOLEAN BuildPageTablesIa32Pae;
if (IsNullDetectionEnabled ()) {
ClearFirst4KPage (HobList.Raw);
}
Status = PeiServicesAllocatePages (EfiBootServicesData, EFI_SIZE_TO_PAGES (STACK_SIZE), &BaseOfStack);
ASSERT_EFI_ERROR (Status);
if (FeaturePcdGet(PcdDxeIplSwitchToLongMode)) {
//
// Compute the top of the stack we were allocated, which is used to load X64 dxe core.
// Pre-allocate a 32 bytes which confroms to x64 calling convention.
//
// The first four parameters to a function are passed in rcx, rdx, r8 and r9.
// Any further parameters are pushed on the stack. Furthermore, space (4 * 8bytes) for the
// register parameters is reserved on the stack, in case the called function
// wants to spill them; this is important if the function is variadic.
//
TopOfStack = BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - 32;
//
// x64 Calling Conventions requires that the stack must be aligned to 16 bytes
//
TopOfStack = (EFI_PHYSICAL_ADDRESS) (UINTN) ALIGN_POINTER (TopOfStack, 16);
//
// Load the GDT of Go64. Since the GDT of 32-bit Tiano locates in the BS_DATA
// memory, it may be corrupted when copying FV to high-end memory
//
AsmWriteGdtr (&gGdt);
//
// Create page table and save PageMapLevel4 to CR3
//
PageTables = CreateIdentityMappingPageTables (BaseOfStack, STACK_SIZE);
//
// End of PEI phase signal
//
PERF_EVENT_SIGNAL_BEGIN (gEndOfPeiSignalPpi.Guid);
Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);
PERF_EVENT_SIGNAL_END (gEndOfPeiSignalPpi.Guid);
ASSERT_EFI_ERROR (Status);
//
// Paging might be already enabled. To avoid conflict configuration,
// disable paging first anyway.
//
AsmWriteCr0 (AsmReadCr0 () & (~BIT31));
AsmWriteCr3 (PageTables);
//
// Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.
//
UpdateStackHob (BaseOfStack, STACK_SIZE);
SizeOfTemplate = AsmGetVectorTemplatInfo (&TemplateBase);
Status = PeiServicesAllocatePages (
EfiBootServicesData,
EFI_SIZE_TO_PAGES(sizeof (X64_IDT_TABLE) + SizeOfTemplate * IDT_ENTRY_COUNT),
&VectorAddress
);
ASSERT_EFI_ERROR (Status);
//
// Store EFI_PEI_SERVICES** in the 4 bytes immediately preceding IDT to avoid that
// it may not be gotten correctly after IDT register is re-written.
//
IdtTableForX64 = (X64_IDT_TABLE *) (UINTN) VectorAddress;
IdtTableForX64->PeiService = GetPeiServicesTablePointer ();
VectorAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) (IdtTableForX64 + 1);
IdtTable = IdtTableForX64->IdtTable;
for (Index = 0; Index < IDT_ENTRY_COUNT; Index++) {
IdtTable[Index].Ia32IdtEntry.Bits.GateType = 0x8e;
IdtTable[Index].Ia32IdtEntry.Bits.Reserved_0 = 0;
IdtTable[Index].Ia32IdtEntry.Bits.Selector = SYS_CODE64_SEL;
IdtTable[Index].Ia32IdtEntry.Bits.OffsetLow = (UINT16) VectorAddress;
IdtTable[Index].Ia32IdtEntry.Bits.OffsetHigh = (UINT16) (RShiftU64 (VectorAddress, 16));
IdtTable[Index].Offset32To63 = (UINT32) (RShiftU64 (VectorAddress, 32));
IdtTable[Index].Reserved = 0;
CopyMem ((VOID *) (UINTN) VectorAddress, TemplateBase, SizeOfTemplate);
AsmVectorFixup ((VOID *) (UINTN) VectorAddress, (UINT8) Index);
VectorAddress += SizeOfTemplate;
}
gLidtDescriptor.Base = (UINTN) IdtTable;
//
// Disable interrupt of Debug timer, since new IDT table cannot handle it.
//
SaveAndSetDebugTimerInterrupt (FALSE);
AsmWriteIdtr (&gLidtDescriptor);
DEBUG ((
DEBUG_INFO,
"%a() Stack Base: 0x%lx, Stack Size: 0x%x\n",
__FUNCTION__,
BaseOfStack,
STACK_SIZE
));
//
// Go to Long Mode and transfer control to DxeCore.
// Interrupts will not get turned on until the CPU AP is loaded.
// Call x64 drivers passing in single argument, a pointer to the HOBs.
//
AsmEnablePaging64 (
SYS_CODE64_SEL,
DxeCoreEntryPoint,
(EFI_PHYSICAL_ADDRESS)(UINTN)(HobList.Raw),
0,
TopOfStack
);
} else {
//
// Get Vector Hand-off Info PPI and build Guided HOB
//
Status = PeiServicesLocatePpi (
&gEfiVectorHandoffInfoPpiGuid,
0,
NULL,
(VOID **)&VectorHandoffInfoPpi
);
if (Status == EFI_SUCCESS) {
DEBUG ((EFI_D_INFO, "Vector Hand-off Info PPI is gotten, GUIDed HOB is created!\n"));
VectorInfo = VectorHandoffInfoPpi->Info;
Index = 1;
while (VectorInfo->Attribute != EFI_VECTOR_HANDOFF_LAST_ENTRY) {
VectorInfo ++;
Index ++;
}
BuildGuidDataHob (
&gEfiVectorHandoffInfoPpiGuid,
VectorHandoffInfoPpi->Info,
sizeof (EFI_VECTOR_HANDOFF_INFO) * Index
);
}
//
// Compute the top of the stack we were allocated. Pre-allocate a UINTN
// for safety.
//
TopOfStack = BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT;
TopOfStack = (EFI_PHYSICAL_ADDRESS) (UINTN) ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);
PageTables = 0;
BuildPageTablesIa32Pae = ToBuildPageTable ();
if (BuildPageTablesIa32Pae) {
PageTables = Create4GPageTablesIa32Pae (BaseOfStack, STACK_SIZE);
if (IsEnableNonExecNeeded ()) {
EnableExecuteDisableBit();
}
}
//
// End of PEI phase signal
//
PERF_EVENT_SIGNAL_BEGIN (gEndOfPeiSignalPpi.Guid);
Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);
PERF_EVENT_SIGNAL_END (gEndOfPeiSignalPpi.Guid);
ASSERT_EFI_ERROR (Status);
if (BuildPageTablesIa32Pae) {
//
// Paging might be already enabled. To avoid conflict configuration,
// disable paging first anyway.
//
AsmWriteCr0 (AsmReadCr0 () & (~BIT31));
AsmWriteCr3 (PageTables);
//
// Set Physical Address Extension (bit 5 of CR4).
//
AsmWriteCr4 (AsmReadCr4 () | BIT5);
}
//
// Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.
//
UpdateStackHob (BaseOfStack, STACK_SIZE);
DEBUG ((
DEBUG_INFO,
"%a() Stack Base: 0x%lx, Stack Size: 0x%x\n",
__FUNCTION__,
BaseOfStack,
STACK_SIZE
));
//
// Transfer the control to the entry point of DxeCore.
//
if (BuildPageTablesIa32Pae) {
AsmEnablePaging32 (
(SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,
HobList.Raw,
NULL,
(VOID *) (UINTN) TopOfStack
);
} else {
SwitchStack (
(SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,
HobList.Raw,
NULL,
(VOID *) (UINTN) TopOfStack
);
}
}
}
/**
Worker function to setup IDT table and initialize the IDT entries.
@param[in] Mailbox Pointer to Mailbox.
**/
VOID
SetupDebugAgentEnviroment (
IN DEBUG_AGENT_MAILBOX *Mailbox
)
{
IA32_DESCRIPTOR Idtr;
UINT16 IdtEntryCount;
UINT64 DebugPortHandle;
if (mMultiProcessorDebugSupport) {
InitializeSpinLock (&mDebugMpContext.MpContextSpinLock);
InitializeSpinLock (&mDebugMpContext.DebugPortSpinLock);
InitializeSpinLock (&mDebugMpContext.MailboxSpinLock);
//
// Clear Break CPU index value
//
mDebugMpContext.BreakAtCpuIndex = (UINT32) -1;
}
//
// Get original IDT address and size.
//
AsmReadIdtr ((IA32_DESCRIPTOR *) &Idtr);
IdtEntryCount = (UINT16) ((Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR));
if (IdtEntryCount < 33) {
ZeroMem (&mIdtEntryTable, sizeof (IA32_IDT_GATE_DESCRIPTOR) * 33);
//
// Copy original IDT table into new one
//
CopyMem (&mIdtEntryTable, (VOID *) Idtr.Base, Idtr.Limit + 1);
//
// Load new IDT table
//
Idtr.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 33 - 1);
Idtr.Base = (UINTN) &mIdtEntryTable;
AsmWriteIdtr ((IA32_DESCRIPTOR *) &Idtr);
}
//
// Initialize the IDT table entries to support source level debug.
//
InitializeDebugIdt ();
//
// If mMailboxPointer is not set before, set it
//
if (mMailboxPointer == NULL) {
if (Mailbox != NULL) {
//
// If Mailbox exists, copy it into one global variable
//
CopyMem (&mMailbox, Mailbox, sizeof (DEBUG_AGENT_MAILBOX));
} else {
ZeroMem (&mMailbox, sizeof (DEBUG_AGENT_MAILBOX));
}
mMailboxPointer = &mMailbox;
}
//
// Initialize debug communication port
//
DebugPortHandle = (UINT64) (UINTN)DebugPortInitialize ((VOID *)(UINTN)mMailboxPointer->DebugPortHandle, NULL);
UpdateMailboxContent (mMailboxPointer, DEBUG_MAILBOX_DEBUG_PORT_HANDLE_INDEX, DebugPortHandle);
if (Mailbox == NULL) {
//
// Trigger one software interrupt to inform HOST
//
TriggerSoftInterrupt (SYSTEM_RESET_SIGNATURE);
SetDebugFlag (DEBUG_AGENT_FLAG_MEMORY_READY, 1);
//
// Memory has been ready
//
if (IsHostAttached ()) {
//
// Trigger one software interrupt to inform HOST
//
TriggerSoftInterrupt (MEMORY_READY_SIGNATURE);
}
}
}
/**
Initialize debug agent.
This function is used to set up debug enviroment for DXE phase.
If this function is called by DXE Core, Context must be the pointer
to HOB list which will be used to get GUIDed HOB. It will enable
interrupt to support break-in feature.
If this function is called by DXE module, Context must be NULL. It
will enable interrupt to support break-in feature.
@param[in] InitFlag Init flag is used to decide initialize process.
@param[in] Context Context needed according to InitFlag.
@param[in] Function Continue function called by debug agent library; it was
optional.
**/
VOID
EFIAPI
InitializeDebugAgent (
IN UINT32 InitFlag,
IN VOID *Context, OPTIONAL
IN DEBUG_AGENT_CONTINUE Function OPTIONAL
)
{
DEBUG_AGENT_MAILBOX *Mailbox;
IA32_DESCRIPTOR Idtr;
UINT16 IdtEntryCount;
BOOLEAN InterruptStatus;
if (InitFlag != DEBUG_AGENT_INIT_DXE_CORE &&
InitFlag != DEBUG_AGENT_INIT_S3 &&
InitFlag != DEBUG_AGENT_INIT_DXE_AP) {
return;
}
//
// Save and disable original interrupt status
//
InterruptStatus = SaveAndDisableInterrupts ();
if (InitFlag == DEBUG_AGENT_INIT_DXE_CORE) {
//
// Try to get Mailbox from GUIDed HOB.
//
mDxeCoreFlag = TRUE;
Mailbox = GetMailboxFromHob (Context);
//
// Clear Break CPU index value
//
mDebugMpContext.BreakAtCpuIndex = (UINT32) -1;
} else if (InitFlag == DEBUG_AGENT_INIT_DXE_AP) {
EnableInterrupts ();
return;
} else {
//
// If it is in S3 path, needn't to install configuration table.
//
Mailbox = NULL;
}
if (Mailbox != NULL) {
//
// If Mailbox exists, copy it into one global variable.
//
CopyMem (&mMailbox, Mailbox, sizeof (DEBUG_AGENT_MAILBOX));
} else {
//
// If Mailbox not exists, used the local Mailbox.
//
ZeroMem (&mMailbox, sizeof (DEBUG_AGENT_MAILBOX));
}
mMailboxPointer = &mMailbox;
//
// Get original IDT address and size.
//
AsmReadIdtr ((IA32_DESCRIPTOR *) &Idtr);
IdtEntryCount = (UINT16) ((Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR));
if (IdtEntryCount < 33) {
Idtr.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 33 - 1);
Idtr.Base = (UINTN) &mIdtEntryTable;
ZeroMem (&mIdtEntryTable, Idtr.Limit + 1);
AsmWriteIdtr ((IA32_DESCRIPTOR *) &Idtr);
}
//
// Initialize the IDT table entries to support source level debug.
//
InitializeDebugIdt ();
//
// Initialize debug communication port
//
mMailboxPointer->DebugPortHandle = (UINT64) (UINTN)DebugPortInitialize ((VOID *)(UINTN)mMailbox.DebugPortHandle, NULL);
InitializeSpinLock (&mDebugMpContext.MpContextSpinLock);
InitializeSpinLock (&mDebugMpContext.DebugPortSpinLock);
if (InitFlag == DEBUG_AGENT_INIT_DXE_CORE) {
//
// Initialize Debug Timer hardware and enable interrupt.
//
InitializeDebugTimer ();
EnableInterrupts ();
return;
} else {
//
// Disable Debug Timer interrupt in S3 path.
//
SaveAndSetDebugTimerInterrupt (FALSE);
//
// Restore interrupt state.
//
SetInterruptState (InterruptStatus);
}
}