static void b43_phy_ht_stop_playback(struct b43_wldev *dev) { struct b43_phy_ht *phy_ht = dev->phy.ht; u16 tmp; int i; tmp = b43_phy_read(dev, B43_PHY_HT_SAMP_STAT); if (tmp & 0x1) b43_phy_set(dev, B43_PHY_HT_SAMP_CMD, B43_PHY_HT_SAMP_CMD_STOP); else if (tmp & 0x2) b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, 0x7FFF); b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0x0004); for (i = 0; i < 3; i++) { if (phy_ht->bb_mult_save[i] >= 0) { b43_httab_write(dev, B43_HTTAB16(13, 0x63 + i * 4), phy_ht->bb_mult_save[i]); b43_httab_write(dev, B43_HTTAB16(13, 0x67 + i * 4), phy_ht->bb_mult_save[i]); } } }
static void b43_phy_ht_channel_setup(struct b43_wldev *dev, const struct b43_phy_ht_channeltab_e_phy *e, struct ieee80211_channel *new_channel) { bool old_band_5ghz; u8 i; old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */ if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) { /* TODO */ } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) { /* TODO */ } b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1); b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2); b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3); b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4); b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5); b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6); /* TODO: some ops on PHY regs 0x0B0 and 0xC0A */ /* TODO: separated function? */ for (i = 0; i < 3; i++) { u16 mask; u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8)); if (0) /* FIXME */ mask = 0x2 << (i * 4); else mask = 0; b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask); b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16); b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)), tmp & 0xFF); b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)), tmp & 0xFF); } b43_phy_write(dev, 0x017e, 0x3830); }
/* Some unknown AFE (Analog Frondned) op */ static void b43_phy_ht_afe_unk1(struct b43_wldev *dev) { u8 i; const u16 ctl_regs[3][2] = { { B43_PHY_HT_AFE_CTL1, B43_PHY_HT_AFE_CTL2 }, { B43_PHY_HT_AFE_CTL3, B43_PHY_HT_AFE_CTL4 }, { B43_PHY_HT_AFE_CTL5, B43_PHY_HT_AFE_CTL6}, }; for (i = 0; i < 3; i++) { /* TODO: verify masks&sets */ b43_phy_set(dev, ctl_regs[i][1], 0x4); b43_phy_set(dev, ctl_regs[i][0], 0x4); b43_phy_mask(dev, ctl_regs[i][1], ~0x1); b43_phy_set(dev, ctl_regs[i][0], 0x1); b43_httab_write(dev, B43_HTTAB16(8, 5 + (i * 0x10)), 0); b43_phy_mask(dev, ctl_regs[i][0], ~0x4); } }
static void b43_phy_ht_tx_power_fix(struct b43_wldev *dev) { int i; for (i = 0; i < 3; i++) { u16 mask; u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8)); if (0) /* FIXME */ mask = 0x2 << (i * 4); else mask = 0; b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask); b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16); b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)), tmp & 0xFF); b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)), tmp & 0xFF); } }
static void b43_phy_ht_run_samples(struct b43_wldev *dev, u16 samps, u16 loops, u16 wait) { struct b43_phy_ht *phy_ht = dev->phy.ht; u16 save_seq_mode; int i; for (i = 0; i < 3; i++) { if (phy_ht->bb_mult_save[i] < 0) phy_ht->bb_mult_save[i] = b43_httab_read(dev, B43_HTTAB16(13, 0x63 + i * 4)); } b43_phy_write(dev, B43_PHY_HT_SAMP_DEP_CNT, samps - 1); if (loops != 0xFFFF) loops--; b43_phy_write(dev, B43_PHY_HT_SAMP_LOOP_CNT, loops); b43_phy_write(dev, B43_PHY_HT_SAMP_WAIT_CNT, wait); save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE); b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE, B43_PHY_HT_RF_SEQ_MODE_CA_OVER); /* TODO: find out mask bits! Do we need more function arguments? */ b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0); b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0); b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, ~0); b43_phy_set(dev, B43_PHY_HT_SAMP_CMD, 0x1); for (i = 0; i < 100; i++) { if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & 1)) { i = 0; break; } udelay(10); } if (i) b43err(dev->wl, "run samples timeout\n"); b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode); }
static int b43_phy_ht_op_init(struct b43_wldev *dev) { u16 tmp; u16 clip_state[3]; b43_phy_ht_tables_init(dev); b43_phy_mask(dev, 0x0be, ~0x2); b43_phy_set(dev, 0x23f, 0x7ff); b43_phy_set(dev, 0x240, 0x7ff); b43_phy_set(dev, 0x241, 0x7ff); b43_phy_ht_zero_extg(dev); b43_phy_mask(dev, B43_PHY_EXTG(0), ~0x3); b43_phy_write(dev, B43_PHY_HT_AFE_CTL1, 0); b43_phy_write(dev, B43_PHY_HT_AFE_CTL3, 0); b43_phy_write(dev, B43_PHY_HT_AFE_CTL5, 0); b43_phy_write(dev, B43_PHY_EXTG(0x103), 0x20); b43_phy_write(dev, B43_PHY_EXTG(0x101), 0x20); b43_phy_write(dev, 0x20d, 0xb8); b43_phy_write(dev, B43_PHY_EXTG(0x14f), 0xc8); b43_phy_write(dev, 0x70, 0x50); b43_phy_write(dev, 0x1ff, 0x30); if (0) /* TODO: condition */ ; /* TODO: PHY op on reg 0x217 */ b43_phy_read(dev, 0xb0); /* TODO: what for? */ b43_phy_set(dev, 0xb0, 0x1); b43_phy_set(dev, 0xb1, 0x91); b43_phy_write(dev, 0x32f, 0x0003); b43_phy_write(dev, 0x077, 0x0010); b43_phy_write(dev, 0x0b4, 0x0258); b43_phy_mask(dev, 0x17e, ~0x4000); b43_phy_write(dev, 0x0b9, 0x0072); b43_httab_write_few(dev, B43_HTTAB16(7, 0x14e), 2, 0x010f, 0x010f); b43_httab_write_few(dev, B43_HTTAB16(7, 0x15e), 2, 0x010f, 0x010f); b43_httab_write_few(dev, B43_HTTAB16(7, 0x16e), 2, 0x010f, 0x010f); b43_phy_ht_afe_unk1(dev); b43_httab_write_few(dev, B43_HTTAB16(7, 0x130), 9, 0x777, 0x111, 0x111, 0x777, 0x111, 0x111, 0x777, 0x111, 0x111); b43_httab_write(dev, B43_HTTAB16(7, 0x120), 0x0777); b43_httab_write(dev, B43_HTTAB16(7, 0x124), 0x0777); b43_httab_write(dev, B43_HTTAB16(8, 0x00), 0x02); b43_httab_write(dev, B43_HTTAB16(8, 0x10), 0x02); b43_httab_write(dev, B43_HTTAB16(8, 0x20), 0x02); b43_httab_write_few(dev, B43_HTTAB16(8, 0x08), 4, 0x8e, 0x96, 0x96, 0x96); b43_httab_write_few(dev, B43_HTTAB16(8, 0x18), 4, 0x8f, 0x9f, 0x9f, 0x9f); b43_httab_write_few(dev, B43_HTTAB16(8, 0x28), 4, 0x8f, 0x9f, 0x9f, 0x9f); b43_httab_write_few(dev, B43_HTTAB16(8, 0x0c), 4, 0x2, 0x2, 0x2, 0x2); b43_httab_write_few(dev, B43_HTTAB16(8, 0x1c), 4, 0x2, 0x2, 0x2, 0x2); b43_httab_write_few(dev, B43_HTTAB16(8, 0x2c), 4, 0x2, 0x2, 0x2, 0x2); b43_phy_maskset(dev, 0x0280, 0xff00, 0x3e); b43_phy_maskset(dev, 0x0283, 0xff00, 0x3e); b43_phy_maskset(dev, B43_PHY_OFDM(0x0141), 0xff00, 0x46); b43_phy_maskset(dev, 0x0283, 0xff00, 0x40); b43_httab_write_few(dev, B43_HTTAB16(00, 0x8), 4, 0x09, 0x0e, 0x13, 0x18); b43_httab_write_few(dev, B43_HTTAB16(01, 0x8), 4, 0x09, 0x0e, 0x13, 0x18); /* TODO: Did wl mean 2 instead of 40? */ b43_httab_write_few(dev, B43_HTTAB16(40, 0x8), 4, 0x09, 0x0e, 0x13, 0x18); b43_phy_maskset(dev, B43_PHY_OFDM(0x24), 0x3f, 0xd); b43_phy_maskset(dev, B43_PHY_OFDM(0x64), 0x3f, 0xd); b43_phy_maskset(dev, B43_PHY_OFDM(0xa4), 0x3f, 0xd); b43_phy_set(dev, B43_PHY_EXTG(0x060), 0x1); b43_phy_set(dev, B43_PHY_EXTG(0x064), 0x1); b43_phy_set(dev, B43_PHY_EXTG(0x080), 0x1); b43_phy_set(dev, B43_PHY_EXTG(0x084), 0x1); /* Copy some tables entries */ tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x144)); b43_httab_write(dev, B43_HTTAB16(7, 0x14a), tmp); tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x154)); b43_httab_write(dev, B43_HTTAB16(7, 0x15a), tmp); tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x164)); b43_httab_write(dev, B43_HTTAB16(7, 0x16a), tmp); /* Reset CCA */ b43_phy_force_clock(dev, true); tmp = b43_phy_read(dev, B43_PHY_HT_BBCFG); b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp | B43_PHY_HT_BBCFG_RSTCCA); b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp & ~B43_PHY_HT_BBCFG_RSTCCA); b43_phy_force_clock(dev, false); b43_mac_phy_clock_set(dev, true); b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RX2TX); b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX); /* TODO: PHY op on reg 0xb0 */ /* TODO: Should we restore it? Or store it in global PHY info? */ b43_phy_ht_read_clip_detection(dev, clip_state); if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) b43_phy_ht_bphy_init(dev); b43_httab_write_bulk(dev, B43_HTTAB32(0x1a, 0xc0), B43_HTTAB_1A_C0_LATE_SIZE, b43_httab_0x1a_0xc0_late); return 0; }
static int b43_phy_ht_op_init(struct b43_wldev *dev) { struct b43_phy_ht *phy_ht = dev->phy.ht; u16 tmp; u16 clip_state[3]; bool saved_tx_pwr_ctl; if (dev->dev->bus_type != B43_BUS_BCMA) { b43err(dev->wl, "HT-PHY is supported only on BCMA bus!\n"); return -EOPNOTSUPP; } b43_phy_ht_tables_init(dev); b43_phy_mask(dev, 0x0be, ~0x2); b43_phy_set(dev, 0x23f, 0x7ff); b43_phy_set(dev, 0x240, 0x7ff); b43_phy_set(dev, 0x241, 0x7ff); b43_phy_ht_zero_extg(dev); b43_phy_mask(dev, B43_PHY_EXTG(0), ~0x3); b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0); b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0); b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0); b43_phy_write(dev, B43_PHY_EXTG(0x103), 0x20); b43_phy_write(dev, B43_PHY_EXTG(0x101), 0x20); b43_phy_write(dev, 0x20d, 0xb8); b43_phy_write(dev, B43_PHY_EXTG(0x14f), 0xc8); b43_phy_write(dev, 0x70, 0x50); b43_phy_write(dev, 0x1ff, 0x30); if (0) /* TODO: condition */ ; /* TODO: PHY op on reg 0x217 */ if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN, 0); else b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN, B43_PHY_HT_CLASS_CTL_CCK_EN); b43_phy_set(dev, 0xb1, 0x91); b43_phy_write(dev, 0x32f, 0x0003); b43_phy_write(dev, 0x077, 0x0010); b43_phy_write(dev, 0x0b4, 0x0258); b43_phy_mask(dev, 0x17e, ~0x4000); b43_phy_write(dev, 0x0b9, 0x0072); b43_httab_write_few(dev, B43_HTTAB16(7, 0x14e), 2, 0x010f, 0x010f); b43_httab_write_few(dev, B43_HTTAB16(7, 0x15e), 2, 0x010f, 0x010f); b43_httab_write_few(dev, B43_HTTAB16(7, 0x16e), 2, 0x010f, 0x010f); b43_phy_ht_afe_unk1(dev); b43_httab_write_few(dev, B43_HTTAB16(7, 0x130), 9, 0x777, 0x111, 0x111, 0x777, 0x111, 0x111, 0x777, 0x111, 0x111); b43_httab_write(dev, B43_HTTAB16(7, 0x120), 0x0777); b43_httab_write(dev, B43_HTTAB16(7, 0x124), 0x0777); b43_httab_write(dev, B43_HTTAB16(8, 0x00), 0x02); b43_httab_write(dev, B43_HTTAB16(8, 0x10), 0x02); b43_httab_write(dev, B43_HTTAB16(8, 0x20), 0x02); b43_httab_write_few(dev, B43_HTTAB16(8, 0x08), 4, 0x8e, 0x96, 0x96, 0x96); b43_httab_write_few(dev, B43_HTTAB16(8, 0x18), 4, 0x8f, 0x9f, 0x9f, 0x9f); b43_httab_write_few(dev, B43_HTTAB16(8, 0x28), 4, 0x8f, 0x9f, 0x9f, 0x9f); b43_httab_write_few(dev, B43_HTTAB16(8, 0x0c), 4, 0x2, 0x2, 0x2, 0x2); b43_httab_write_few(dev, B43_HTTAB16(8, 0x1c), 4, 0x2, 0x2, 0x2, 0x2); b43_httab_write_few(dev, B43_HTTAB16(8, 0x2c), 4, 0x2, 0x2, 0x2, 0x2); b43_phy_maskset(dev, 0x0280, 0xff00, 0x3e); b43_phy_maskset(dev, 0x0283, 0xff00, 0x3e); b43_phy_maskset(dev, B43_PHY_OFDM(0x0141), 0xff00, 0x46); b43_phy_maskset(dev, 0x0283, 0xff00, 0x40); b43_httab_write_few(dev, B43_HTTAB16(00, 0x8), 4, 0x09, 0x0e, 0x13, 0x18); b43_httab_write_few(dev, B43_HTTAB16(01, 0x8), 4, 0x09, 0x0e, 0x13, 0x18); /* TODO: Did wl mean 2 instead of 40? */ b43_httab_write_few(dev, B43_HTTAB16(40, 0x8), 4, 0x09, 0x0e, 0x13, 0x18); b43_phy_maskset(dev, B43_PHY_OFDM(0x24), 0x3f, 0xd); b43_phy_maskset(dev, B43_PHY_OFDM(0x64), 0x3f, 0xd); b43_phy_maskset(dev, B43_PHY_OFDM(0xa4), 0x3f, 0xd); b43_phy_set(dev, B43_PHY_EXTG(0x060), 0x1); b43_phy_set(dev, B43_PHY_EXTG(0x064), 0x1); b43_phy_set(dev, B43_PHY_EXTG(0x080), 0x1); b43_phy_set(dev, B43_PHY_EXTG(0x084), 0x1); /* Copy some tables entries */ tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x144)); b43_httab_write(dev, B43_HTTAB16(7, 0x14a), tmp); tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x154)); b43_httab_write(dev, B43_HTTAB16(7, 0x15a), tmp); tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x164)); b43_httab_write(dev, B43_HTTAB16(7, 0x16a), tmp); /* Reset CCA */ b43_phy_force_clock(dev, true); tmp = b43_phy_read(dev, B43_PHY_HT_BBCFG); b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp | B43_PHY_HT_BBCFG_RSTCCA); b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp & ~B43_PHY_HT_BBCFG_RSTCCA); b43_phy_force_clock(dev, false); b43_mac_phy_clock_set(dev, true); b43_phy_ht_pa_override(dev, false); b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RX2TX); b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX); b43_phy_ht_pa_override(dev, true); /* TODO: Should we restore it? Or store it in global PHY info? */ b43_phy_ht_classifier(dev, 0, 0); b43_phy_ht_read_clip_detection(dev, clip_state); if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) b43_phy_ht_bphy_init(dev); b43_httab_write_bulk(dev, B43_HTTAB32(0x1a, 0xc0), B43_HTTAB_1A_C0_LATE_SIZE, b43_httab_0x1a_0xc0_late); saved_tx_pwr_ctl = phy_ht->tx_pwr_ctl; b43_phy_ht_tx_power_fix(dev); b43_phy_ht_tx_power_ctl(dev, false); b43_phy_ht_tx_power_ctl_idle_tssi(dev); b43_phy_ht_tx_power_ctl_setup(dev); b43_phy_ht_tx_power_ctl(dev, saved_tx_pwr_ctl); return 0; }
static void b43_phy_ht_tx_power_ctl_setup(struct b43_wldev *dev) { struct b43_phy_ht *phy_ht = dev->phy.ht; struct ssb_sprom *sprom = dev->dev->bus_sprom; u8 *idle = phy_ht->idle_tssi; u8 target[3]; s16 a1[3], b0[3], b1[3]; u16 freq = dev->phy.channel_freq; int i, c; if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { for (c = 0; c < 3; c++) { target[c] = sprom->core_pwr_info[c].maxpwr_2g; a1[c] = sprom->core_pwr_info[c].pa_2g[0]; b0[c] = sprom->core_pwr_info[c].pa_2g[1]; b1[c] = sprom->core_pwr_info[c].pa_2g[2]; } } else if (freq >= 4900 && freq < 5100) { for (c = 0; c < 3; c++) { target[c] = sprom->core_pwr_info[c].maxpwr_5gl; a1[c] = sprom->core_pwr_info[c].pa_5gl[0]; b0[c] = sprom->core_pwr_info[c].pa_5gl[1]; b1[c] = sprom->core_pwr_info[c].pa_5gl[2]; } } else if (freq >= 5100 && freq < 5500) { for (c = 0; c < 3; c++) { target[c] = sprom->core_pwr_info[c].maxpwr_5g; a1[c] = sprom->core_pwr_info[c].pa_5g[0]; b0[c] = sprom->core_pwr_info[c].pa_5g[1]; b1[c] = sprom->core_pwr_info[c].pa_5g[2]; } } else if (freq >= 5500) { for (c = 0; c < 3; c++) { target[c] = sprom->core_pwr_info[c].maxpwr_5gh; a1[c] = sprom->core_pwr_info[c].pa_5gh[0]; b0[c] = sprom->core_pwr_info[c].pa_5gh[1]; b1[c] = sprom->core_pwr_info[c].pa_5gh[2]; } } else { target[0] = target[1] = target[2] = 52; a1[0] = a1[1] = a1[2] = -424; b0[0] = b0[1] = b0[2] = 5612; b1[0] = b1[1] = b1[2] = -1393; } b43_phy_set(dev, B43_PHY_HT_TSSIMODE, B43_PHY_HT_TSSIMODE_EN); b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1, ~B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN & 0xFFFF); /* TODO: Does it depend on sprom->fem.ghz2.tssipos? */ b43_phy_set(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI, 0x4000); b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1, ~B43_PHY_HT_TXPCTL_CMD_C1_INIT, 0x19); b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C2, ~B43_PHY_HT_TXPCTL_CMD_C2_INIT, 0x19); b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C3, ~B43_PHY_HT_TXPCTL_CMD_C3_INIT, 0x19); b43_phy_set(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI, B43_PHY_HT_TXPCTL_IDLE_TSSI_BINF); b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI, ~B43_PHY_HT_TXPCTL_IDLE_TSSI_C1, idle[0] << B43_PHY_HT_TXPCTL_IDLE_TSSI_C1_SHIFT); b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI, ~B43_PHY_HT_TXPCTL_IDLE_TSSI_C2, idle[1] << B43_PHY_HT_TXPCTL_IDLE_TSSI_C2_SHIFT); b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI2, ~B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3, idle[2] << B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3_SHIFT); b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_N, ~B43_PHY_HT_TXPCTL_N_TSSID, 0xf0); b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_N, ~B43_PHY_HT_TXPCTL_N_NPTIL2, 0x3 << B43_PHY_HT_TXPCTL_N_NPTIL2_SHIFT); #if 0 /* TODO: what to mask/set? */ b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1, 0x800, 0) b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1, 0x400, 0) #endif b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR, ~B43_PHY_HT_TXPCTL_TARG_PWR_C1, target[0] << B43_PHY_HT_TXPCTL_TARG_PWR_C1_SHIFT); b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR, ~B43_PHY_HT_TXPCTL_TARG_PWR_C2 & 0xFFFF, target[1] << B43_PHY_HT_TXPCTL_TARG_PWR_C2_SHIFT); b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR2, ~B43_PHY_HT_TXPCTL_TARG_PWR2_C3, target[2] << B43_PHY_HT_TXPCTL_TARG_PWR2_C3_SHIFT); for (c = 0; c < 3; c++) { s32 num, den, pwr; u32 regval[64]; for (i = 0; i < 64; i++) { num = 8 * (16 * b0[c] + b1[c] * i); den = 32768 + a1[c] * i; pwr = max((4 * num + den / 2) / den, -8); regval[i] = pwr; } b43_httab_write_bulk(dev, B43_HTTAB16(26 + c, 0), 64, regval); } }