static void lradc_keypad_hwinit () { /* Clear the Clock Gate and SFTRST for normal operation */ HW_LRADC_CTRL0_CLR(BM_LRADC_CTRL0_SFTRST); HW_LRADC_CTRL0_CLR(BM_LRADC_CTRL0_CLKGATE); /* Disable on-chip ground reference */ HW_LRADC_CTRL0_CLR(BM_LRADC_CTRL0_ONCHIP_GROUNDREF); /* Configure 6Mhz frequency */ HW_LRADC_CTRL3_CLR(BM_LRADC_CTRL3_CYCLE_TIME); HW_LRADC_CTRL3_SET(BF_LRADC_CTRL3_CYCLE_TIME(LRADC_CLOCK_6MHZ)); /* Select VddIO input on channel 6 */ HW_LRADC_CTRL4_CLR(BM_LRADC_CTRL4_LRADC6SELECT); HW_LRADC_CTRL4_SET(BF_LRADC_CTRL4_LRADC6SELECT(lradc_vddio_ch)); /* * Clear the divide by two for channel 6 since it has a HW * divide-by-two built in, and enable this feature for the * button channel */ HW_LRADC_CTRL2_CLR(BF_LRADC_CTRL2_DIVIDE_BY_TWO(1<<VDDIO_VOLTAGE_CH)); HW_LRADC_CTRL2_SET(BF_LRADC_CTRL2_DIVIDE_BY_TWO(1<<lradc_keypad_ch)); /* Clear the accumulator & NUM_SAMPLES */ HW_LRADC_CHn_CLR(VDDIO_VOLTAGE_CH, 0xFFFFFFFF); HW_LRADC_CHn_CLR(lradc_keypad_ch, 0xFFFFFFFF); }
void hw_lradc_configure_channel(int channel, int enable_div2, int enable_acc, int samples) { if (enable_div2) __raw_writel(BF_LRADC_CTRL2_DIVIDE_BY_TWO(1 << channel), mxs_lradc.base + HW_LRADC_CTRL2_SET); else __raw_writel(BF_LRADC_CTRL2_DIVIDE_BY_TWO(1 << channel), mxs_lradc.base + HW_LRADC_CTRL2_CLR); /* Clear the accumulator & NUM_SAMPLES */ __raw_writel(0xFFFFFFFF, mxs_lradc.base + HW_LRADC_CHn_CLR(channel)); /* Sets NUM_SAMPLES bitfield of HW_LRADC_CHn register. */ __raw_writel(BM_LRADC_CHn_NUM_SAMPLES, mxs_lradc.base + HW_LRADC_CHn_CLR(channel)); __raw_writel(BF_LRADC_CHn_NUM_SAMPLES(samples), mxs_lradc.base + HW_LRADC_CHn_SET(channel)); if (enable_acc) __raw_writel(BM_LRADC_CHn_ACCUMULATE, mxs_lradc.base + HW_LRADC_CHn_SET(channel)); else __raw_writel(BM_LRADC_CHn_ACCUMULATE, mxs_lradc.base + HW_LRADC_CHn_CLR(channel)); }
u32 hw_lradc_vddio(void) { /* Clear the Soft Reset and Clock Gate for normal operation */ __raw_writel(BM_LRADC_CTRL0_SFTRST | BM_LRADC_CTRL0_CLKGATE, mxs_lradc.base + HW_LRADC_CTRL0_CLR); /* * Clear the divide by two for channel 6 since * it has a HW divide-by-two built in. */ __raw_writel(BF_LRADC_CTRL2_DIVIDE_BY_TWO(1 << VDDIO_VOLTAGE_CH), mxs_lradc.base + HW_LRADC_CTRL2_CLR); /* Clear the accumulator & NUM_SAMPLES */ __raw_writel(0xFFFFFFFF, mxs_lradc.base + HW_LRADC_CHn_CLR(VDDIO_VOLTAGE_CH)); /* Clear the interrupt flag */ __raw_writel(BM_LRADC_CTRL1_LRADC6_IRQ, mxs_lradc.base + HW_LRADC_CTRL1_CLR); /* * Get VddIO; this is the max scale value for the button resistor * ladder. * schedule ch 6: */ __raw_writel(BF_LRADC_CTRL0_SCHEDULE(1 << VDDIO_VOLTAGE_CH), mxs_lradc.base + HW_LRADC_CTRL0_SET); /* wait for completion */ while ((__raw_readl(mxs_lradc.base + HW_LRADC_CTRL1) & BM_LRADC_CTRL1_LRADC6_IRQ) != BM_LRADC_CTRL1_LRADC6_IRQ) cpu_relax(); /* Clear the interrupt flag */ __raw_writel(BM_LRADC_CTRL1_LRADC6_IRQ, mxs_lradc.base + HW_LRADC_CTRL1_CLR); /* read ch 6 value. */ return __raw_readl(mxs_lradc.base + HW_LRADC_CHn(VDDIO_VOLTAGE_CH)) & BM_LRADC_CHn_VALUE; }