#include <sys/rman.h>
#include <machine/resource.h>
#include <dev/bhnd/bhnd.h>
#include "bcm_bmipsreg.h"
/*
* BMIPS32 and BMIPS3300 core driver.
*
* These cores are only found on siba(4) chipsets, allowing
* us to assume the availability of siba interrupt registers.
*/
static const struct bhnd_device bcm_bmips_devs[] = {
BHND_DEVICE(BCM, MIPS33, NULL, NULL, BHND_DF_SOC),
BHND_DEVICE_END
};
struct bcm_bmips_softc {
device_t dev;
struct resource *mem_res;
int mem_rid;
};
static int
bcm_bmips_probe(device_t dev)
{
const struct bhnd_device *id;
id = bhnd_device_lookup(dev, bcm_bmips_devs,
#include <dev/bhnd/bhnd.h>
#include <dev/bhnd/bhndvar.h>
#include "chipcreg.h"
#include "chipcvar.h"
#include "chipc_private.h"
devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */
static struct bhnd_device_quirk chipc_quirks[];
/* Supported device identifiers */
static const struct bhnd_device chipc_devices[] = {
BHND_DEVICE(BCM, CC, NULL, chipc_quirks),
BHND_DEVICE_END
};
/* Device quirks table */
static struct bhnd_device_quirk chipc_quirks[] = {
/* HND OTP controller revisions */
BHND_CORE_QUIRK (HWREV_EQ (12), CHIPC_QUIRK_OTP_HND), /* (?) */
BHND_CORE_QUIRK (HWREV_EQ (17), CHIPC_QUIRK_OTP_HND), /* BCM4311 */
BHND_CORE_QUIRK (HWREV_EQ (22), CHIPC_QUIRK_OTP_HND), /* BCM4312 */
/* IPX OTP controller revisions */
BHND_CORE_QUIRK (HWREV_EQ (21), CHIPC_QUIRK_OTP_IPX),
BHND_CORE_QUIRK (HWREV_GTE(23), CHIPC_QUIRK_OTP_IPX),
/* Bus-level quirks when bridged via a PCI host bridge core */
static struct bhnd_device_quirk pci_bridge_quirks[] = {
BHND_DEVICE_QUIRK_END
};
/* Bus-level quirks when bridged via a PCIe host bridge core */
static struct bhnd_device_quirk pcie_bridge_quirks[] = {
BHND_CHIP_QUIRK (4311, HWREV_EQ(2), SIBA_QUIRK_PCIE_D11_SB_TIMEOUT),
BHND_CHIP_QUIRK (4312, HWREV_EQ(0), SIBA_QUIRK_PCIE_D11_SB_TIMEOUT),
BHND_DEVICE_QUIRK_END
};
/* Bus-level quirks specific to a particular host bridge core */
static struct bhnd_device bridge_devs[] = {
BHND_DEVICE(BCM, PCI, NULL, pci_bridge_quirks),
BHND_DEVICE(BCM, PCIE, NULL, pcie_bridge_quirks),
BHND_DEVICE_END
};
static int
siba_bhndb_probe(device_t dev)
{
const struct bhnd_chipid *cid;
int error;
/* Defer to default probe implementation */
if ((error = siba_probe(dev)) > 0)
return (error);
/* Check bus type */
#include "chipcreg.h"
#include "chipcvar.h"
devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */
static const struct resource_spec chipc_rspec[CHIPC_MAX_RSPEC] = {
{ SYS_RES_MEMORY, 0, RF_ACTIVE },
{ -1, -1, 0 }
};
static struct bhnd_device_quirk chipc_quirks[];
/* Supported device identifiers */
static const struct bhnd_device chipc_devices[] = {
BHND_DEVICE(CC, "CC", chipc_quirks),
BHND_DEVICE_END
};
/* Device quirks table */
static struct bhnd_device_quirk chipc_quirks[] = {
{ BHND_HWREV_RANGE (0, 21), CHIPC_QUIRK_ALWAYS_HAS_SPROM },
{ BHND_HWREV_EQ (22), CHIPC_QUIRK_SPROM_CHECK_CST_R22 },
{ BHND_HWREV_RANGE (23, 31), CHIPC_QUIRK_SPROM_CHECK_CST_R23 },
{ BHND_HWREV_GTE (35), CHIPC_QUIRK_SUPPORTS_NFLASH },
BHND_DEVICE_QUIRK_END
};
/* quirk and capability flag convenience macros */
#define CHIPC_QUIRK(_sc, _name) \
