/**
* Return the node number.
* For one case (config registers) these are not the right bit fields.
*/
static int r_node(u32 reg)
{
return BITS(reg, 0, 0x7);
}
int Shift(int i) const {
return i % BITS(BIT_BLOCK);
};
/**
* Return the link number.
* For one case (config registers) these are not the right bit fields.
*/
static int r_link(u32 reg)
{
return BITS(reg, 4, 0x3);
}
int32_t ZAP_decrunch(uint8_t *in, uint8_t *out, uint32_t inlen)
{
struct ZAPdecr zd;
uint8_t *match, *o;
int x, y;
/* initialise state */
zd.bb = 0;
zd.bl = 0;
zd.err = XADERR_OK;
zd.in = in;
zd.i = in + inlen;
o = out + ZAP_getlong(&zd);
zd.sum = ZAP_getlong(&zd);
/* throw away bits up to first set bit */
while (!BIT) if (zd.err) break;
while (o > out) {
if ((x=BITS(2)) == 3) x = BIT ? (BIT ? -1 : (BITS(8)+19)) : (BITS(4)+3);
if (x >= 0) do { PUT(BITS(8)); } while (x-- > 0);
if (o <= out) break;
if ((x = BITS(2)) == 3) {
x = BIT ? (BIT ? -1 : (BITS(8)+20)) : (BITS(4)+4);
if (x >= 0) y = BIT ? (BITS(13)+258) : (BITS(8)+2);
}
else {
if (x) { x++; y = BIT ? (BITS(13)+258) : (BITS(8)+2); }
else { x=1; y = BITS(8)+2; }
}
match = o + y; if (x >= 0) do { PUT(*--match); } while (x-- > 0);
}
/* checksum should be 0 on exit */
if (!zd.err && zd.sum) zd.err = XADERR_CHECKSUM;
return (LONG) zd.err;
}
int Index(int i) const {
return i / BITS(BIT_BLOCK);
};
/*----------------------------------------------------------------------------*/
VOID
rlmUpdateParamsForAP (
P_ADAPTER_T prAdapter,
P_BSS_INFO_T prBssInfo,
BOOLEAN fgUpdateBeacon
)
{
P_LINK_T prStaList;
P_STA_RECORD_T prStaRec;
BOOLEAN fgErpProtectMode, fgSta40mIntolerant;
BOOLEAN fgUseShortPreamble, fgUseShortSlotTime;
ENUM_HT_PROTECT_MODE_T eHtProtectMode;
ENUM_GF_MODE_T eGfOperationMode;
UINT_8 ucHtOpInfo1;
#if CFG_SUPPORT_HOTSPOT_OPTIMIZATION
P_GLUE_INFO_T prGlueInfo;
#endif
ASSERT(prAdapter);
ASSERT(prBssInfo);
if (!IS_BSS_ACTIVE(prBssInfo) ||
prBssInfo->eCurrentOPMode != OP_MODE_ACCESS_POINT) {
return;
}
fgErpProtectMode = FALSE;
eHtProtectMode = HT_PROTECT_MODE_NONE;
eGfOperationMode = GF_MODE_NORMAL;
fgSta40mIntolerant = FALSE;
fgUseShortPreamble = prBssInfo->fgIsShortPreambleAllowed;
fgUseShortSlotTime = TRUE;
ucHtOpInfo1 = (UINT_8) CHNL_EXT_SCN;
prStaList = &prBssInfo->rStaRecOfClientList;
LINK_FOR_EACH_ENTRY(prStaRec, prStaList, rLinkEntry, STA_RECORD_T) {
//ASSERT(prStaRec);
if(!prStaRec){
DBGLOG(P2P, TRACE, ("prStaRec is NULL in rlmUpdateParamsForAP() \n"));
break;
}
if (prStaRec->fgIsInUse && prStaRec->ucStaState == STA_STATE_3 &&
prStaRec->ucNetTypeIndex == prBssInfo->ucNetTypeIndex) {
if (!(prStaRec->ucPhyTypeSet &
(PHY_TYPE_SET_802_11GN | PHY_TYPE_SET_802_11A))) {
/* B-only mode, so mode 1 (ERP protection) */
fgErpProtectMode = TRUE;
}
if (!(prStaRec->ucPhyTypeSet & PHY_TYPE_SET_802_11N)) {
/* BG-only or A-only */
eHtProtectMode = HT_PROTECT_MODE_NON_HT;
}
else if (!(prStaRec->u2HtCapInfo & HT_CAP_INFO_SUP_CHNL_WIDTH)) {
/* 20MHz-only */
/*
The HT Protection field may be set to 20 MHz protection
mode only if the following are true:
¡X All STAs detected (by any means) in the primary channel
and all STAs detected (by any means) in the secondary
channel are HT STAs and all STAs that are members of
this BSS are HT STAs, and
¡X This BSS is a 20/40 MHz BSS, and
¡X There is at least one 20 MHz HT STA associated with this BSS.
*/
if (eHtProtectMode == HT_PROTECT_MODE_NONE &&
prBssInfo->fgAssoc40mBwAllowed) {
eHtProtectMode = HT_PROTECT_MODE_20M;
}
}
if (!(prStaRec->u2HtCapInfo & HT_CAP_INFO_HT_GF)) {
eGfOperationMode = GF_MODE_PROTECT;
}
if (!(prStaRec->u2CapInfo & CAP_INFO_SHORT_PREAMBLE)) {
fgUseShortPreamble = FALSE;
}
if (!(prStaRec->u2CapInfo & CAP_INFO_SHORT_SLOT_TIME)) {
fgUseShortSlotTime = FALSE;
}
if (prStaRec->u2HtCapInfo & HT_CAP_INFO_40M_INTOLERANT) {
fgSta40mIntolerant = TRUE;
}
}
} /* end of LINK_FOR_EACH_ENTRY */
/* Check if HT operation IE about 20/40M bandwidth shall be updated */
if (prBssInfo->eBssSCO != CHNL_EXT_SCN) {
if (/*!LINK_IS_EMPTY(prStaList) && */ !fgSta40mIntolerant &&
!prBssInfo->fgObssActionForcedTo20M &&
!prBssInfo->fgObssBeaconForcedTo20M) {
ucHtOpInfo1 = (UINT_8)
(((UINT_32) prBssInfo->eBssSCO) | HT_OP_INFO1_STA_CHNL_WIDTH);
}
}
#if CFG_SUPPORT_HOTSPOT_OPTIMIZATION
prGlueInfo = prAdapter->prGlueInfo;
if (prGlueInfo->prP2PInfo->u4PsLevel & BITS(8, 15))
fgErpProtectMode = TRUE;
#endif
/* Check if any new parameter may be updated */
if (prBssInfo->fgErpProtectMode != fgErpProtectMode ||
prBssInfo->eHtProtectMode != eHtProtectMode ||
prBssInfo->eGfOperationMode != eGfOperationMode ||
prBssInfo->ucHtOpInfo1 != ucHtOpInfo1 ||
prBssInfo->fgUseShortPreamble != fgUseShortPreamble ||
prBssInfo->fgUseShortSlotTime != fgUseShortSlotTime) {
prBssInfo->fgErpProtectMode = fgErpProtectMode;
prBssInfo->eHtProtectMode = eHtProtectMode;
prBssInfo->eGfOperationMode = eGfOperationMode;
prBssInfo->ucHtOpInfo1 = ucHtOpInfo1;
prBssInfo->fgUseShortPreamble = fgUseShortPreamble;
prBssInfo->fgUseShortSlotTime = fgUseShortSlotTime;
if (fgUseShortSlotTime) {
prBssInfo->u2CapInfo |= CAP_INFO_SHORT_SLOT_TIME;
}
else {
prBssInfo->u2CapInfo &= ~CAP_INFO_SHORT_SLOT_TIME;
}
rlmSyncOperationParams(prAdapter, prBssInfo);
fgUpdateBeacon = TRUE;
}
/* Update Beacon content if related IE content is changed */
if (fgUpdateBeacon) {
bssUpdateBeaconContent(prAdapter, prBssInfo->ucNetTypeIndex);
}
}
/*----------------------------------------------------------------------------*/
WLAN_STATUS
wlanoidSetAddP2PKey(IN P_ADAPTER_T prAdapter,
IN PVOID pvSetBuffer, IN UINT_32 u4SetBufferLen, OUT PUINT_32 pu4SetInfoLen)
{
CMD_802_11_KEY rCmdKey;
P_PARAM_KEY_T prNewKey;
DEBUGFUNC("wlanoidSetAddP2PKey");
DBGLOG(REQ, INFO, ("\n"));
ASSERT(prAdapter);
ASSERT(pvSetBuffer);
ASSERT(pu4SetInfoLen);
prNewKey = (P_PARAM_KEY_T) pvSetBuffer;
/* Verify the key structure length. */
if (prNewKey->u4Length > u4SetBufferLen) {
DBGLOG(REQ, WARN,
("Invalid key structure length (%d) greater than total buffer length (%d)\n",
(UINT_8) prNewKey->u4Length, (UINT_8) u4SetBufferLen));
*pu4SetInfoLen = u4SetBufferLen;
return WLAN_STATUS_INVALID_LENGTH;
}
/* Verify the key material length for key material buffer */
else if (prNewKey->u4KeyLength >
prNewKey->u4Length - OFFSET_OF(PARAM_KEY_T, aucKeyMaterial)) {
DBGLOG(REQ, WARN,
("Invalid key material length (%d)\n", (UINT_8) prNewKey->u4KeyLength));
*pu4SetInfoLen = u4SetBufferLen;
return WLAN_STATUS_INVALID_DATA;
}
/* Exception check */
else if (prNewKey->u4KeyIndex & 0x0fffff00) {
return WLAN_STATUS_INVALID_DATA;
}
/* Exception check, pairwise key must with transmit bit enabled */
else if ((prNewKey->u4KeyIndex & BITS(30, 31)) == IS_UNICAST_KEY) {
return WLAN_STATUS_INVALID_DATA;
} else if (!(prNewKey->u4KeyLength == CCMP_KEY_LEN)
&& !(prNewKey->u4KeyLength == TKIP_KEY_LEN)) {
return WLAN_STATUS_INVALID_DATA;
}
/* Exception check, pairwise key must with transmit bit enabled */
else if ((prNewKey->u4KeyIndex & BITS(30, 31)) == BITS(30, 31)) {
if (((prNewKey->u4KeyIndex & 0xff) != 0) ||
((prNewKey->arBSSID[0] == 0xff) && (prNewKey->arBSSID[1] == 0xff)
&& (prNewKey->arBSSID[2] == 0xff) && (prNewKey->arBSSID[3] == 0xff)
&& (prNewKey->arBSSID[4] == 0xff) && (prNewKey->arBSSID[5] == 0xff))) {
return WLAN_STATUS_INVALID_DATA;
}
}
*pu4SetInfoLen = u4SetBufferLen;
/* fill CMD_802_11_KEY */
kalMemZero(&rCmdKey, sizeof(CMD_802_11_KEY));
rCmdKey.ucAddRemove = 1; /* add */
rCmdKey.ucTxKey = ((prNewKey->u4KeyIndex & IS_TRANSMIT_KEY) == IS_TRANSMIT_KEY) ? 1 : 0;
rCmdKey.ucKeyType = ((prNewKey->u4KeyIndex & IS_UNICAST_KEY) == IS_UNICAST_KEY) ? 1 : 0;
if (kalP2PGetRole(prAdapter->prGlueInfo) == 1) { /* group client */
rCmdKey.ucIsAuthenticator = 0;
} else { /* group owner */
rCmdKey.ucIsAuthenticator = 1;
}
COPY_MAC_ADDR(rCmdKey.aucPeerAddr, prNewKey->arBSSID);
rCmdKey.ucNetType = NETWORK_TYPE_P2P_INDEX;
if (prNewKey->u4KeyLength == CCMP_KEY_LEN)
rCmdKey.ucAlgorithmId = CIPHER_SUITE_CCMP; /* AES */
else if (prNewKey->u4KeyLength == TKIP_KEY_LEN)
rCmdKey.ucAlgorithmId = CIPHER_SUITE_TKIP; /* TKIP */
rCmdKey.ucKeyId = (UINT_8) (prNewKey->u4KeyIndex & 0xff);
rCmdKey.ucKeyLen = (UINT_8) prNewKey->u4KeyLength;
kalMemCopy(rCmdKey.aucKeyMaterial, (PUINT_8) prNewKey->aucKeyMaterial, rCmdKey.ucKeyLen);
return wlanoidSendSetQueryP2PCmd(prAdapter,
CMD_ID_ADD_REMOVE_KEY,
TRUE,
FALSE,
TRUE,
nicCmdEventSetCommon,
NULL,
sizeof(CMD_802_11_KEY),
(PUINT_8) &rCmdKey, pvSetBuffer, u4SetBufferLen);
}
int wwunpack(uint8_t *exe, uint32_t exesz, uint8_t *wwsect, struct cli_exe_section *sects, uint16_t scount, uint32_t pe, int desc) {
uint8_t *structs = wwsect + 0x2a1, *compd, *ccur, *unpd, *ucur, bc;
uint32_t src, srcend, szd, bt, bits;
int error=0, i;
cli_dbgmsg("in wwunpack\n");
while (1) {
if (!CLI_ISCONTAINED(wwsect, sects[scount].rsz, structs, 17)) {
cli_dbgmsg("WWPack: Array of structs out of section\n");
break;
}
src = sects[scount].rva - cli_readint32(structs); /* src delta / dst delta - not used / dwords / end of src */
structs+=8;
szd = cli_readint32(structs) * 4;
structs+=4;
srcend = cli_readint32(structs);
structs+=4;
unpd = ucur = exe+src+srcend+4-szd;
if (!szd || !CLI_ISCONTAINED(exe, exesz, unpd, szd)) {
cli_dbgmsg("WWPack: Compressed data out of file\n");
break;
}
cli_dbgmsg("WWP: src: %x, szd: %x, srcend: %x - %x\n", src, szd, srcend, srcend+4-szd);
if (!(compd = cli_malloc(szd))) {
cli_dbgmsg("WWPack: Unable to allocate memory for compd\n");
break;
}
memcpy(compd, unpd, szd);
memset(unpd, -1, szd); /*FIXME*/
ccur=compd;
RESEED;
while(!error) {
uint32_t backbytes, backsize;
uint8_t saved;
BIT;
if (!bits) { /* BYTE copy */
if(ccur-compd>=szd || !CLI_ISCONTAINED(exe, exesz, ucur, 1))
error=1;
else
*ucur++=*ccur++;
continue;
}
BITS(2);
if(bits==3) { /* WORD backcopy */
uint8_t shifted, subbed = 31;
BITS(2);
shifted = bits + 5;
if(bits>=2) {
shifted++;
subbed += 0x80;
}
backbytes = (1<<shifted)-subbed; /* 1h, 21h, 61h, 161h */
BITS(shifted); /* 5, 6, 8, 9 */
if(error || bits == 0x1ff) break;
backbytes+=bits;
if(!CLI_ISCONTAINED(exe, exesz, ucur, 2) || !CLI_ISCONTAINED(exe, exesz, ucur-backbytes, 2)) {
error=1;
} else {
ucur[0]=*(ucur-backbytes);
ucur[1]=*(ucur-backbytes+1);
ucur+=2;
}
continue;
}
/* BLOCK backcopy */
saved = bits; /* cmp al, 1 / pushf */
BITS(3);
if (bits<6) {
backbytes = bits;
switch(bits) {
case 4: /* 10,11 */
backbytes++;
case 3: /* 8,9 */
BIT;
backbytes+=bits;
case 0: case 1: case 2: /* 5,6,7 */
backbytes+=5;
break;
case 5: /* 12 */
backbytes=12;
break;
}
BITS(backbytes);
bits+=(1<<backbytes)-31;
} else if(bits==6) {
BITS(0x0e);
bits+=0x1fe1;
} else {
BITS(0x0f);
bits+=0x5fe1;
}
backbytes = bits;
/* popf / jb */
if (!saved) {
BIT;
if(!bits) {
BIT;
bits+=5;
} else {
BITS(3);
if(bits) {
bits+=6;
} else {
BITS(4);
if(bits) {
bits+=13;
} else {
uint8_t cnt = 4;
uint16_t shifted = 0x0d;
do {
if(cnt==7) { cnt = 0x0e; shifted = 0; break; }
shifted=((shifted+2)<<1)-1;
BIT;
cnt++;
} while(!bits);
BITS(cnt);
bits+=shifted;
}
}
}
backsize = bits;
} else {
backsize = saved+2;
}
if(!CLI_ISCONTAINED(exe, exesz, ucur, backsize) || !CLI_ISCONTAINED(exe, exesz, ucur-backbytes, backsize)) error=1;
else while(backsize--) {
*ucur=*(ucur-backbytes);
ucur++;
}
}
free(compd);
if(error) {
cli_dbgmsg("WWPack: decompression error\n");
break;
}
if (error || !*structs++) break;
}
if(!error) {
exe[pe+6]=(uint8_t)scount;
exe[pe+7]=(uint8_t)(scount>>8);
cli_writeint32(&exe[pe+0x28], cli_readint32(wwsect+0x295)+sects[scount].rva+0x299);
cli_writeint32(&exe[pe+0x50], cli_readint32(&exe[pe+0x50])-sects[scount].vsz);
structs = &exe[(0xffff&cli_readint32(&exe[pe+0x14]))+pe+0x18];
for(i=0 ; i<scount ; i++) {
if (!CLI_ISCONTAINED(exe, exesz, structs, 0x28)) {
cli_dbgmsg("WWPack: structs pointer out of bounds\n");
return CL_EFORMAT;
}
cli_writeint32(structs+8, sects[i].vsz);
cli_writeint32(structs+12, sects[i].rva);
cli_writeint32(structs+16, sects[i].vsz);
cli_writeint32(structs+20, sects[i].rva);
structs+=0x28;
}
if (!CLI_ISCONTAINED(exe, exesz, structs, 0x28)) {
cli_dbgmsg("WWPack: structs pointer out of bounds\n");
return CL_EFORMAT;
}
memset(structs, 0, 0x28);
error = (uint32_t)cli_writen(desc, exe, exesz)!=exesz;
}
OBJ(name,desc), \
BITS(kn,1,0,0,mgc,0,0,0,0,HARDGEM(mohs),0,-P_SLING,glass), 0, \
OBJ_TYPE_Gem, prob, 0, wt, gval, sdam, ldam, 0, 0, nutr, color )
#define OBJ(name,desc) name,desc
#define BITS(nameknown,merge,usesknown,container,magic,charged,unique,nowish,big,tough,dir,subtype,material) \
nameknown,merge,usesknown,0,magic,charged,unique,nowish,big,tough,dir,material,subtype
#define COLOR_FIELD(X) (X)
#define HARDGEM(n) (n >= 8)
objPrototype g_objectPrototype[] =
{
/* dummy object[0] -- description [2nd arg] *must* be NULL */
OBJECT(OBJ("strange object",(char *)0), BITS(1,0,0,0,0,0,0,0,0,0,0,P_NONE,0),
0, ILLOBJ_CLASS, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
/* missiles */
PROJECTILE("arrow", (char *)0,
1, 55, 1, 2, 6, 6, 0, IRON, -P_BOW, HI_METAL),
PROJECTILE("elven arrow", "runed arrow",
0, 20, 1, 2, 7, 6, 0, WOOD, -P_BOW, HI_WOOD),
PROJECTILE("orcish arrow", "crude arrow",
0, 20, 1, 2, 5, 6, 0, IRON, -P_BOW, CLR_BLACK),
PROJECTILE("silver arrow", (char *)0,
1, 12, 1, 5, 6, 6, 0, SILVER, -P_BOW, HI_SILVER),
PROJECTILE("ya", "bamboo arrow",
0, 15, 1, 4, 7, 7, 1, METAL, -P_BOW, HI_METAL),
PROJECTILE("crossbow bolt", (char *)0,
1, 55, 1, 2, 4, 6, 0, IRON, -P_CROSSBOW, HI_METAL),
void
bitcat(seg *tsp, seg *fsp)
{
boundary tb, fb, n;
long size; /* unsigned is too clumsy here */
uchar *tp, *fp;
int tx, fx, left;
tb = tsp->bounds.start; /* (end of active) target boundary */
fb = fsp->bounds.start; /* (start of) source boundary */
size = tsp->bounds.stop - tb; /* bits still available at target */
n = fsp->bounds.stop - fb; /* bits at source */
if (size > n) size = n; /* bits to be copied */
if (size == 0) return; /* nothing to do */
tsp->bounds.start += size; /* regard the target space as used */
tp = tsp->base + BYTES(tb); /* first byte of target */
fp = fsp->base + BYTES(fb); /* first byte of source */
tx = BITS(tb); /* bits in use at target byte */
fx = BITS(fb); /* bits in use at source byte */
/* If the bit offsets of target and source are the same,
** we don't have to shift chars as we copy them.
** Just take care of any odd bits at the start, then copy entire bytes.
** It's ok to copy ``extra'' bits. There will always be space for them,
** and they'll simply be ignored, or overwritten later.
*/
if (tx == fx) { /* good deal, we're aligned the same */
if (tx) { /* we have used some bits in the 1st byte */
left = BITSPERCHAR - tx; /* how many are still unused */
*tp &= ~Lobits[left]; /* clear the unused bits */
*tp++ |= *fp++ & Lobits[left]; /* or in from the source */
size -= left; /* account for these bits */
}
while (size > 0) { /* Byte or partial byte remains, aligned */
*tp++ = *fp++;
size -= BITSPERCHAR;
}
} else { /* source and target misaligned */
/* We are going to use variable n as a ``one-byte buffer''
** of source bits. We will maintain the invariant that the
** byte contains fx bits from the byte currently addressed by fp,
** and (BITSPERCHAR - fx) bits from the previous byte.
*/
n = *fp++; /* load complete source byte */
if (fx) { /* some bits are in the next byte */
n <<= BITSPERCHAR;
n |= *fp;
n >>= fx;
}
/* Next source byte now complete in n, invariant applies.
**
** Begin by filling out the target byte to a byte boundary,
** so we can complete the copy with the target aligned.
*/
if (tx) { /* partial 1st byte */
left = BITSPERCHAR - tx; /* bits still unused */
*tp &= ~Lobits[left]; /* clear the unused bits */
/* Align and ``or in'' from the source byte */
*tp++ |= (n >> tx) & Lobits[left];
size -= left; /* account for these bits */
/* We just gobbled ``left'' bits from the source byte in n.
** Shift the entire byte over, leaving the unused tx bits
** adjacent to the high order bits of the low byte.
** Load the low byte with the remaining bits from the byte at fp.
** If the new source boundary is into the next byte,
** load as many bits as necessary from there.
** Leave the invariant about fp and n and fx valid.
*/
n <<= BITSPERCHAR;
n |= (((*fp) << fx) & BYTEMASK);
fx += left;
if (fx >= BITSPERCHAR) {
fp++;
fx -= BITSPERCHAR;
if (fx > 0) {
n |= ((*fp) >> (BITSPERCHAR - fx)) & Lobits[fx];
}
}
/* Having now loaded (at least) ``left'' bits into
** the byte buffer in n, shift any excess out,
** replacing them with the corresponding unused bits.
*/
n >>= tx;
n &= BYTEMASK;
}
static void op_cp15_reg_transfer(word ins, void *data)
{
int opcode_1, opcode_2;
int CRn, CRm;
int Rd;
int L;
int cp_num;
reg_t val;
// decode the fields in the instruction
CRm = BITS(ins, 3, 0);
opcode_2 = BITS_SHIFT(ins, 7, 5);
cp_num = BITS_SHIFT(ins, 11, 8);
Rd = BITS_SHIFT(ins, 15, 12);
CRn = BITS_SHIFT(ins, 19, 16);
L = BIT_SET(ins, 20);
opcode_1 = BITS_SHIFT(ins, 23, 21);
CPU_TRACE(5, "\t\top_cp15_reg_transfer: cp_num %d L %d Rd %d CRn %d CRm %d op1 %d op2 %d\n",
cp_num, L, Rd, CRn, CRm, opcode_1, opcode_2);
#if COUNT_ARM_OPS
inc_perf_counter(OP_COP_REG_TRANS);
#endif
/* some coprocessors we dont care about */
switch(CRn) {
case 0: // id register
if(L) {
val = cp15.id;
goto loadval;
}
goto done;
case 1: // system control register
if(L) {
val = cp15.cr1;
goto loadval;
} else {
word newval = get_reg(Rd);
if (newval & (1<<15)) { // armv5 backwards compatibility mode
panic_cpu("backwards compatible PC load mode not supported in armv5 (bit 15 in cr1)\n");
}
/* ignore all the other bits */
/* set high/low vector base */
set_exception_base((newval & (1<<13)) ? 0xffff0000 : 0);
/* load the potentially new mmu config */
mmu_set_flags(newval & MMU_FLAG_MASK);
/* save our config */
cp15.cr1 = newval;
goto done;
}
case 2: // translation table base
if(L) {
val = mmu_get_register(MMU_TRANS_TABLE_REG);
goto loadval;
} else {
mmu_set_register(MMU_TRANS_TABLE_REG, get_reg(Rd));
goto done;
}
case 3: // domain access control
if(L) {
val = mmu_get_register(MMU_DOMAIN_ACCESS_CONTROL_REG);
goto loadval;
} else {
mmu_set_register(MMU_DOMAIN_ACCESS_CONTROL_REG, get_reg(Rd));
goto done;
}
case 4: // unpredictable
goto donothing;
case 5: // fault state register
if(L) {
val = mmu_get_register(MMU_FAULT_STATUS_REG);
goto loadval;
} else {
mmu_set_register(MMU_FAULT_STATUS_REG, get_reg(Rd));
goto done;
}
case 6: // fault address register
if(L) {
val = mmu_get_register(MMU_FAULT_ADDRESS_REG);
goto loadval;
} else {
mmu_set_register(MMU_FAULT_ADDRESS_REG, get_reg(Rd));
goto done;
}
case 7: // cache registers, we only sort of emulate the instruction cache
CPU_TRACE(5, "cache instruction: L %d m %d n %d d %d op1 %d op2 %d\n", L, CRm, CRn, Rd, opcode_1, opcode_2);
if (!L) {
switch(CRm) {
case 0: // wait for interrupt
goto done;
case 5: // various forms of ICache invalidation
case 7: // invalidate Icache + Dcache
flush_all_codepages();
goto done;
case 6: // invalidate dcache
goto done;
case 10: // clean dcache & drain write buffer
goto done;
case 13: // prefetch icache
goto done;
case 14: // clean and invalidate dcache
goto done;
}
} else { // store
switch(CRm) {
case 14: // clean and invalidate dcache
case 10: // clean dcache & drain write buffer
// arm926 special cache routine that makes it easy to clear the entire cache
// since it doesn't really do anything, probably okay to leave it in for all cores
if (opcode_2 == 3) {
// test and clean, side effect is to set the NZ condition
val = 0; // (1<<30);
set_NZ_condition(val);
goto loadval;
}
}
goto donothing;
}
case 8: // tlb flush
if (L) {
switch(CRm) {
case 7: // unified TLB
case 5: // instruction TLB
flush_all_codepages();
// fall through
case 6: // data TLB
mmu_invalidate_tcache();
goto done;
}
}
goto donothing;
case 9: // cache lockdown
goto donothing;
case 10: // tlb lockdown
goto donothing;
case 11:
case 12: // unpredictable
goto donothing;
case 13: // process id register
if(L) {
val = cp15.process_id;
goto loadval;
} else {
cp15.process_id = get_reg(Rd);
goto done;
}
case 14: // reserved
goto donothing;
case 15: // test and debug
goto donothing;
default:
goto donothing;
}
loadval:
if(L && Rd != 15)
put_reg(Rd, val);
goto done;
unsupported:
panic_cpu("reading from or writing to unsupported cp15 control register!\n");
donothing:
if(L && Rd != 15) {
put_reg(Rd, 0);
}
done:
;
}
/* disasm_instr: Analyses instruction at addr, stores
* findings in *state
*/
void __kprobes disasm_instr(unsigned long addr, struct disasm_state *state,
int userspace, struct pt_regs *regs, struct callee_regs *cregs)
{
int fieldA = 0;
int fieldC = 0, fieldCisReg = 0;
uint16_t word1 = 0, word0 = 0;
int subopcode, is_linked, op_format;
uint16_t *ins_ptr;
uint16_t ins_buf[4];
int bytes_not_copied = 0;
memset(state, 0, sizeof(struct disasm_state));
/* This fetches the upper part of the 32 bit instruction
* in both the cases of Little Endian or Big Endian configurations. */
if (userspace) {
bytes_not_copied = copy_from_user(ins_buf,
(const void __user *) addr, 8);
if (bytes_not_copied > 6)
goto fault;
ins_ptr = ins_buf;
} else {
ins_ptr = (uint16_t *) addr;
}
word1 = *((uint16_t *)addr);
state->major_opcode = (word1 >> 11) & 0x1F;
/* Check if the instruction is 32 bit or 16 bit instruction */
if (state->major_opcode < 0x0B) {
if (bytes_not_copied > 4)
goto fault;
state->instr_len = 4;
word0 = *((uint16_t *)(addr+2));
state->words[0] = (word1 << 16) | word0;
} else {
state->instr_len = 2;
state->words[0] = word1;
}
/* Read the second word in case of limm */
word1 = *((uint16_t *)(addr + state->instr_len));
word0 = *((uint16_t *)(addr + state->instr_len + 2));
state->words[1] = (word1 << 16) | word0;
switch (state->major_opcode) {
case op_Bcc:
state->is_branch = 1;
/* unconditional branch s25, conditional branch s21 */
fieldA = (IS_BIT(state->words[0], 16)) ?
FIELD_s25(state->words[0]) :
FIELD_s21(state->words[0]);
state->delay_slot = IS_BIT(state->words[0], 5);
state->target = fieldA + (addr & ~0x3);
state->flow = direct_jump;
break;
case op_BLcc:
if (IS_BIT(state->words[0], 16)) {
/* Branch and Link*/
/* unconditional branch s25, conditional branch s21 */
fieldA = (IS_BIT(state->words[0], 17)) ?
(FIELD_s25(state->words[0]) & ~0x3) :
FIELD_s21(state->words[0]);
state->flow = direct_call;
} else {
/*Branch On Compare */
fieldA = FIELD_s9(state->words[0]) & ~0x3;
state->flow = direct_jump;
}
state->delay_slot = IS_BIT(state->words[0], 5);
state->target = fieldA + (addr & ~0x3);
state->is_branch = 1;
break;
case op_LD: /* LD<zz> a,[b,s9] */
state->write = 0;
state->di = BITS(state->words[0], 11, 11);
if (state->di)
break;
state->x = BITS(state->words[0], 6, 6);
state->zz = BITS(state->words[0], 7, 8);
state->aa = BITS(state->words[0], 9, 10);
state->wb_reg = FIELD_B(state->words[0]);
if (state->wb_reg == REG_LIMM) {
state->instr_len += 4;
state->aa = 0;
state->src1 = state->words[1];
} else {
state->src1 = get_reg(state->wb_reg, regs, cregs);
}
state->src2 = FIELD_s9(state->words[0]);
state->dest = FIELD_A(state->words[0]);
state->pref = (state->dest == REG_LIMM);
break;
case op_ST:
state->write = 1;
state->di = BITS(state->words[0], 5, 5);
if (state->di)
break;
state->aa = BITS(state->words[0], 3, 4);
state->zz = BITS(state->words[0], 1, 2);
state->src1 = FIELD_C(state->words[0]);
if (state->src1 == REG_LIMM) {
state->instr_len += 4;
state->src1 = state->words[1];
} else {
state->src1 = get_reg(state->src1, regs, cregs);
}
state->wb_reg = FIELD_B(state->words[0]);
if (state->wb_reg == REG_LIMM) {
state->aa = 0;
state->instr_len += 4;
state->src2 = state->words[1];
} else {
state->src2 = get_reg(state->wb_reg, regs, cregs);
}
state->src3 = FIELD_s9(state->words[0]);
break;
case op_MAJOR_4:
subopcode = MINOR_OPCODE(state->words[0]);
switch (subopcode) {
case 32: /* Jcc */
case 33: /* Jcc.D */
case 34: /* JLcc */
case 35: /* JLcc.D */
is_linked = 0;
if (subopcode == 33 || subopcode == 35)
state->delay_slot = 1;
if (subopcode == 34 || subopcode == 35)
is_linked = 1;
fieldCisReg = 0;
op_format = BITS(state->words[0], 22, 23);
if (op_format == 0 || ((op_format == 3) &&
(!IS_BIT(state->words[0], 5)))) {
fieldC = FIELD_C(state->words[0]);
if (fieldC == REG_LIMM) {
fieldC = state->words[1];
state->instr_len += 4;
} else {
fieldCisReg = 1;
}
} else if (op_format == 1 || ((op_format == 3)
&& (IS_BIT(state->words[0], 5)))) {
fieldC = FIELD_C(state->words[0]);
} else {
/* op_format == 2 */
fieldC = FIELD_s12(state->words[0]);
}
if (!fieldCisReg) {
state->target = fieldC;
state->flow = is_linked ?
direct_call : direct_jump;
} else {
state->target = get_reg(fieldC, regs, cregs);
state->flow = is_linked ?
indirect_call : indirect_jump;
}
state->is_branch = 1;
break;
case 40: /* LPcc */
if (BITS(state->words[0], 22, 23) == 3) {
/* Conditional LPcc u7 */
fieldC = FIELD_C(state->words[0]);
fieldC = fieldC << 1;
fieldC += (addr & ~0x03);
state->is_branch = 1;
state->flow = direct_jump;
state->target = fieldC;
}
/* For Unconditional lp, next pc is the fall through
* which is updated */
break;
case 48 ... 55: /* LD a,[b,c] */
state->di = BITS(state->words[0], 15, 15);
if (state->di)
break;
state->x = BITS(state->words[0], 16, 16);
state->zz = BITS(state->words[0], 17, 18);
state->aa = BITS(state->words[0], 22, 23);
state->wb_reg = FIELD_B(state->words[0]);
if (state->wb_reg == REG_LIMM) {
state->instr_len += 4;
state->src1 = state->words[1];
} else {
state->src1 = get_reg(state->wb_reg, regs,
cregs);
}
state->src2 = FIELD_C(state->words[0]);
if (state->src2 == REG_LIMM) {
state->instr_len += 4;
state->src2 = state->words[1];
} else {
state->src2 = get_reg(state->src2, regs,
cregs);
}
state->dest = FIELD_A(state->words[0]);
if (state->dest == REG_LIMM)
state->pref = 1;
break;
case 10: /* MOV */
/* still need to check for limm to extract instr len */
/* MOV is special case because it only takes 2 args */
switch (BITS(state->words[0], 22, 23)) {
case 0: /* OP a,b,c */
if (FIELD_C(state->words[0]) == REG_LIMM)
state->instr_len += 4;
break;
case 1: /* OP a,b,u6 */
break;
case 2: /* OP b,b,s12 */
break;
case 3: /* OP.cc b,b,c/u6 */
if ((!IS_BIT(state->words[0], 5)) &&
(FIELD_C(state->words[0]) == REG_LIMM))
state->instr_len += 4;
break;
}
break;
default:
/* Not a Load, Jump or Loop instruction */
/* still need to check for limm to extract instr len */
switch (BITS(state->words[0], 22, 23)) {
case 0: /* OP a,b,c */
if ((FIELD_B(state->words[0]) == REG_LIMM) ||
(FIELD_C(state->words[0]) == REG_LIMM))
state->instr_len += 4;
break;
case 1: /* OP a,b,u6 */
break;
case 2: /* OP b,b,s12 */
break;
case 3: /* OP.cc b,b,c/u6 */
if ((!IS_BIT(state->words[0], 5)) &&
((FIELD_B(state->words[0]) == REG_LIMM) ||
(FIELD_C(state->words[0]) == REG_LIMM)))
state->instr_len += 4;
break;
}
break;
}
break;
/* 16 Bit Instructions */
case op_LD_ADD: /* LD_S|LDB_S|LDW_S a,[b,c] */
state->zz = BITS(state->words[0], 3, 4);
state->src1 = get_reg(FIELD_S_B(state->words[0]), regs, cregs);
state->src2 = get_reg(FIELD_S_C(state->words[0]), regs, cregs);
state->dest = FIELD_S_A(state->words[0]);
break;
case op_ADD_MOV_CMP:
/* check for limm, ignore mov_s h,b (== mov_s 0,b) */
if ((BITS(state->words[0], 3, 4) < 3) &&
(FIELD_S_H(state->words[0]) == REG_LIMM))
state->instr_len += 4;
break;
case op_S:
subopcode = BITS(state->words[0], 5, 7);
switch (subopcode) {
case 0: /* j_s */
case 1: /* j_s.d */
case 2: /* jl_s */
case 3: /* jl_s.d */
state->target = get_reg(FIELD_S_B(state->words[0]),
regs, cregs);
state->delay_slot = subopcode & 1;
state->flow = (subopcode >= 2) ?
direct_call : indirect_jump;
break;
case 7:
switch (BITS(state->words[0], 8, 10)) {
case 4: /* jeq_s [blink] */
case 5: /* jne_s [blink] */
case 6: /* j_s [blink] */
case 7: /* j_s.d [blink] */
state->delay_slot = (subopcode == 7);
state->flow = indirect_jump;
state->target = get_reg(31, regs, cregs);
default:
break;
}
default:
break;
}
break;
case op_LD_S: /* LD_S c, [b, u7] */
state->src1 = get_reg(FIELD_S_B(state->words[0]), regs, cregs);
state->src2 = FIELD_S_u7(state->words[0]);
state->dest = FIELD_S_C(state->words[0]);
break;
case op_LDB_S:
case op_STB_S:
/* no further handling required as byte accesses should not
* cause an unaligned access exception */
state->zz = 1;
break;
case op_LDWX_S: /* LDWX_S c, [b, u6] */
state->x = 1;
/* intentional fall-through */
case op_LDW_S: /* LDW_S c, [b, u6] */
state->zz = 2;
state->src1 = get_reg(FIELD_S_B(state->words[0]), regs, cregs);
state->src2 = FIELD_S_u6(state->words[0]);
state->dest = FIELD_S_C(state->words[0]);
break;
case op_ST_S: /* ST_S c, [b, u7] */
state->write = 1;
state->src1 = get_reg(FIELD_S_C(state->words[0]), regs, cregs);
state->src2 = get_reg(FIELD_S_B(state->words[0]), regs, cregs);
state->src3 = FIELD_S_u7(state->words[0]);
break;
case op_STW_S: /* STW_S c,[b,u6] */
state->write = 1;
state->zz = 2;
state->src1 = get_reg(FIELD_S_C(state->words[0]), regs, cregs);
state->src2 = get_reg(FIELD_S_B(state->words[0]), regs, cregs);
state->src3 = FIELD_S_u6(state->words[0]);
break;
case op_SP: /* LD_S|LDB_S b,[sp,u7], ST_S|STB_S b,[sp,u7] */
/* note: we are ignoring possibility of:
* ADD_S, SUB_S, PUSH_S, POP_S as these should not
* cause unaliged exception anyway */
state->write = BITS(state->words[0], 6, 6);
state->zz = BITS(state->words[0], 5, 5);
if (state->zz)
break; /* byte accesses should not come here */
if (!state->write) {
state->src1 = get_reg(28, regs, cregs);
state->src2 = FIELD_S_u7(state->words[0]);
state->dest = FIELD_S_B(state->words[0]);
} else {
state->src1 = get_reg(FIELD_S_B(state->words[0]), regs,
cregs);
state->src2 = get_reg(28, regs, cregs);
state->src3 = FIELD_S_u7(state->words[0]);
}
break;
case op_GP: /* LD_S|LDB_S|LDW_S r0,[gp,s11/s9/s10] */
/* note: ADD_S r0, gp, s11 is ignored */
state->zz = BITS(state->words[0], 9, 10);
state->src1 = get_reg(26, regs, cregs);
state->src2 = state->zz ? FIELD_S_s10(state->words[0]) :
FIELD_S_s11(state->words[0]);
state->dest = 0;
break;
case op_Pcl: /* LD_S b,[pcl,u10] */
state->src1 = regs->ret & ~3;
state->src2 = FIELD_S_u10(state->words[0]);
state->dest = FIELD_S_B(state->words[0]);
break;
case op_BR_S:
state->target = FIELD_S_s8(state->words[0]) + (addr & ~0x03);
state->flow = direct_jump;
state->is_branch = 1;
break;
case op_B_S:
fieldA = (BITS(state->words[0], 9, 10) == 3) ?
FIELD_S_s7(state->words[0]) :
FIELD_S_s10(state->words[0]);
state->target = fieldA + (addr & ~0x03);
state->flow = direct_jump;
state->is_branch = 1;
break;
case op_BL_S:
state->target = FIELD_S_s13(state->words[0]) + (addr & ~0x03);
state->flow = direct_call;
state->is_branch = 1;
break;
default:
break;
}
if (bytes_not_copied <= (8 - state->instr_len))
return;
fault: state->fault = 1;
}
long add_noise_to_kmers(long L, long num_kmers, word *kmers[MAX_L], double noise_table[MAX_L*4][4][4],
word *noisy_kmers[MAX_L])
{
long i, j, k;
long half_word_size = 4*sizeof(word);
long word_size = 2*half_word_size;
long num_words_in_kmer = ceil(double(L) / double(half_word_size));
long num_bytes_in_kmer = ceil(double(L) / 4.0); // temp - a bit wasteful but easier to make sure it's correct
long num_bytes_in_kmer_ceil; // = 4 * ceil(double(L) / 16.0); // temp - a bit wasteful but easier to make sure it's correct
if(word_size == 32)
num_bytes_in_kmer_ceil = 4 * ceil(double(L) / 16.0); // temp - a bit wasteful but easier to make sure it's correct (4 bytes in word)
else
num_bytes_in_kmer_ceil = 8 * ceil(double(L) / 32.0); // temp - a bit wasteful but easier to make sure it's correct (8 bytes in word)
word cur_nuc;
long last_word_in_kmer = (L-1)%half_word_size+1;
word current_kmer[MAX_L]; // save one kmer
long debug_prints=0;
long add_int = 0;
word ones_mask;
double cumulative_noise_table[MAX_L*4][4][4]; // multiply by 64
double r; // random number
if(word_size == 32)
ones_mask = 0xFFFFFFFF;
else // assume it's 64
ones_mask = 0xFFFFFFFFFFFFFFFF;
if(debug_prints)
{
printf("Start adding noise\n");
fflush(stdout);
}
for(i=0; i<L; i++) // compute cumulative sum
for(j=0; j<4; j++)
{
cumulative_noise_table[i][j][0] = noise_table[i][j][0];
for(k=1; k<4; k++)
cumulative_noise_table[i][j][k] = cumulative_noise_table[i][j][k-1] + noise_table[i][j][k];
}
if(debug_prints)
{
printf("Cumulative Noise MAtrix\n");
for(i=0; i<L; i++) // compute cumulative sum
{
printf("I=%ld: ", i);
for(j=0; j<4; j++)
{
for(k=0; k<4; k++)
printf("%lf, ", cumulative_noise_table[i][j][k]);
printf(" | ");
}
printf("\n");
}
}
for(i = 0; i < num_kmers; i++) // loop on all sequences
{
// printf("Adding noise to kmer %ld\n", i);
// fflush(stdout);
memcpy(noisy_kmers[i], kmers[i], num_bytes_in_kmer_ceil); // first copy without noise
for(j = 0; j < L; j++) // loop on all positions
{
cur_nuc = BITS(kmers[i][j/half_word_size], 2*(j%half_word_size), 2*(j%half_word_size)+1); // get kmer represented as two bits
// printf("---Adding noise to position %ld\n. Cur nuc=%ld. ", j, cur_nuc);
/* printf("Noise Matrix used: [%lf %lf %lf %lf] Cumulative: [%lf %lf %lf %lf]\n",
noise_table[j][cur_nuc][0], noise_table[j][cur_nuc][1],
noise_table[j][cur_nuc][2], noise_table[j][cur_nuc][3],
cumulative_noise_table[j][cur_nuc][0], cumulative_noise_table[j][cur_nuc][1],
cumulative_noise_table[j][cur_nuc][2], cumulative_noise_table[j][cur_nuc][3]);
fflush(stdout);
*/
r = double(rand()) / RAND_MAX; // randomize in [0,1]
// printf(" Randomized r=%lf\n", r);
for(k=0; k<4; k++)
{
// printf("------Try nucleotide %ld ", k);
// fflush(stdout);
if(r <= cumulative_noise_table[j][cur_nuc][k]) // passed
{
// printf("nuc[%ld][%ld] %ld -> %ld\n", i, j, cur_nuc, k);
if(k != cur_nuc) // noisy kmer different from true kmer
{
noisy_kmers[i][j/half_word_size] &= (ones_mask ^ (3UL << (2*(j%half_word_size)))); // get rid of previous nucleotide
noisy_kmers[i][j/half_word_size] ^= (k << (2*(j%half_word_size)));
}
break;
}
}
}
}
if(debug_prints)
for(i = 0; i < num_kmers; i++) // loop on all sequences
{
printf("Kmer %ld: [pure,noisy]\n", i);
print_packed_dna(kmers[i], L, 1);
print_packed_dna(noisy_kmers[i], L, 1);
}
return 0;
} // end of function extract_sub_kmers
int main(int argc, char **argv)
{
I830Rec i830;
I830Ptr pI830 = &i830;
uint32_t dword;
int i;
do_self_tests();
intel_i830rec_init(pI830);
/* printf("%-18s %8s %s\n\n", "register name", "raw value", "description"); */
#if 0 /* enable HDMI audio bits */
dump_reg(SDVOB, "Digital Display Port B Control Register");
dword |= SDVO_ENABLE;
dword |= SDVO_BORDER_ENABLE;
dword |= SDVO_AUDIO_ENABLE;
dword |= SDVO_NULL_PACKETS_DURING_VSYNC;
OUTREG(SDVOB, dword);
dump_reg(PORT_HOTPLUG_EN, "Hot Plug Detect Enable");
OUTREG(PORT_HOTPLUG_EN, dword | AUDIO_HOTPLUG_EN);
dump_reg(VIDEO_DIP_CTL, "Video DIP Control");
dword &= ~(VIDEO_DIP_ENABLE_AVI |
VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
OUTREG(VIDEO_DIP_CTL, dword);
dword |= VIDEO_DIP_ENABLE;
OUTREG(VIDEO_DIP_CTL, dword);
#endif
#if 0 /* disable HDMI audio bits */
dump_reg(SDVOB, "Digital Display Port B Control Register");
dword &= ~SDVO_AUDIO_ENABLE;
dword &= ~SDVO_NULL_PACKETS_DURING_VSYNC;
OUTREG(SDVOB, dword);
#endif
dump_reg(VIDEO_DIP_CTL, "Video DIP Control");
dump_reg(SDVOB, "Digital Display Port B Control Register");
dump_reg(SDVOC, "Digital Display Port C Control Register");
dump_reg(PORT_HOTPLUG_EN, "Hot Plug Detect Enable");
dump_reg(AUD_CONFIG, "Audio Configuration");
dump_reg(AUD_DEBUG, "Audio Debug");
dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
dump_reg(AUD_RID, "Audio Revision ID");
dump_reg(AUD_SUBN_CNT, "Audio Subordinate Node Count");
dump_reg(AUD_FUNC_GRP, "Audio Function Group Type");
dump_reg(AUD_SUBN_CNT2, "Audio Subordinate Node Count");
dump_reg(AUD_GRP_CAP, "Audio Function Group Capabilities");
dump_reg(AUD_PWRST, "Audio Power State");
dump_reg(AUD_SUPPWR, "Audio Supported Power States");
dump_reg(AUD_SID, "Audio Root Node Subsystem ID");
dump_reg(AUD_OUT_CWCAP, "Audio Output Converter Widget Capabilities");
dump_reg(AUD_OUT_PCMSIZE, "Audio PCM Size and Rates");
dump_reg(AUD_OUT_STR, "Audio Stream Formats");
dump_reg(AUD_OUT_DIG_CNVT, "Audio Digital Converter");
dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
dump_reg(AUD_OUT_STR_DESC, "Audio Stream Descriptor Format");
dump_reg(AUD_PINW_CAP, "Audio Pin Complex Widget Capabilities");
dump_reg(AUD_PIN_CAP, "Audio Pin Capabilities");
dump_reg(AUD_PINW_CONNLNG, "Audio Connection List Length");
dump_reg(AUD_PINW_CONNLST, "Audio Connection List Entry");
dump_reg(AUD_PINW_CNTR, "Audio Pin Widget Control");
dump_reg(AUD_PINW_UNSOLRESP, "Audio Unsolicited Response Enable");
dump_reg(AUD_CNTL_ST, "Audio Control State Register");
dump_reg(AUD_PINW_CONFIG, "Audio Configuration Default");
dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
dump_reg(AUD_HDMIW_HDMIEDID, "Audio HDMI Data EDID Block");
dump_reg(AUD_HDMIW_INFOFR, "Audio HDMI Widget Data Island Packet");
dump_reg(AUD_CONV_CHCNT, "Audio Converter Channel Count");
dump_reg(AUD_CTS_ENABLE, "Audio CTS Programming Enable");
printf("\nDetails:\n\n");
dword = INREG(AUD_VID_DID);
printf("AUD_VID_DID vendor id\t\t\t0x%x\n", dword >> 16);
printf("AUD_VID_DID device id\t\t\t0x%x\n", dword & 0xffff);
dword = INREG(AUD_RID);
printf("AUD_RID major revision\t\t\t0x%lx\n", BITS(dword, 23, 20));
printf("AUD_RID minor revision\t\t\t0x%lx\n", BITS(dword, 19, 16));
printf("AUD_RID revision id\t\t\t0x%lx\n", BITS(dword, 15, 8));
printf("AUD_RID stepping id\t\t\t0x%lx\n", BITS(dword, 7, 0));
dword = INREG(SDVOB);
printf("SDVOB enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
printf("SDVOB HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
printf("SDVOB SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
printf("SDVOB null packets\t\t\t%u\n",
!!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
printf("SDVOB audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
dword = INREG(SDVOC);
printf("SDVOC enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
printf("SDVOC HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
printf("SDVOC SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
printf("SDVOC null packets\t\t\t%u\n",
!!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
printf("SDVOC audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
dword = INREG(PORT_HOTPLUG_EN);
printf("PORT_HOTPLUG_EN DisplayPort/HDMI port B\t%ld\n",
BIT(dword, 29)),
printf("PORT_HOTPLUG_EN DisplayPort/HDMI port C\t%ld\n",
BIT(dword, 28)),
printf("PORT_HOTPLUG_EN DisplayPort port D\t%ld\n", BIT(dword, 27)),
printf("PORT_HOTPLUG_EN SDVOB\t\t\t%ld\n", BIT(dword, 26)),
printf("PORT_HOTPLUG_EN SDVOC\t\t\t%ld\n", BIT(dword, 25)),
printf("PORT_HOTPLUG_EN audio\t\t\t%ld\n", BIT(dword, 24)),
printf("PORT_HOTPLUG_EN TV\t\t\t%ld\n", BIT(dword, 23)),
printf("PORT_HOTPLUG_EN CRT\t\t\t%ld\n", BIT(dword, 9)), dword =
INREG(VIDEO_DIP_CTL);
printf("VIDEO_DIP_CTL enable graphics DIP\t%ld\n", BIT(dword, 31)),
printf("VIDEO_DIP_CTL port select\t\t[0x%lx] %s\n",
BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
printf("VIDEO_DIP_CTL DIP buffer trans active\t%lu\n", BIT(dword, 28));
printf("VIDEO_DIP_CTL AVI DIP enabled\t\t%lu\n", BIT(dword, 21));
printf("VIDEO_DIP_CTL vendor DIP enabled\t%lu\n", BIT(dword, 22));
printf("VIDEO_DIP_CTL SPD DIP enabled\t\t%lu\n", BIT(dword, 24));
printf("VIDEO_DIP_CTL DIP buffer index\t\t[0x%lx] %s\n",
BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
printf("VIDEO_DIP_CTL DIP trans freq\t\t[0x%lx] %s\n",
BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
printf("VIDEO_DIP_CTL DIP buffer size\t\t%lu\n", BITS(dword, 11, 8));
printf("VIDEO_DIP_CTL DIP address\t\t%lu\n", BITS(dword, 3, 0));
dword = INREG(AUD_CONFIG);
printf("AUD_CONFIG pixel clock\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
OPNAME(pixel_clock, BITS(dword, 19, 16)));
printf("AUD_CONFIG fabrication enabled\t\t%lu\n", BITS(dword, 2, 2));
printf("AUD_CONFIG professional use allowed\t%lu\n", BIT(dword, 1));
printf("AUD_CONFIG fuse enabled\t\t\t%lu\n", BIT(dword, 0));
dword = INREG(AUD_DEBUG);
printf("AUD_DEBUG function reset\t\t%lu\n", BIT(dword, 0));
dword = INREG(AUD_SUBN_CNT);
printf("AUD_SUBN_CNT starting node number\t0x%lx\n",
BITS(dword, 23, 16));
printf("AUD_SUBN_CNT total number of nodes\t0x%lx\n",
BITS(dword, 7, 0));
dword = INREG(AUD_SUBN_CNT2);
printf("AUD_SUBN_CNT2 starting node number\t0x%lx\n",
BITS(dword, 24, 16));
printf("AUD_SUBN_CNT2 total number of nodes\t0x%lx\n",
BITS(dword, 7, 0));
dword = INREG(AUD_FUNC_GRP);
printf("AUD_FUNC_GRP unsol capable\t\t%lu\n", BIT(dword, 8));
printf("AUD_FUNC_GRP node type\t\t\t0x%lx\n", BITS(dword, 7, 0));
dword = INREG(AUD_GRP_CAP);
printf("AUD_GRP_CAP beep 0\t\t\t%lu\n", BIT(dword, 16));
printf("AUD_GRP_CAP input delay\t\t\t%lu\n", BITS(dword, 11, 8));
printf("AUD_GRP_CAP output delay\t\t%lu\n", BITS(dword, 3, 0));
dword = INREG(AUD_PWRST);
printf("AUD_PWRST device power state\t\t%s\n",
power_state[BITS(dword, 5, 4)]);
printf("AUD_PWRST device power state setting\t%s\n",
power_state[BITS(dword, 1, 0)]);
dword = INREG(AUD_SUPPWR);
printf("AUD_SUPPWR support D0\t\t\t%lu\n", BIT(dword, 0));
printf("AUD_SUPPWR support D1\t\t\t%lu\n", BIT(dword, 1));
printf("AUD_SUPPWR support D2\t\t\t%lu\n", BIT(dword, 2));
printf("AUD_SUPPWR support D3\t\t\t%lu\n", BIT(dword, 3));
dword = INREG(AUD_OUT_CWCAP);
printf("AUD_OUT_CWCAP widget type\t\t0x%lx\n", BITS(dword, 23, 20));
printf("AUD_OUT_CWCAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16));
printf("AUD_OUT_CWCAP channel count\t\t%lu\n",
BITS(dword, 15, 13) * 2 + BIT(dword, 0) + 1);
printf("AUD_OUT_CWCAP L-R swap\t\t\t%lu\n", BIT(dword, 11));
printf("AUD_OUT_CWCAP power control\t\t%lu\n", BIT(dword, 10));
printf("AUD_OUT_CWCAP digital\t\t\t%lu\n", BIT(dword, 9));
printf("AUD_OUT_CWCAP conn list\t\t\t%lu\n", BIT(dword, 8));
printf("AUD_OUT_CWCAP unsol\t\t\t%lu\n", BIT(dword, 7));
printf("AUD_OUT_CWCAP mute\t\t\t%lu\n", BIT(dword, 5));
printf("AUD_OUT_CWCAP format override\t\t%lu\n", BIT(dword, 4));
printf("AUD_OUT_CWCAP amp param override\t%lu\n", BIT(dword, 3));
printf("AUD_OUT_CWCAP out amp present\t\t%lu\n", BIT(dword, 2));
printf("AUD_OUT_CWCAP in amp present\t\t%lu\n", BIT(dword, 1));
dword = INREG(AUD_OUT_DIG_CNVT);
printf("AUD_OUT_DIG_CNVT SPDIF category\t\t0x%lx\n",
BITS(dword, 14, 8));
printf("AUD_OUT_DIG_CNVT SPDIF level\t\t%lu\n", BIT(dword, 7));
printf("AUD_OUT_DIG_CNVT professional\t\t%lu\n", BIT(dword, 6));
printf("AUD_OUT_DIG_CNVT non PCM\t\t%lu\n", BIT(dword, 5));
printf("AUD_OUT_DIG_CNVT copyright asserted\t%lu\n", BIT(dword, 4));
printf("AUD_OUT_DIG_CNVT filter preemphasis\t%lu\n", BIT(dword, 3));
printf("AUD_OUT_DIG_CNVT validity config\t%lu\n", BIT(dword, 2));
printf("AUD_OUT_DIG_CNVT validity flag\t\t%lu\n", BIT(dword, 1));
printf("AUD_OUT_DIG_CNVT digital enable\t\t%lu\n", BIT(dword, 0));
dword = INREG(AUD_OUT_CH_STR);
printf("AUD_OUT_CH_STR stream id\t\t0x%lx\n", BITS(dword, 7, 4));
printf("AUD_OUT_CH_STR lowest channel\t\t0x%lx\n", BITS(dword, 3, 0));
dword = INREG(AUD_OUT_STR_DESC);
printf("AUD_OUT_STR_DESC stream channels\t0x%lx\n", BITS(dword, 3, 0));
dword = INREG(AUD_PINW_CAP);
printf("AUD_PINW_CAP widget type\t\t0x%lx\n", BITS(dword, 23, 20));
printf("AUD_PINW_CAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16));
printf("AUD_PINW_CAP channel count\t\t0x%lx\n",
BITS(dword, 15, 13) * 2 + BIT(dword, 0));
printf("AUD_PINW_CAP HDCP\t\t\t%lu\n", BIT(dword, 12));
printf("AUD_PINW_CAP L-R swap\t\t\t%lu\n", BIT(dword, 11));
printf("AUD_PINW_CAP power control\t\t%lu\n", BIT(dword, 10));
printf("AUD_PINW_CAP digital\t\t\t%lu\n", BIT(dword, 9));
printf("AUD_PINW_CAP conn list\t\t\t%lu\n", BIT(dword, 8));
printf("AUD_PINW_CAP unsol\t\t\t%lu\n", BIT(dword, 7));
printf("AUD_PINW_CAP mute\t\t\t%lu\n", BIT(dword, 5));
printf("AUD_PINW_CAP format override\t\t%lu\n", BIT(dword, 4));
printf("AUD_PINW_CAP amp param override\t\t%lu\n", BIT(dword, 3));
printf("AUD_PINW_CAP out amp present\t\t%lu\n", BIT(dword, 2));
printf("AUD_PINW_CAP in amp present\t\t%lu\n", BIT(dword, 1));
dword = INREG(AUD_PIN_CAP);
printf("AUD_PIN_CAP EAPD\t\t\t%lu\n", BIT(dword, 16));
printf("AUD_PIN_CAP HDMI\t\t\t%lu\n", BIT(dword, 7));
printf("AUD_PIN_CAP output\t\t\t%lu\n", BIT(dword, 4));
printf("AUD_PIN_CAP presence detect\t\t%lu\n", BIT(dword, 2));
dword = INREG(AUD_PINW_CNTR);
printf("AUD_PINW_CNTR mute status\t\t%lu\n", BIT(dword, 8));
printf("AUD_PINW_CNTR out enable\t\t%lu\n", BIT(dword, 6));
printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8));
printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8));
printf("AUD_PINW_CNTR stream type\t\t[0x%lx] %s\n",
BITS(dword, 2, 0), OPNAME(stream_type, BITS(dword, 2, 0)));
dword = INREG(AUD_PINW_UNSOLRESP);
printf("AUD_PINW_UNSOLRESP enable unsol resp\t%lu\n", BIT(dword, 31));
dword = INREG(AUD_CNTL_ST);
printf("AUD_CNTL_ST DIP audio enabled\t\t%lu\n", BIT(dword, 21));
printf("AUD_CNTL_ST DIP ACP enabled\t\t%lu\n", BIT(dword, 22));
printf("AUD_CNTL_ST DIP ISRCx enabled\t\t%lu\n", BIT(dword, 23));
printf("AUD_CNTL_ST DIP port select\t\t[0x%lx] %s\n",
BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
printf("AUD_CNTL_ST DIP buffer index\t\t[0x%lx] %s\n",
BITS(dword, 20, 18), OPNAME(dip_index, BITS(dword, 20, 18)));
printf("AUD_CNTL_ST DIP trans freq\t\t[0x%lx] %s\n",
BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
printf("AUD_CNTL_ST DIP address\t\t\t%lu\n", BITS(dword, 3, 0));
printf("AUD_CNTL_ST CP ready\t\t\t%lu\n", BIT(dword, 15));
printf("AUD_CNTL_ST ELD valid\t\t\t%lu\n", BIT(dword, 14));
printf("AUD_CNTL_ST ELD ack\t\t\t%lu\n", BIT(dword, 4));
printf("AUD_CNTL_ST ELD bufsize\t\t\t%lu\n", BITS(dword, 13, 9));
printf("AUD_CNTL_ST ELD address\t\t\t%lu\n", BITS(dword, 8, 5));
dword = INREG(AUD_HDMIW_STATUS);
printf("AUD_HDMIW_STATUS CDCLK/DOTCLK underrun\t%lu\n", BIT(dword, 31));
printf("AUD_HDMIW_STATUS CDCLK/DOTCLK overrun\t%lu\n", BIT(dword, 30));
printf("AUD_HDMIW_STATUS BCLK/CDCLK underrun\t%lu\n", BIT(dword, 29));
printf("AUD_HDMIW_STATUS BCLK/CDCLK overrun\t%lu\n", BIT(dword, 28));
dword = INREG(AUD_CONV_CHCNT);
printf("AUD_CONV_CHCNT HDMI HBR enabled\t\t%lu\n", BITS(dword, 15, 14));
printf("AUD_CONV_CHCNT HDMI channel count\t%lu\n",
BITS(dword, 11, 8) + 1);
printf("AUD_CONV_CHCNT HDMI channel mapping:\n");
for (i = 0; i < 8; i++) {
OUTREG(AUD_CONV_CHCNT, i);
dword = INREG(AUD_CONV_CHCNT);
printf("\t\t\t\t\t[0x%x] %u => %lu \n", dword, i,
BITS(dword, 7, 4));
}
return 0;
}
void ptp2_apply(struct PTP2_data *data, struct PTP2_trig *trig)
{
volatile unsigned int val_0 = BITS(PTP2_DET_RAMPSTART, data->RAMPSTART) |
BITS(PTP2_DET_RAMPSTEP, data->RAMPSTEP) |
BITS(PTP2_DET_DELAY, data->DELAY) |
BITS(PTP2_DET_AUTO_STOP_BYPASS_ENABLE, data->AUTO_STOP_BYPASS_ENABLE) |
BITS(PTP2_DET_TRIGGER_PUL_DELAY, data->TRIGGER_PUL_DELAY) |
BITS(PTP2_CTRL_ENABLE, data->CTRL_ENABLE) |
BITS(PTP2_DET_ENABLE, data->DET_ENABLE);
volatile unsigned int val_1 = BITS(PTP2_MP0_nCORERESET, trig->mp0_nCORE_RESET) |
BITS(PTP2_MP0_STANDBYWFE, trig->mp0_STANDBY_WFE) |
BITS(PTP2_MP0_STANDBYWFI, trig->mp0_STANDBY_WFI) |
BITS(PTP2_MP0_STANDBYWFIL2, trig->mp0_STANDBY_WFIL2) |
BITS(PTP2_MP1_nCORERESET, trig->mp1_nCORE_RESET) |
BITS(PTP2_MP1_STANDBYWFE, trig->mp1_STANDBY_WFE) |
BITS(PTP2_MP1_STANDBYWFI, trig->mp1_STANDBY_WFI) |
BITS(PTP2_MP1_STANDBYWFIL2, trig->mp1_STANDBY_WFIL2);
ptp2_ctrl_lo[0] = val_0;
ptp2_ctrl_lo[1] = val_1;
ptp2_write(PTP2_CTRL_REG_0, val_0);
ptp2_write(PTP2_CTRL_REG_1, val_1);
//Apply software reset that apply the PTP2 LO value to system
ptp2_write_field(PTP2_CTRL_REG_0, PTP2_DET_SWRST, 1);
udelay(1000);
ptp2_write_field(PTP2_CTRL_REG_0, PTP2_DET_SWRST, 0);
}
//this code is called at cpu reset: don't call it directly!
void initLowLevelCpu(void)
{
UInt32 i;
// Power on I/O
SETBIT(LPC_SYSCON->SYSAHBCLKCTRL,16);
//====== CONFIGURE CLOCK & OSCILLATOR ====//
// Power up system oscillator
CLRBIT(LPC_SYSCON->PDRUNCFG,5); //system oscillator power on
// Use an external oscillator between 1-20 MHz
// SETBIT(LPC_SYSCON->SYSOSCCTRL,0);
// use internal osc ?
CLRBIT(LPC_SYSCON->SYSOSCCTRL,0);
for (i = 0; i < 200; i++)
{
__NOP();
}
// Use system oscillator
LPC_SYSCON->SYSPLLCLKSEL = 0 ;
#ifdef MCU_IS_LPC1311
// Update system oscillator
LPC_SYSCON->SYSPLLCLKUEN = 1;
LPC_SYSCON->SYSPLLCLKUEN = 0;
LPC_SYSCON->SYSPLLCLKUEN = 1;
// Wait oscillator update
while ( !(LPC_SYSCON->SYSPLLCLKUEN & BIT(0)) );
#endif
// Compute M :
//
// M = CPU / OSC
// M = 72MHz / 12MHz
// Compute P :
//
// FCC0 = 2 x P x 72MHz AND 156MHz < FCC0 < 320MHz
//
// P = 2
// FCC0 = 2 x 2 x 72MHz = 288MHz
//
// MUST SET M-1 AND P-1
// Set system pll clock value
LPC_SYSCON->SYSPLLCTRL = BITS(0,5) | BITS(5,1);
// Power up system pll
CLRBIT(LPC_SYSCON->PDRUNCFG,7);
while (!(LPC_SYSCON->SYSPLLSTAT & BIT(0)) );
// Use system pll clock out for the main clock
LPC_SYSCON->MAINCLKSEL = 3;
// Update main clock selection
#ifdef MCU_IS_LPC1311
LPC_SYSCON->MAINCLKUEN = 1;
LPC_SYSCON->MAINCLKUEN = 0;
LPC_SYSCON->MAINCLKUEN = 1;
// Wait main clock
while ( !(LPC_SYSCON->MAINCLKUEN & BIT(0)) );
#endif
//====== USB Clock ====//
// USB avalaible only on LPC1343
// Power down usb clock
// SETBIT(LPC_SYSCON->PDRUNCFG,10);
// SETBIT(LPC_SYSCON->PDRUNCFG,8);
//====== Peripheral clock ====//
// System clock divider :
// divide the main clock for the core, memory and peripheral
LPC_SYSCON->SYSAHBCLKDIV = 1;
// Voir le datasheet page 26 pour les clocks des peripheriques
// Disable USB clock
// CLRBIT(LPC_SYSCON->SYSAHBCLKCTRL,14);
//====== Flash access clock ====//
// bon pour le moment on s'en fout si cpu = 72MHz
// CLRBITS(LPC_SYSCON->FLASHCFG, 3);
// LPC_SYSCON->FLASHCFG |= BIT(1);
// Interrupt vectors are in flash memory
//LPC_SYSCON->SYSMEMREMAP = 0x2;
}
#include <nano-X.h>
/*
* For defining bitmaps easily.
*/
#define X ((unsigned) 1)
#define _ ((unsigned) 0)
#define BITS(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p) \
(((((((((((((((a*2+b)*2+c)*2+d)*2+e)*2+f)*2+g)*2+h)*2+i)*2+j)*2+k) \
*2+l)*2+m)*2+n)*2+o)*2+p)
/* The utility button not pressed bitmap */
GR_BITMAP utilitybutton_notpressed[] = {
BITS(X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,_),
BITS(X,_,_,_,_,_,_,_,_,_,_,_,_,_,X,_),
BITS(X,_,_,_,_,_,_,_,_,_,_,_,_,_,X,_),
BITS(X,_,_,_,_,_,_,_,_,_,_,_,_,_,X,_),
BITS(X,_,_,_,_,_,_,_,_,_,_,_,_,_,X,_),
BITS(X,_,_,_,_,_,_,_,_,_,_,_,_,_,X,_),
BITS(X,_,_,X,X,X,X,X,X,X,X,X,_,_,X,_),
BITS(X,_,_,X,_,_,_,_,_,_,_,X,_,_,X,_),
BITS(X,_,_,X,X,X,X,X,X,X,X,X,_,_,X,_),
BITS(X,_,_,_,_,_,_,_,_,_,_,_,_,_,X,_),
BITS(X,_,_,_,_,_,_,_,_,_,_,_,_,_,X,_),
BITS(X,_,_,_,_,_,_,_,_,_,_,_,_,_,X,_),
BITS(X,_,_,_,_,_,_,_,_,_,_,_,_,_,X,_),
BITS(X,_,_,_,_,_,_,_,_,_,_,_,_,_,X,_),
BITS(X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,_),
BITS(_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_)
void Via::Write(uint16_t address, uint8_t value) {
auto UpdateIntegrators = [&] {
const bool muxEnabled = !TestBits(m_portB, PortB::MuxDisabled);
if (muxEnabled) {
switch (ReadBitsWithShift(m_portB, PortB::MuxSelMask, PortB::MuxSelShift)) {
case 0: // Y-axis integrator
m_screen.SetIntegratorY(static_cast<int8_t>(m_portA));
break;
case 1: // X,Y Axis integrator offset
m_screen.SetIntegratorXYOffset(static_cast<int8_t>(m_portA));
break;
case 2: // Z Axis (Vector Brightness) level
m_screen.SetBrightness(m_portA);
break;
case 3: // Connected to sound output line via divider network
m_directAudioSamples.Add(static_cast<int8_t>(m_portA) / 128.f); // [-1,1]
break;
default:
FAIL();
break;
}
}
// Always output to X-axis integrator
m_screen.SetIntegratorX(static_cast<int8_t>(m_portA));
};
auto UpdatePsg = [&] {
const bool muxEnabled = !TestBits(m_portB, PortB::MuxDisabled);
if (!muxEnabled) {
m_psg.SetBC1(TestBits(m_portB, PortB::SoundBC1));
m_psg.SetBDIR(TestBits(m_portB, PortB::SoundBDir));
// @TODO: not sure if we should always send port A value to PSG's DA bus, or just when
// MUX disabled
m_psg.WriteDA(m_portA);
}
};
const uint16_t index = MemoryMap::Via.MapAddress(address);
switch (index) {
case Register::PortB:
m_portB = value;
UpdateIntegrators();
UpdatePsg();
break;
case Register::PortA:
m_ca1InterruptFlag = false; // Cleared by read/write of Port A
// Port A is connected directly to the DAC, which in turn is connected to both a MUX with 4
// outputs, and to the X-axis integrator.
m_portA = value;
if (m_dataDirA == 0xFF) {
UpdateIntegrators();
}
break;
case Register::DataDirB:
m_dataDirB = value;
break;
case Register::DataDirA:
m_dataDirA = value;
ASSERT_MSG(m_dataDirA == 0 || m_dataDirA == 0xFF,
"Expecting DDR for A to be either all 0s or all 1s");
break;
case Register::Timer1Low:
m_timer1.WriteCounterLow(value);
break;
case Register::Timer1High:
m_timer1.WriteCounterHigh(value);
break;
case Register::Timer1LatchLow:
m_timer1.WriteLatchLow(value);
break;
case Register::Timer1LatchHigh:
m_timer1.WriteLatchHigh(value);
break;
case Register::Timer2Low:
m_timer2.WriteCounterLow(value);
break;
case Register::Timer2High:
m_timer2.WriteCounterHigh(value);
break;
case Register::Shift:
m_shiftRegister.SetValue(value);
break;
case Register::AuxCntl: {
// For now just read the shift register mode, which will assert if it's invalid/unexpected
auto shiftRegisterMode = AuxCntl::GetShiftRegisterMode(value);
(void)shiftRegisterMode;
ASSERT_MSG(AuxCntl::GetTimer1Mode(value) == TimerMode::OneShot,
"t1 assumed always on one-shot mode");
ASSERT_MSG(AuxCntl::GetTimer2Mode(value) == TimerMode::OneShot,
"t2 assumed always on one-shot mode");
m_timer1.SetTimerMode(AuxCntl::GetTimer1Mode(value));
m_timer2.SetTimerMode(AuxCntl::GetTimer2Mode(value));
m_timer1.SetPB7Flag(TestBits(value, AuxCntl::PB7Flag));
} break;
case Register::PeriphCntl: {
ASSERT_MSG(ReadBitsWithShift(value, PeriphCntl::CA2Mask, PeriphCntl::CA2Shift) == 0b110 ||
ReadBitsWithShift(value, PeriphCntl::CA2Mask, PeriphCntl::CA2Shift) == 0b111,
"Unexpected value for CA2 bits");
ASSERT_MSG(ReadBitsWithShift(value, PeriphCntl::CB2Mask, PeriphCntl::CB2Shift) == 0b110 ||
ReadBitsWithShift(value, PeriphCntl::CB2Mask, PeriphCntl::CB2Shift) == 0b111,
"Top 2 bits should always be 1 (right?)");
m_periphCntl = value;
if (!m_shiftRegister.Enabled()) {
m_screen.SetBlankEnabled(PeriphCntl::IsBlankEnabled(m_periphCntl));
}
} break;
case Register::InterruptFlag:
// Clear interrupt flags for any bits that are enabled
//@TODO: validate if this is the correct behaviour
// Assert if trying to clear an interrupt we don't handle yet
#define ASSERT_UNHANDLED(flag) \
ASSERT_MSG(!TestBits(value, flag), "Write to clear interrupt not supported yet: %s", #flag)
ASSERT_UNHANDLED(InterruptFlag::CA2);
ASSERT_UNHANDLED(InterruptFlag::CB1);
ASSERT_UNHANDLED(InterruptFlag::CB2);
#undef ASSERT_UNHANDLED
if (TestBits(value, InterruptFlag::CA1))
m_ca1InterruptFlag = false;
if (TestBits(value, InterruptFlag::Shift))
m_shiftRegister.SetInterruptFlag(false);
if (TestBits(value, InterruptFlag::Timer2))
m_timer2.SetInterruptFlag(false);
if (TestBits(value, InterruptFlag::Timer1))
m_timer1.SetInterruptFlag(false);
break;
case Register::InterruptEnable: {
// When bit 7 = 0 : Each 1 in a bit position is cleared (disabled).
// When bit 7 = 1 : Each 1 in a bit position enables that bit.
// (Zeros in bit positions are left unchanged)
SetBits(m_interruptEnable, (value & 0x7F), TestBits(value, BITS(7)));
// Assert if trying to enable interrupt we don't handle yet
#define ASSERT_UNHANDLED(flag) \
ASSERT_MSG(!TestBits(m_interruptEnable, flag), \
"Write to enable interrupt not supported yet: %s", #flag)
ASSERT_UNHANDLED(InterruptFlag::CA2);
ASSERT_UNHANDLED(InterruptFlag::CB1);
ASSERT_UNHANDLED(InterruptFlag::CB2);
#undef ASSERT_UNHANDLED
} break;
case Register::PortANoHandshake:
FAIL_MSG("A without handshake not implemented yet");
break;
default:
FAIL();
break;
}
}
/* SCO's version of MSC 5.x barfs on the line above without a trailing space */
#ifdef TEXTCOLOR
# define OBJECT(obj,bits,prp,sym,prob,dly,wt,cost,sdam,ldam,oc1,oc2,nut,color) \
{0, 0, NULL, bits, prp, sym, dly, color,\
prob, wt, cost, sdam, ldam, oc1, oc2, nut}
#else
# define OBJECT(obj,bits,prp,sym,prob,dly,wt,cost,sdam,ldam,oc1,oc2,nut,color) \
{0, 0, NULL, bits, prp, sym, dly,\
prob, wt, cost, sdam, ldam, oc1, oc2, nut}
#endif
NEARDATA struct objclass objects[] = {
#endif
/* dummy object[0] -- description [2nd arg] *must* be NULL */
OBJECT(OBJ("strange object",NULL), BITS(1,0,0,0,0,0,0,0,0,0,0), 0,
ILLOBJ_CLASS, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
/* weapons ... */
#define WEAPON(name,app,kn,mg,bi,prob,wt,cost,sdam,ldam,hitbon,metal,color) OBJECT( \
OBJ(name,app), BITS(kn,mg,1,0,0,1,0,0,bi,0,metal), 0, \
WEAPON_CLASS, prob, 0, \
wt, cost, sdam, ldam, hitbon, 0, wt, color )
#define PROJECTILE(name,app,kn,prob,wt,cost,sdam,ldam,hitbon,metal,prop,color) OBJECT( \
OBJ(name,app), BITS(kn,1,1,0,0,1,0,0,0,0,metal), 0, \
WEAPON_CLASS, prob, 0, \
wt, cost, sdam, ldam, hitbon, prop, wt, color )
#define BOW(name,app,kn,prob,wt,cost,sdam,ldam,hitbon,metal,prop,color) OBJECT( \
OBJ(name,app), BITS(kn,0,1,0,0,1,0,0,0,0,metal), 0, \
WEAPON_CLASS, prob, 0, \
wt, cost, sdam, ldam, hitbon, -(prop), wt, color )
static inline void
_planar_mode_color_read(const uint8_t *etc, uint32_t *bgra)
{
// RO: Bits 57-62
const int RO = _6to8(BITS(etc[0], 1, 6));
// GO: Bits 49-54,56
const int GO = _7to8((BIT(etc[0], 0) << 6) | (BITS(etc[1], 1, 6)));
// BO: Bits 39,40-41,43-44,48
const int BO = _6to8((BIT(etc[1], 0) << 5) | (BITS(etc[2], 3, 4) << 3) | (BITS(etc[2], 0, 1) << 1) | BIT(etc[3], 7));
// RH: Bits 32,34-38
const int RH = _6to8((BITS(etc[3], 2, 6) << 1) | BIT(etc[3], 0));
// GH: Bits 25-31
const int GH = _7to8(BITS(etc[4], 1, 7));
// BH: Bits 19-23,24
const int BH = _6to8((BIT(etc[4], 0) << 5) | (BITS(etc[5], 3, 7)));
// RV: Bits 13-15,16-18
const int RV = _6to8((BITS(etc[5], 0, 2) << 3) | (BITS(etc[6], 5, 7)));
// GV: Bits 6-7,8-12
const int GV = _7to8((BITS(etc[6], 0, 4) << 2) | (BITS(etc[7], 6, 7)));
// BV: Bits 0-5
const int BV = _6to8(BITS(etc[7], 0, 5));
for (int y = 0; y < 4; y++)
for (int x = 0; x < 4; x++)
{
// Formulas straight from the spec
const int R = CLAMP(((x * (RH - RO)) + y * (RV - RO) + 4 * RO + 2) >> 2);
const int G = CLAMP(((x * (GH - GO)) + y * (GV - GO) + 4 * GO + 2) >> 2);
const int B = CLAMP(((x * (BH - BO)) + y * (BV - BO) + 4 * BO + 2) >> 2);
*bgra++ = BGRA(R, G, B, 255);
}
}
int do_select(int n, fd_set_bits *fds, long *timeout)
{
poll_table table, *wait;
int retval, i, off;
long __timeout = *timeout;
read_lock(¤t->files->file_lock);
retval = max_select_fd(n, fds);
read_unlock(¤t->files->file_lock);
if (retval < 0)
return retval;
n = retval;
poll_initwait(&table);
wait = &table;
if (!__timeout)
wait = NULL;
retval = 0;
for (;;) {
set_current_state(TASK_INTERRUPTIBLE);
for (i = 0 ; i < n; i++) {
unsigned long bit = BIT(i);
unsigned long mask;
struct file *file;
off = i / __NFDBITS;
if (!(bit & BITS(fds, off)))
continue;
file = fget(i);
mask = POLLNVAL;
if (file) {
mask = DEFAULT_POLLMASK;
if (file->f_op && file->f_op->poll)
mask = file->f_op->poll(file, wait);
fput(file);
}
if ((mask & POLLIN_SET) && ISSET(bit, __IN(fds,off))) {
SET(bit, __RES_IN(fds,off));
retval++;
wait = NULL;
}
if ((mask & POLLOUT_SET) && ISSET(bit, __OUT(fds,off))) {
SET(bit, __RES_OUT(fds,off));
retval++;
wait = NULL;
}
if ((mask & POLLEX_SET) && ISSET(bit, __EX(fds,off))) {
SET(bit, __RES_EX(fds,off));
retval++;
wait = NULL;
}
}
wait = NULL;
if (retval || !__timeout || signal_pending(current))
break;
if(table.error) {
retval = table.error;
break;
}
__timeout = schedule_timeout(__timeout);
}
current->state = TASK_RUNNING;
poll_freewait(&table);
/*
* Up-to-date the caller timeout.
*/
*timeout = __timeout;
return retval;
}
/*----------------------------------------------------------------------------*/
VOID rlmBssInitForAP(P_ADAPTER_T prAdapter, P_BSS_INFO_T prBssInfo)
{
ENUM_BAND_T eBand;
UINT_8 ucChannel, i;
ENUM_CHNL_EXT_T eSCO;
ASSERT(prAdapter);
ASSERT(prBssInfo);
if (prBssInfo->eCurrentOPMode != OP_MODE_ACCESS_POINT) {
return;
}
/* Operation band, channel shall be ready before invoking this function.
* Bandwidth may be ready if other network is connected
*/
prBssInfo->fg40mBwAllowed = FALSE;
prBssInfo->fgAssoc40mBwAllowed = FALSE;
prBssInfo->eBssSCO = CHNL_EXT_SCN;
/* Check if AP can set its bw to 40MHz
* But if any of BSS is setup in 40MHz, the second BSS would prefer to use 20MHz
* in order to remain in SCC case
*/
if (cnmBss40mBwPermitted(prAdapter, prBssInfo->ucBssIndex)) {
/* In this case, the first BSS's SCO is 40MHz and known, so AP can
* apply 40MHz bandwidth, but the first BSS's SCO may be changed
* later if its Beacon lost timeout occurs
*/
if (cnmPreferredChannel(prAdapter, &eBand, &ucChannel, &eSCO) &&
eSCO != CHNL_EXT_SCN && ucChannel == prBssInfo->ucPrimaryChannel &&
eBand == prBssInfo->eBand) {
prBssInfo->eBssSCO = eSCO;
} else {
prBssInfo->eBssSCO = rlmDecideScoForAP(prAdapter, prBssInfo);
}
if (prBssInfo->eBssSCO != CHNL_EXT_SCN) {
prBssInfo->fg40mBwAllowed = TRUE;
prBssInfo->fgAssoc40mBwAllowed = TRUE;
prBssInfo->ucHtOpInfo1 = (UINT_8)
(((UINT_32) prBssInfo->eBssSCO) | HT_OP_INFO1_STA_CHNL_WIDTH);
rlmUpdateBwByChListForAP(prAdapter, prBssInfo);
}
}
/* Filled the VHT BW/S1/S2 and MCS rate set */
if(prBssInfo->ucPhyTypeSet & PHY_TYPE_BIT_VHT) {
for(i = 0 ; i < 8 ; i++ ){
prBssInfo->u2VhtBasicMcsSet |= BITS(2*i,(2*i+1));
}
prBssInfo->u2VhtBasicMcsSet &= (VHT_CAP_INFO_MCS_MAP_MCS9 << VHT_CAP_INFO_MCS_1SS_OFFSET);
if(cnmGetBssMaxBw(prAdapter, prBssInfo->ucBssIndex) < MAX_BW_80MHZ || prBssInfo->eBand == BAND_2G4) {
prBssInfo->ucVhtChannelWidth = VHT_OP_CHANNEL_WIDTH_20_40;
prBssInfo->ucVhtChannelFrequencyS1 = 0;
prBssInfo->ucVhtChannelFrequencyS2 = 0;
}
else if(cnmGetBssMaxBw(prAdapter, prBssInfo->ucBssIndex) == MAX_BW_80MHZ) {
prBssInfo->ucVhtChannelWidth = VHT_OP_CHANNEL_WIDTH_80;
prBssInfo->ucVhtChannelFrequencyS1 = nicGetVhtS1(prBssInfo->ucPrimaryChannel);
prBssInfo->ucVhtChannelFrequencyS2 = 0;
}
else {
//4 TODO: BW160 / BW80+80 support
}
}
else {
prBssInfo->ucVhtChannelWidth = VHT_OP_CHANNEL_WIDTH_20_40;
prBssInfo->ucVhtChannelFrequencyS1 = 0;
prBssInfo->ucVhtChannelFrequencyS2 = 0;
}
DBGLOG(RLM, INFO, ("WLAN AP SCO=%d BW=%d S1=%d S2=%d CH=%d Band=%d\n",
prBssInfo->eBssSCO,
prBssInfo->ucVhtChannelWidth,
prBssInfo->ucVhtChannelFrequencyS1,
prBssInfo->ucVhtChannelFrequencyS2,
prBssInfo->ucVhtChannelWidth,
prBssInfo->eBand
));
}
