void
evgSeqRam::dealloc() {
m_softSeq = 0;
//clear interrupt flags
BITSET32(m_pReg, IrqFlag, EVG_IRQ_STOP_RAM(m_id));
BITSET32(m_pReg, IrqFlag, EVG_IRQ_START_RAM(m_id));
}
void
evgMrm::enable(bool ena) {
if(ena)
BITSET32(m_pReg, Control, EVG_MASTER_ENA);
else
BITCLR32(m_pReg, Control, EVG_MASTER_ENA);
BITSET32(m_pReg, Control, EVG_DIS_EVT_REC);
BITSET32(m_pReg, Control, EVG_REV_PWD_DOWN);
BITSET32(m_pReg, Control, EVG_MXC_RESET);
}
void
evgEvtClk::setSource (bool clkSrc) {
if(clkSrc)
BITSET32 (m_pReg, ClockControl, ClockControl_EXTRF);
else
BITCLR32 (m_pReg, ClockControl, ClockControl_EXTRF);
}
void
evgMxc::setPolarity(bool polarity) {
if(polarity)
BITSET32(m_pReg, MuxControl(m_id), MuxControl_Pol);
else
BITCLR32(m_pReg, MuxControl(m_id), MuxControl_Pol);
}
void
evgSeqRam::enable() {
if(isAllocated()) {
BITSET32(m_pReg, SeqControl(m_id), EVG_SEQ_RAM_ARM);
} else
throw std::runtime_error("Trying to enable Unallocated seqRam");
}
void
evgSeqRam::setRunMode(SeqRunMode mode) {
switch (mode) {
case(Normal):
BITCLR32(m_pReg, SeqControl(m_id), EVG_SEQ_RAM_SINGLE);
BITCLR32(m_pReg, SeqControl(m_id), EVG_SEQ_RAM_RECYCLE);
break;
case(Auto):
BITCLR32(m_pReg, SeqControl(m_id), EVG_SEQ_RAM_SINGLE);
BITSET32(m_pReg, SeqControl(m_id), EVG_SEQ_RAM_RECYCLE);
break;
case(Single):
BITSET32(m_pReg, SeqControl(m_id), EVG_SEQ_RAM_SINGLE);
break;
default:
throw std::runtime_error("Unknown SeqRam RunMode");
}
}
void
evgMxc::setTrigEvtMap(epicsUInt16 trigEvt, bool ena) {
if(trigEvt > 7)
throw std::runtime_error("EVG Mxc Trig Event ID too large. Max: 7");
epicsUInt32 mask = 1 << (trigEvt+MuxControl_TrigMap_SHIFT);
if(ena)
BITSET32(m_pReg, MuxControl(m_id), mask);
else
BITCLR32(m_pReg, MuxControl(m_id), mask);
}
s8 pvt_init(u8 div)
{
//u32 load_val;
//per_clk = 800000000/4;
PVT_TMR_CONTROL = div<<8; //Disable timer
//Clear interrupt flag
PVT_TMR_INT_STATUS = BIT0;
PVT_TMR_COUNTER = 0xFFFFFFFF; //counter init val
PVT_TMR_LOAD = 0xFFFFFFFF; //reload val
BITSET32(PVT_TMR_CONTROL, BIT1);
return true;
}
void
evgMrm::process_eos1_cb(CALLBACK *pCallback) {
void* pVoid;
evgSeqRam* seqRam;
callbackGetUser(pVoid, pCallback);
seqRam = (evgSeqRam*)pVoid;
if(!seqRam)
return;
{
interruptLock ig;
if(seqRam->m_owner->irqStop1_queued==2)
BITSET32(seqRam->m_owner->getRegAddr(), IrqEnable, EVG_IRQ_STOP_RAM(1));
seqRam->m_owner->irqStop1_queued=0;
}
seqRam->process_eos();
}
void gic_Int_cfg(u16 irq, u16 prio, u16 pol)
{
u32 reg;
reg = (u32)&GIC_INT_REG_ICDIPR; /* Configure interrupt priority. */
reg += (irq / 4u *4);
*(u32 *) reg &=~(0xFF<<((irq%4)*8));
*(u32 *) reg |= prio<<((irq%4)*8);
reg = (u32)&GIC_INT_REG_ICDICFR;
reg += (irq / 16u);
if (pol == GIC_INT_POL_LEVEL_HIGH || pol == GIC_INT_POL_LEVEL_LOW) {
BITCLR32((*(u32 *)reg), (1u << (((irq % 16u) * 2u) + 1u)));
} else {
BITSET32((*(u32 *)reg), (1u << (((irq % 16u) * 2u) + 1u)));
}
}
void
evgMrm::process_inp_cb(CALLBACK *pCallback) {
void* pVoid;
callbackGetUser(pVoid, pCallback);
evgMrm* evg = (evgMrm*)pVoid;
{
interruptLock ig;
if(evg->irqExtInp_queued==2)
BITSET32(evg->getRegAddr(), IrqEnable, EVG_IRQ_EXT_INP);
evg->irqExtInp_queued=0;
}
epicsUInt32 data = evg->sendTimestamp();
if(!data)
return;
for(int i = 0; i < 32; data <<= 1, i++) {
if( data & 0x80000000 )
evg->getSoftEvt()->setEvtCode(MRF_EVENT_TS_SHIFT_1);
else
evg->getSoftEvt()->setEvtCode(MRF_EVENT_TS_SHIFT_0);
}
}
void
evgMrm::resetMxc(bool reset) {
if(reset)
BITSET32(m_pReg, Control, EVG_MXC_RESET);
}
void
evgSeqRam::softTrig() {
BITSET32(m_pReg, SeqControl(m_id), EVG_SEQ_RAM_SW_TRIG);
}
void
evgSeqRam::reset() {
BITSET32(m_pReg, SeqControl(m_id), EVG_SEQ_RAM_RESET);
}
void
evgSeqRam::disable() {
BITSET32(m_pReg, SeqControl(m_id), EVG_SEQ_RAM_DISABLE);
}
void pvt_start (void)
{
BITSET32(PVT_TMR_CONTROL, BIT0);
}
void gic_Int_init (void)
{
u32 reg;
u32 core_msk;
u8 i;
u16 irq;
gic_irq_vect_t *pvect;
u32 flags;
struct bm_gic_chip_data *gic_data = (struct bm_gic_chip_data *)(AMPPHY_START + AMP_GIC_DATA_OFFSET);
void *base = (void *)GIC_INT_DIST_BASE;
u32 gic_irqs;
BITCLR32(GIC_INT_REG_ICDDCR, BIT0); /* Disable the Global Interrupt Controller. */
//uartprintf("********####gic_irqs\r\n");
gic_irqs = readl(base + 4) & 0x1f;
gic_irqs = (gic_irqs + 1) * 32;
//uartprintf("++gic_irqs = %d\r\n", gic_irqs);
if (gic_irqs > 1020)
gic_irqs = 1020;
gic_data->gic_irqs = gic_irqs;
for (i = 0u; i < (gic_irqs / 32u); i++) { /* Disable all the GIC irq sources. */
reg = (u32)&GIC_INT_REG_ICDICER;
reg += (4u + (i * 4u));
(*(u32 *)reg) = 0xFFFFFFFF;
reg = (u32)&GIC_INT_REG_ICDICPR;
reg += i * 4u;
//(*(u32 *)reg) = 0xa0a0a0a0;
(*(u32 *)reg) = 0xFFFFFFFF;
}
for (i = 32; i < (gic_irqs / 16); i += 16)
writel(0, (void *)GIC_INT_DIST_BASE + 0xc00 + i * 4 / 16);
core_msk = (BIT0 | BIT8 | BIT16 | BIT24); /* bit0~7 for cpu0~cpu8 */
//core_msk = (BIT1 | BIT9 | BIT17 | BIT25);
for (i = 0u; i < ((gic_irqs - 32u) / 4u); i++) {
reg = (u32)&GIC_INT_REG_ICDIPTR; //target
reg += (((32u / 4u) + i) * 4u);
(*(u32 *)reg) = core_msk;
reg = (u32)&GIC_INT_REG_ICDIPR; //priority
reg += (((32u / 4u) + i) * 4u);
(*(u32 *)reg) = 0xa0a0a0a0;
}
gic_Int_cfg_target(GIC_DMA0);
gic_Int_cfg_target(GIC_PFGA0);
gic_Int_cfg(GIC_PFGA0, 0x80, GIC_INT_POL_EDGE_RISING);
/* Initialize the vector table. */
for (irq = 0u; irq < MAX_IRQ_NR; irq++) {
pvect = &gic_vect_tbl[irq];
flags = cpu_local_irq_save();
gic_Int_vect_clr(pvect); /* Initialize main vector table entry. */
cpu_local_irq_restore(flags);
}
BITCLR32(GIC_INT_REG_ICCPMR, 0xffff);
BITSET32(GIC_INT_REG_ICCPMR, BIT4|BIT5|BIT6|BIT7); /* Set priority mask. */
BITSET32(GIC_INT_REG_ICCICR, BIT0); /* Enable CPU interface. */
BITSET32(GIC_INT_REG_ICDDCR, BIT0); /* Enable the Global Interrupt Controller. */
}
