u64_t tele_mntn_func_sw_bit_set (u32_t bit)
{
if(TELE_MNTN_NULL != tele_mntn_func_sw)
{
*tele_mntn_func_sw = ((*tele_mntn_func_sw) & (~(BIT_64(bit))))|BIT_64(bit);
return (*tele_mntn_func_sw);
}
return 0;
}
static inline int __flip_bit(u32 msr, u8 bit, bool set)
{
struct msr m, m1;
int err = -EINVAL;
if (bit > 63)
return err;
err = msr_read(msr, &m);
if (err)
return err;
m1 = m;
if (set)
m1.q |= BIT_64(bit);
else
m1.q &= ~BIT_64(bit);
if (m1.q == m.q)
return 0;
err = msr_write(msr, &m1);
if (err)
return err;
return 1;
}
static void decode_mc1_mce(struct mce *m)
{
u16 ec = EC(m->status);
u8 xec = XEC(m->status, xec_mask);
pr_emerg(HW_ERR "MC1 Error: ");
if (TLB_ERROR(ec))
pr_cont("%s TLB %s.\n", LL_MSG(ec),
(xec ? "multimatch" : "parity error"));
else if (BUS_ERROR(ec)) {
bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58)));
pr_cont("during %s.\n", (k8 ? "system linefill" : "NB data read"));
} else if (INT_ERROR(ec)) {
if (xec <= 0x3f)
pr_cont("Hardware Assert.\n");
else
goto wrong_mc1_mce;
} else if (fam_ops->mc1_mce(ec, xec))
;
else
goto wrong_mc1_mce;
return;
wrong_mc1_mce:
pr_emerg(HW_ERR "Corrupted MC1 MCE info?\n");
}
s32_t tele_mntn_is_func_on (TELE_MNTN_TYPE_ID type_id)
{
/*lint -e571*/
if((TELE_MNTN_NULL != tele_mntn_func_sw)&&((*tele_mntn_func_sw) & BIT_64(type_id)))
{
return TELE_MNTN_OK;
}
return TELE_MNTN_ERRO;
/*lint +e571*/
}
static void amd_decode_ic_mce(struct mce *m)
{
u16 ec = EC(m->status);
u8 xec = XEC(m->status, xec_mask);
pr_emerg(HW_ERR "Instruction Cache Error: ");
if (TLB_ERROR(ec))
pr_cont("%s TLB %s.\n", LL_MSG(ec),
(xec ? "multimatch" : "parity error"));
else if (BUS_ERROR(ec)) {
bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58)));
pr_cont("during %s.\n", (k8 ? "system linefill" : "NB data read"));
} else if (fam_ops->ic_mce(ec, xec))
;
else
pr_emerg(HW_ERR "Corrupted IC MCE info?\n");
}
