void reboot_device(unsigned reboot_reason)
{
uint32_t soc_ver = 0;
uint8_t reset_type = 0;
soc_ver = board_soc_version();
/* Write the reboot reason */
if (platform_is_8974() && BOARD_SOC_VERSION1(soc_ver))
writel(reboot_reason, RESTART_REASON_ADDR);
else
writel(reboot_reason, RESTART_REASON_ADDR_V2);
if(reboot_reason == FASTBOOT_MODE)
reset_type = PON_PSHOLD_WARM_RESET;
else
reset_type = PON_PSHOLD_HARD_RESET;
/* Configure PMIC for warm reset */
if (platform_is_8974() && (pmic_ver == PM8X41_VERSION_V2))
pm8x41_v2_reset_configure(reset_type);
else
pm8x41_reset_configure(reset_type);
/* Drop PS_HOLD for MSM */
writel(0x00, MPM2_MPM_PS_HOLD);
mdelay(5000);
dprintf(CRITICAL, "Rebooting failed\n");
}
/*
* Function to set the capabilities for the host
*/
void target_mmc_caps(struct mmc_host *host)
{
uint32_t soc_ver = 0;
soc_ver = board_soc_version();
/*
* 8974 v1 fluid devices, have a hardware bug
* which limits the bus width to 4 bit.
*/
switch(board_hardware_id())
{
case HW_PLATFORM_FLUID:
if (platform_is_8974() && BOARD_SOC_VERSION1(soc_ver))
host->caps.bus_width = MMC_BOOT_BUS_WIDTH_4_BIT;
else
host->caps.bus_width = MMC_BOOT_BUS_WIDTH_8_BIT;
break;
default:
host->caps.bus_width = MMC_BOOT_BUS_WIDTH_8_BIT;
};
host->caps.ddr_mode = 1;
host->caps.hs200_mode = 1;
host->caps.hs_clk_rate = MMC_CLK_96MHZ;
}
unsigned check_reboot_mode(void)
{
uint32_t restart_reason = 0;
uint32_t soc_ver = 0;
uint32_t restart_reason_addr;
soc_ver = board_soc_version();
if (platform_is_8974() && BOARD_SOC_VERSION1(soc_ver))
restart_reason_addr = RESTART_REASON_ADDR;
else
restart_reason_addr = RESTART_REASON_ADDR_V2;
/* Read reboot reason and scrub it */
restart_reason = readl(restart_reason_addr);
writel(0x00, restart_reason_addr);
return restart_reason;
}
void reboot_device(unsigned reboot_reason)
{
uint32_t soc_ver = 0;
uint8_t reset_type = 0;
soc_ver = board_soc_version();
/* Write the reboot reason */
if (target_is_8974() && BOARD_SOC_VERSION1(soc_ver))
writel(reboot_reason, RESTART_REASON_ADDR);
else
writel(reboot_reason, RESTART_REASON_ADDR_V2);
if(reboot_reason == FASTBOOT_MODE)
reset_type = PON_PSHOLD_WARM_RESET;
else
reset_type = PON_PSHOLD_HARD_RESET;
/* Configure PMIC for warm reset */
if (target_is_8974() && (pmic_ver == PM8X41_VERSION_V2))
pm8x41_v2_reset_configure(reset_type);
else
pm8x41_reset_configure(reset_type);
/* Disable Watchdog Debug.
* Required becuase of a H/W bug which causes the system to
* reset partially even for non watchdog resets.
*/
writel(readl(GCC_WDOG_DEBUG) & ~(1 << WDOG_DEBUG_DISABLE_BIT), GCC_WDOG_DEBUG);
dsb();
/* Wait until the write takes effect. */
while(readl(GCC_WDOG_DEBUG) & (1 << WDOG_DEBUG_DISABLE_BIT));
/* Drop PS_HOLD for MSM */
writel(0x00, MPM2_MPM_PS_HOLD);
mdelay(5000);
dprintf(CRITICAL, "Rebooting failed\n");
}
static void target_mmc_sdhci_init()
{
struct mmc_config_data config = {0};
uint32_t soc_ver = 0;
soc_ver = board_soc_version();
/*
* 8974 v1 fluid devices, have a hardware bug
* which limits the bus width to 4 bit.
*/
switch(board_hardware_id())
{
case HW_PLATFORM_FLUID:
if (platform_is_8974() && BOARD_SOC_VERSION1(soc_ver))
config.bus_width = DATA_BUS_WIDTH_4BIT;
else
config.bus_width = DATA_BUS_WIDTH_8BIT;
break;
default:
config.bus_width = DATA_BUS_WIDTH_8BIT;
};
/* Trying Slot 1*/
config.slot = 1;
/*
* For 8974 AC platform the software clock
* plan recommends to use the following frequencies:
* 200 MHz --> 192 MHZ
* 400 MHZ --> 384 MHZ
* only for emmc slot
*/
if (platform_is_8974ac())
config.max_clk_rate = MMC_CLK_192MHZ;
else
config.max_clk_rate = MMC_CLK_200MHZ;
config.sdhc_base = mmc_sdhci_base[config.slot - 1];
config.pwrctl_base = mmc_sdc_base[config.slot - 1];
config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
config.hs400_support = 1;
if (!(dev = mmc_init(&config))) {
/* Trying Slot 2 next */
config.slot = 2;
config.max_clk_rate = MMC_CLK_200MHZ;
config.sdhc_base = mmc_sdhci_base[config.slot - 1];
config.pwrctl_base = mmc_sdc_base[config.slot - 1];
config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
if (!(dev = mmc_init(&config))) {
dprintf(CRITICAL, "mmc init failed!");
ASSERT(0);
}
}
/*
* MMC initialization is complete, read the partition table info
*/
if (partition_read_table()) {
dprintf(CRITICAL, "Error reading the partition table info\n");
ASSERT(0);
}
}
