/****************************************************************************
*
* Function Name: cVoid chal_caph_dma_clear_register(CHAL_HANDLE handle,
* CAPH_DMA_CHANNEL_e channel)
*
* Description: Clear CR1 and CR2 registers before starting configuration
*
****************************************************************************/
cVoid chal_caph_dma_clear_register(CHAL_HANDLE handle,
CAPH_DMA_CHANNEL_e channel)
{
cUInt32 base = ((chal_caph_dma_cb_t *) handle)->base;
cUInt8 index;
cUInt32 cr = 0;
/* Find the channel we are looking for */
for (index = 0; index < CHAL_CAPH_DMA_MAX_CHANNELS; index++) {
if ((1UL << index) & channel) {
/* Apply the settings in the hardware */
BRCM_WRITE_REG_IDX(base, CPH_AADMAC_CH1_AADMAC_CR_2,
(index * CHAL_CAPH_DMA_CH_REG_SIZE),
cr);
BRCM_WRITE_REG_IDX(base, CPH_AADMAC_CH1_AADMAC_CR_1,
(index * CHAL_CAPH_DMA_CH_REG_SIZE),
cr);
break;
}
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_switch_remove_dst(CHAL_HANDLE handle,
* CAPH_SWITCH_CHNL_e channel,
* cUInt16 fifo_address)
*
* Description: CAPH ASW remove dst
*
****************************************************************************/
void chal_caph_switch_remove_dst(CHAL_HANDLE handle,
CAPH_SWITCH_CHNL_e channel,
cUInt16 address)
{
cUInt32 base = ((chal_caph_switch_cb_t*)handle)->base;
cUInt8 ch_idx;
cUInt16 reg_idx;
cUInt8 dst;
cUInt32 reg_val;
register cUInt32 loopCount;
address &= CPH_SSASW_CH01_DST1_CH01_DST1_ADDR_MASK;
/* Find the channel we are looking for */
for(ch_idx = 0; ch_idx < CHAL_CAPH_SWITCH_MAX_CHANNELS; ch_idx++)
{
if((1UL << ch_idx)&channel)
{
/* found the channel we are looking for, Look for the destination */
for(dst=0; dst < CHAL_CAPH_SWITCH_MAX_DESTINATIONS; dst++)
{
reg_idx = (ch_idx*CHAL_CAPH_SWITCH_CH_REG_SIZE) + (dst*CHAL_CAPH_SWITCH_DST_REG_SIZE);
reg_val = BRCM_READ_REG_IDX( base, CPH_SSASW_CH01_DST1, reg_idx);
if((reg_val & CPH_SSASW_CH01_DST1_CH01_DST1_ADDR_MASK) == address)
{
/* Clear destination information */
reg_val &= ~CPH_SSASW_CH01_DST1_CH01_DST1_EN_MASK;
BRCM_WRITE_REG_IDX(base, CPH_SSASW_CH01_DST1, reg_idx, reg_val);
/* ASIC team:
When there are more than one destination, first disable
the destination without changing the destination address
in CHxx_DST register(only change the destination enable
to 0, dest_addr unchanged). Then read back this CHxx_DST
register five times. This is to insert some delay to
make sure the source had stopped sending transfer to the
old address.
*/
for (loopCount = 5; loopCount != 0; loopCount--)
reg_val = BRCM_READ_REG_IDX(base, CPH_SSASW_CH01_DST1, reg_idx);
reg_val &= ~CPH_SSASW_CH01_DST1_CH01_DST1_ADDR_MASK;
BRCM_WRITE_REG_IDX(base, CPH_SSASW_CH01_DST1, reg_idx,reg_val);
break;
}
}
break;
}
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_switch_select_trigger(CHAL_HANDLE handle,
* CAPH_SWITCH_CHNL_e channel,
* CAPH_SWITCH_TRIGGER_e trigger)
*
* Description: CAPH ASW data tx trigger selection
*
****************************************************************************/
void chal_caph_switch_select_trigger(CHAL_HANDLE handle,
CAPH_SWITCH_CHNL_e channel,
CAPH_SWITCH_TRIGGER_e trigger)
{
cUInt32 base = ((chal_caph_switch_cb_t*)handle)->base;
cUInt8 index;
cUInt32 reg_val;
register cUInt32 loopCount;
/* Find the channel we are looking for */
for(index = 0; index < CHAL_CAPH_SWITCH_MAX_CHANNELS; index++)
{
if((1UL << index)&channel)
{
/* found the channel we are looking for, disable the channel */
// reg_val = BRCM_READ_REG_IDX( base, CPH_SSASW_CH01_SRC, (index*CHAL_CAPH_SWITCH_CH_REG_SIZE));
for (loopCount = 5; loopCount != 0; loopCount--)
reg_val = BRCM_READ_REG_IDX( base, CPH_SSASW_CH01_SRC, (index*CHAL_CAPH_SWITCH_CH_REG_SIZE));
/* Configure the trigger selection */
reg_val &= ~CPH_SSASW_CH01_SRC_CH01_TRIGGER_SEL_MASK;
reg_val |= (trigger << CPH_SSASW_CH01_SRC_CH01_TRIGGER_SEL_SHIFT);
/* Apply the settings to hardware */
BRCM_WRITE_REG_IDX(base, CPH_SSASW_CH01_SRC, (index*CHAL_CAPH_SWITCH_CH_REG_SIZE), reg_val);
break;
}
}
return;
}
/****************************************************************************
*
* Function Name: cVoid chal_caph_dma_enable(CHAL_HANDLE handle,
* cUInt16 channel)
*
* Description: enable CAPH DMA channel
*
****************************************************************************/
cVoid chal_caph_dma_enable(CHAL_HANDLE handle, cUInt16 channel)
{
cUInt32 base = ((chal_caph_dma_cb_t *) handle)->base;
cUInt8 index;
cUInt32 reg_val;
/* Find the channel we are looking for */
for (index = 0; index < CHAL_CAPH_DMA_MAX_CHANNELS; index++) {
if ((1UL << index) & channel) {
/* found the channel, enable the channel */
reg_val =
BRCM_READ_REG_IDX(base, CPH_AADMAC_CH1_AADMAC_CR_2,
(index *
CHAL_CAPH_DMA_CH_REG_SIZE));
reg_val |=
CPH_AADMAC_CH1_AADMAC_CR_2_CH1_AADMAC_EN_MASK;
BRCM_WRITE_REG_IDX(base, CPH_AADMAC_CH1_AADMAC_CR_2,
(index * CHAL_CAPH_DMA_CH_REG_SIZE),
reg_val);
}
}
return;
}
/****************************************************************************
*
* Function Name: cVoid chal_caph_cfifo_set_direction(CHAL_HANDLE handle,
* CAPH_CFIFO_e fifo,
* CAPH_CFIFO_CHNL_DIRECTION_e direction)
*
* Description: config CAPH CFIFO channel transfer direction
*
****************************************************************************/
cVoid chal_caph_cfifo_set_direction(CHAL_HANDLE handle,
CAPH_CFIFO_e fifo,
CAPH_CFIFO_CHNL_DIRECTION_e direction)
{
cUInt32 base = ((chal_caph_cfifo_cb_t *) handle)->base;
cUInt8 index;
cUInt32 reg_val;
/* Find the FIFOs we are looking for */
for (index = 0; index < CHAL_CAPH_CFIFO_MAX_FIFOS; index++) {
if ((1UL << index) & fifo) {
reg_val =
BRCM_READ_REG_IDX(base, CPH_CFIFO_CPH_CR_1,
(index *
CHAL_CAPH_CFIFO_CR_REG_SIZE));
/* configure direction */
reg_val &= ~CPH_CFIFO_CPH_CR_1_CH1_IN_OUT_MASK;
reg_val |=
(direction << CPH_CFIFO_CPH_CR_1_CH1_IN_OUT_SHIFT);
/* Apply the settings to the register */
BRCM_WRITE_REG_IDX(base, CPH_CFIFO_CPH_CR_1,
(index *
CHAL_CAPH_CFIFO_CR_REG_SIZE),
reg_val);
break;
}
}
return;
}
/****************************************************************************
*
* Function Name: cVoid chal_caph_dma_clr_ddrfifo_status(CHAL_HANDLE handle,
* CAPH_DMA_CHANNEL_e channel,
* CAPH_DMA_CHNL_FIFO_STATUS_e status)
*
* Description: clear CAPH DMA ddr fifo status
*
****************************************************************************/
static cVoid chal_caph_dma_rheaB0_clr_ddrfifo_status(CHAL_HANDLE handle,
CAPH_DMA_CHANNEL_e channel,
CAPH_DMA_CHNL_FIFO_STATUS_e
status)
{
cUInt32 base = ((chal_caph_dma_cb_t *) handle)->base;
cUInt8 index;
cUInt32 sr;
/*if (cpu_is_rhea_B0()) {*/
/*-- Rhea B0 --*/
/* Find the channel */
for (index = 0; index < CHAL_CAPH_DMA_MAX_CHANNELS; index++) {
if ((1UL << index) & channel) {
/* found the channel, Get the channel status */
sr = BRCM_READ_REG_IDX(base, CPH_AADMAC_CH1_AADMAC_SR_1,
(index *
CHAL_CAPH_DMA_CH_REG_SIZE));
/* write 0 to clear the bits that had been set */
sr &=
~((status & CAPH_READY_HIGHLOW) <<
CPH_AADMAC_CH1_AADMAC_SR_1_CH1_HW_READY_LOW_SHIFT);
BRCM_WRITE_REG_IDX(base, CPH_AADMAC_CH1_AADMAC_SR_1,
(index * CHAL_CAPH_DMA_CH_REG_SIZE),
sr);
break;
}
}
#if 0 /*B0 code does the same thing*/
} else {
/****************************************************************************
*
* Function Name: cVoid chal_caph_cfifo_disable(CHAL_HANDLE handle,
* cUInt16 fifo)
*
* Description: disable CAPH CFIFOs
*
****************************************************************************/
cVoid chal_caph_cfifo_disable(CHAL_HANDLE handle, cUInt16 fifo)
{
cUInt32 base = ((chal_caph_cfifo_cb_t *) handle)->base;
cUInt8 index;
cUInt32 reg_val;
/* Find the FIFOs we are looking for */
for (index = 0; index < CHAL_CAPH_CFIFO_MAX_FIFOS; index++) {
if ((1UL << index) & fifo) {
/* found the FIFO, Disable the FIFO */
reg_val =
BRCM_READ_REG_IDX(base, CPH_CFIFO_CPH_CR_1,
(index *
CHAL_CAPH_CFIFO_CR_REG_SIZE));
reg_val &=
~CPH_CFIFO_CPH_CR_1_CH1_CENTRAL_FIFO_ENABLE_MASK;
BRCM_WRITE_REG_IDX(base, CPH_CFIFO_CPH_CR_1,
(index *
CHAL_CAPH_CFIFO_CR_REG_SIZE),
reg_val);
}
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_dma_set_direction(CHAL_HANDLE handle,
* CAPH_DMA_CHANNEL_e channel,
* CAPH_CFIFO_CHNL_DIRECTION_e direction)
*
* Description: config CAPH DMA channel transfer direction
*
****************************************************************************/
void chal_caph_dma_set_direction(CHAL_HANDLE handle,
CAPH_DMA_CHANNEL_e channel,
CAPH_CFIFO_CHNL_DIRECTION_e direction)
{
uint32_t base = ((chal_caph_dma_cb_t*)handle)->base;
uint8_t index;
uint32_t cr = 0;
/* Find the channel we are looking for */
for(index = 0; index < CHAL_CAPH_DMA_MAX_CHANNELS; index++)
{
if((1UL << index)&channel)
{
/* Get the current configuration */
cr = BRCM_READ_REG_IDX( base, CPH_AADMAC_CH1_AADMAC_CR_2, (index*CHAL_CAPH_DMA_CH_REG_SIZE));
/* configure the direction of transfer */
cr &= ~CPH_AADMAC_CH1_AADMAC_CR_2_CH1_AADMAC_IN_OUT_MASK;
cr |= (direction << CPH_AADMAC_CH1_AADMAC_CR_2_CH1_AADMAC_IN_OUT_SHIFT);
/* Apply the settings in the hardware */
BRCM_WRITE_REG_IDX( base, CPH_AADMAC_CH1_AADMAC_CR_2, (index*CHAL_CAPH_DMA_CH_REG_SIZE), cr);
break;
}
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_switch_select_src(CHAL_HANDLE handle,
* CAPH_SWITCH_CHNL_e channel,
* cUInt16 fifo_address)
*
* Description: CAPH ASW src selection
*
****************************************************************************/
void chal_caph_switch_select_src(CHAL_HANDLE handle,
CAPH_SWITCH_CHNL_e channel,
cUInt16 address)
{
cUInt32 base = ((chal_caph_switch_cb_t*)handle)->base;
cUInt8 index;
cUInt32 reg_val;
/* Find the channel we are looking for */
for(index = 0; index < CHAL_CAPH_SWITCH_MAX_CHANNELS; index++)
{
if((1UL << index)&channel)
{
/* found the channel we are looking for, enable the channel */
reg_val = BRCM_READ_REG_IDX( base, CPH_SSASW_CH01_SRC, (index*CHAL_CAPH_SWITCH_CH_REG_SIZE));
reg_val &= ~CPH_SSASW_CH01_SRC_CH01_SRC_ADDR_MASK;
reg_val |= (address&CPH_SSASW_CH01_SRC_CH01_SRC_ADDR_MASK);
BRCM_WRITE_REG_IDX(base, CPH_SSASW_CH01_SRC, (index*CHAL_CAPH_SWITCH_CH_REG_SIZE), reg_val);
break;
}
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_dma_set_ddrfifo_status(CHAL_HANDLE handle,
* CAPH_DMA_CHANNEL_e channel,
* CAPH_DMA_CHNL_FIFO_STATUS_e status)
*
* Description: set CAPH DMA ddr fifo status
*
****************************************************************************/
void chal_caph_dma_set_ddrfifo_status(CHAL_HANDLE handle,
CAPH_DMA_CHANNEL_e channel,
CAPH_DMA_CHNL_FIFO_STATUS_e status)
{
uint32_t base = ((chal_caph_dma_cb_t*)handle)->base;
uint8_t index;
uint32_t cr = 0;
/* Find the channel we are looking for */
for(index = 0; index < CHAL_CAPH_DMA_MAX_CHANNELS; index++)
{
if((1UL << index)&channel)
{
/* found the channel we are looking for, Set the DDR fifo status */
cr = BRCM_READ_REG_IDX( base, CPH_AADMAC_CH1_AADMAC_CR_2, (index*CHAL_CAPH_DMA_CH_REG_SIZE));
if(status == CAPH_READY_NONE)
{
cr &= (~CPH_AADMAC_CH1_AADMAC_CR_2_CH1_SW_READY_LOW_MASK);
cr &= (~CPH_AADMAC_CH1_AADMAC_CR_2_CH1_SW_READY_HIGH_MASK);
}
else
{
cr |= (status << CPH_AADMAC_CH1_AADMAC_CR_2_CH1_SW_READY_LOW_SHIFT);
}
BRCM_WRITE_REG_IDX( base, CPH_AADMAC_CH1_AADMAC_CR_2, (index*CHAL_CAPH_DMA_CH_REG_SIZE), cr);
break;
}
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_switch_disable(CHAL_HANDLE handle,
* cUInt16 channel)
*
* Description: CAPH ASW disable
*
****************************************************************************/
void chal_caph_switch_disable(CHAL_HANDLE handle,
cUInt16 channel)
{
cUInt32 base = ((chal_caph_switch_cb_t*)handle)->base;
cUInt8 index;
cUInt32 reg_val;
register cUInt32 loopCount;
/* Find the channel we are looking for */
for(index = 0; index < CHAL_CAPH_SWITCH_MAX_CHANNELS; index++)
{
if((1UL << index)&channel)
{
/* found the channel we are looking for, disable the channel */
// reg_val = BRCM_READ_REG_IDX( base, CPH_SSASW_CH01_SRC, (index*CHAL_CAPH_SWITCH_CH_REG_SIZE));
for (loopCount = 5; loopCount != 0; loopCount--)
reg_val = BRCM_READ_REG_IDX( base, CPH_SSASW_CH01_SRC, (index*CHAL_CAPH_SWITCH_CH_REG_SIZE));
reg_val &= ~CPH_SSASW_CH01_SRC_CH01_SRC_EN_MASK;
BRCM_WRITE_REG_IDX(base, CPH_SSASW_CH01_SRC, (index*CHAL_CAPH_SWITCH_CH_REG_SIZE), reg_val);
}
}
return;
}
void chal_audio_eancpath_set_AFIR_coef(CHAL_HANDLE handle, cUInt32 *AFIR_coef )
{
cUInt32 base = ((ChalAudioCtrlBlk_t*)handle)->audioh_base;
cUInt32 index;
cUInt32 eanc_ctrl;
for(index = 0; index < 10; index++)
{
BRCM_WRITE_REG_IDX(base, AUDIOH_EANC_CO_AFIR, index, AFIR_coef[index]);
}
//Create a Raising edge pulse for the Coefficients Set bit
eanc_ctrl = BRCM_READ_REG(base, AUDIOH_EANC_CTL);
//Make sure bit is low
eanc_ctrl &= (~AUDIOH_EANC_CTL_EANC_AFIR_CO_SET_MASK);
BRCM_WRITE_REG(base, AUDIOH_EANC_CTL, eanc_ctrl);
//Set to high to make a raising edge
eanc_ctrl |= (AUDIOH_EANC_CTL_EANC_AFIR_CO_SET_MASK);
BRCM_WRITE_REG(base, AUDIOH_EANC_CTL, eanc_ctrl);
BRCM_WRITE_REG(base, AUDIOH_EANC_CTL, eanc_ctrl);
BRCM_WRITE_REG(base, AUDIOH_EANC_CTL, eanc_ctrl);
BRCM_WRITE_REG(base, AUDIOH_EANC_CTL, eanc_ctrl);
BRCM_WRITE_REG(base, AUDIOH_EANC_CTL, eanc_ctrl);
BRCM_WRITE_REG(base, AUDIOH_EANC_CTL, eanc_ctrl);
//Make sure bit is low, creates a falling edge
eanc_ctrl &= (~AUDIOH_EANC_CTL_EANC_AFIR_CO_SET_MASK);
BRCM_WRITE_REG(base, AUDIOH_EANC_CTL, eanc_ctrl);
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_switch_set_datafmt(CHAL_HANDLE handle,
* CAPH_SWITCH_CHNL_e channel,
* CAPH_DATA_FORMAT_e dataFormat)
*
* Description: CAPH ASW set data format: mono/stereo/16b/24b
*
****************************************************************************/
void chal_caph_switch_set_datafmt(CHAL_HANDLE handle,
CAPH_SWITCH_CHNL_e channel,
CAPH_DATA_FORMAT_e dataFormat)
{
cUInt32 base = ((chal_caph_switch_cb_t*)handle)->base;
cUInt8 index;
cUInt32 reg_val;
/* Find the channel we are looking for */
for(index = 0; index < CHAL_CAPH_SWITCH_MAX_CHANNELS; index++)
{
if((1UL << index)&channel)
{
/* found the channel we are looking for, disable the channel */
reg_val = BRCM_READ_REG_IDX( base, CPH_SSASW_CH01_SRC, (index*CHAL_CAPH_SWITCH_CH_REG_SIZE));
/* Configure the trigger selection */
reg_val &= ~CPH_SSASW_CH01_SRC_CH01_TWO_WORDS_MASK;
if(dataFormat == CAPH_STEREO_24BIT)
{
reg_val |= CPH_SSASW_CH01_SRC_CH01_TWO_WORDS_MASK;
}
/* Apply the settings to hardware */
BRCM_WRITE_REG_IDX(base, CPH_SSASW_CH01_SRC, (index*CHAL_CAPH_SWITCH_CH_REG_SIZE), reg_val);
break;
}
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_switch_clear_all_dst(CHAL_HANDLE handle,
* CAPH_SWITCH_CHNL_e channel,
* cUInt16 fifo_address)
*
* Description: CAPH ASW remove dst
*
****************************************************************************/
void chal_caph_switch_clear_all_dst(CHAL_HANDLE handle,
CAPH_SWITCH_CHNL_e channel)
{
cUInt32 base = ((chal_caph_switch_cb_t*)handle)->base;
cUInt8 ch_idx;
cUInt16 reg_idx;
cUInt8 dst;
cUInt32 reg_val;
/* Find the channel we are looking for */
for(ch_idx = 0; ch_idx < CHAL_CAPH_SWITCH_MAX_CHANNELS; ch_idx++)
{
if((1UL << ch_idx)&channel)
{
/* found the channel we are looking for, Look for the destination */
for(dst=0; dst < CHAL_CAPH_SWITCH_MAX_DESTINATIONS; dst++)
{
reg_idx = (ch_idx*CHAL_CAPH_SWITCH_CH_REG_SIZE) + (dst*CHAL_CAPH_SWITCH_DST_REG_SIZE);
reg_val = BRCM_READ_REG_IDX( base, CPH_SSASW_CH01_DST1, reg_idx);
/* Clear destination information */
reg_val &= ~CPH_SSASW_CH01_DST1_CH01_DST1_EN_MASK;
reg_val &= ~CPH_SSASW_CH01_DST1_CH01_DST1_ADDR_MASK;
BRCM_WRITE_REG_IDX(base, CPH_SSASW_CH01_DST1, reg_idx,reg_val);
}
break;
}
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_dma_clr_ddrfifo_status(CHAL_HANDLE handle,
* CAPH_DMA_CHANNEL_e channel,
* CAPH_DMA_CHNL_FIFO_STATUS_e status)
*
* Description: set CAPH DMA ddr fifo status
*
****************************************************************************/
void chal_caph_dma_clr_ddrfifo_status(CHAL_HANDLE handle,
CAPH_DMA_CHANNEL_e channel,
CAPH_DMA_CHNL_FIFO_STATUS_e status)
{
uint32_t base = ((chal_caph_dma_cb_t*)handle)->base;
uint8_t index;
uint32_t sr = 0;
/* Find the channel we are looking for */
for(index = 0; index < CHAL_CAPH_DMA_MAX_CHANNELS; index++)
{
if((1UL << index)&channel)
{
/* found the channel we are looking for, Set the DDR fifo status */
sr = (~status) & CAPH_READY_HIGHLOW;
sr <<= CPH_AADMAC_CH1_AADMAC_SR_1_CH1_HW_READY_LOW_SHIFT;
BRCM_WRITE_REG_IDX( base, CPH_AADMAC_CH1_AADMAC_SR_1, (index*CHAL_CAPH_DMA_CH_REG_SIZE), sr);
break;
}
}
return;
}
/****************************************************************************
*
* Function Name: CAPH_DST_STATUS_e chal_caph_switch_add_dst(CHAL_HANDLE handle,
* CAPH_SWITCH_CHNL_e channel,
* cUInt16 fifo_address)
*
* Description: CAPH ASW add dst
*
****************************************************************************/
CAPH_DST_STATUS_e chal_caph_switch_add_dst(CHAL_HANDLE handle,
CAPH_SWITCH_CHNL_e channel,
cUInt16 address)
{
cUInt32 base = ((chal_caph_switch_cb_t*)handle)->base;
cUInt8 ch_idx;
cUInt16 reg_idx;
cUInt8 dst;
cUInt32 reg_val;
address &= CPH_SSASW_CH01_DST1_CH01_DST1_ADDR_MASK;
/* Check for if this destination address is already allocated else where on the same channel as well as on all other channels */
for(ch_idx = 0; ch_idx < CHAL_CAPH_SWITCH_MAX_CHANNELS; ch_idx++)
{
for(dst=0; dst < CHAL_CAPH_SWITCH_MAX_DESTINATIONS; dst++)
{
reg_idx = (ch_idx*CHAL_CAPH_SWITCH_CH_REG_SIZE) + (dst*CHAL_CAPH_SWITCH_DST_REG_SIZE);
reg_val = BRCM_READ_REG_IDX( base, CPH_SSASW_CH01_DST1, reg_idx);
if((reg_val & CPH_SSASW_CH01_DST1_CH01_DST1_EN_MASK) &&
((reg_val & CPH_SSASW_CH01_DST1_CH01_DST1_ADDR_MASK) == address))
{
return CAPH_DST_USED;
}
}
}
/* Find the channel we are looking for */
for(ch_idx = 0; ch_idx < CHAL_CAPH_SWITCH_MAX_CHANNELS; ch_idx++)
{
if((1UL << ch_idx)&channel)
{
/* found the channel we are looking for, enable the channel */
for(dst=0; dst < CHAL_CAPH_SWITCH_MAX_DESTINATIONS; dst++)
{
reg_idx = (ch_idx*CHAL_CAPH_SWITCH_CH_REG_SIZE) + (dst*CHAL_CAPH_SWITCH_DST_REG_SIZE);
reg_val = BRCM_READ_REG_IDX( base, CPH_SSASW_CH01_DST1, reg_idx);
if(!(reg_val & CPH_SSASW_CH01_DST1_CH01_DST1_EN_MASK))
{
reg_val |= CPH_SSASW_CH01_DST1_CH01_DST1_EN_MASK;
reg_val &= ~CPH_SSASW_CH01_DST1_CH01_DST1_ADDR_MASK;
reg_val |= address;
BRCM_WRITE_REG_IDX(base, CPH_SSASW_CH01_DST1, reg_idx,reg_val);
return CAPH_DST_OK;
}
}
return CAPH_DST_NONE;
}
}
return CAPH_DST_NONE;
}
/****************************************************************************
*
* Function Name: cVoid chal_caph_dma_disable(CHAL_HANDLE handle,
* cUInt16 channel)
*
* Description: disable CAPH DMA channel
*
****************************************************************************/
cVoid chal_caph_dma_disable(CHAL_HANDLE handle, cUInt16 channel)
{
cUInt32 base = ((chal_caph_dma_cb_t *) handle)->base;
cUInt8 index;
cUInt32 reg_val;
/* Find the channel we are looking for */
for (index = 0; index < CHAL_CAPH_DMA_MAX_CHANNELS; index++) {
if ((1UL << index) & channel) {
#ifdef CAPH_NEW_SEQUENCE
/* found the channel we are looking for,
set FIFO_RST accordng to new sequence */
reg_val = BRCM_READ_REG_IDX(base,
CPH_AADMAC_CH1_AADMAC_SR_1,
(index*CHAL_CAPH_DMA_CH_REG_SIZE));
reg_val |= CPH_AADMAC_CH1_AADMAC_SR_1_CH1_AADMAC_FIFO_RST_MASK;
BRCM_WRITE_REG_IDX(base, CPH_AADMAC_CH1_AADMAC_SR_1,
(index*CHAL_CAPH_DMA_CH_REG_SIZE), reg_val);
#endif
/* found the channel, disable the channel */
reg_val =
BRCM_READ_REG_IDX(base, CPH_AADMAC_CH1_AADMAC_CR_2,
(index *
CHAL_CAPH_DMA_CH_REG_SIZE));
reg_val &=
~CPH_AADMAC_CH1_AADMAC_CR_2_CH1_AADMAC_EN_MASK;
BRCM_WRITE_REG_IDX(base, CPH_AADMAC_CH1_AADMAC_CR_2,
(index * CHAL_CAPH_DMA_CH_REG_SIZE),
reg_val);
#ifdef CAPH_NEW_SEQUENCE
/* found the channel we are looking for,
clear FIFO_RST according to new sequence*/
reg_val = BRCM_READ_REG_IDX(base,
CPH_AADMAC_CH1_AADMAC_SR_1,
(index*CHAL_CAPH_DMA_CH_REG_SIZE));
reg_val &= ~CPH_AADMAC_CH1_AADMAC_SR_1_CH1_AADMAC_FIFO_RST_MASK;
BRCM_WRITE_REG_IDX(base, CPH_AADMAC_CH1_AADMAC_SR_1,
(index*CHAL_CAPH_DMA_CH_REG_SIZE), reg_val);
#endif
}
}
return;
}
/****************************************************************************
*
* Function Name: cVoid chal_caph_dma_set_buffer(CHAL_HANDLE handle,
* CAPH_DMA_CHANNEL_e channel,
* cUInt32 address,
* cUInt32 size)
*
* Description: config CAPH DMA channel buffer parameters (address and size)
*
****************************************************************************/
static cVoid chal_caph_dma_rheaB0_set_hibuffer(CHAL_HANDLE handle,
CAPH_DMA_CHANNEL_e channel,
cUInt32 address, cUInt32 size)
{
cUInt32 base = ((chal_caph_dma_cb_t *) handle)->base;
cUInt8 index;
/*cUInt32 cr = 0;*/
/* Find the channel we are looking for */
for (index = 0; index < CHAL_CAPH_DMA_MAX_CHANNELS; index++) {
if ((1UL << index) & channel) {
/* Set the DMA buffer Address */
address &=
CPH_AADMAC_CH1_AADMAC_CR_3_CH1_AADMAC_HIGH_BASE_MASK;
BRCM_WRITE_REG_IDX(base, CPH_AADMAC_CH1_AADMAC_CR_3,
index, address);
#if 0
/* enable the use of hi buffer */
cr = BRCM_READ_REG_IDX(base, CPH_AADMAC_CH1_AADMAC_CR_2,
(index *
CHAL_CAPH_DMA_CH_REG_SIZE));
/* Configure the use of buffer base address register */
cr &=
~CPH_AADMAC_CH1_AADMAC_CR_2_CH1_AADMAC_HIGH_BASE_EN_MASK;
cr |=
(1 <<
CPH_AADMAC_CH1_AADMAC_CR_2_CH1_AADMAC_HIGH_BASE_EN_SHIFT);
/* Apply the settings in the hardware */
BRCM_WRITE_REG_IDX(base, CPH_AADMAC_CH1_AADMAC_CR_2,
(index * CHAL_CAPH_DMA_CH_REG_SIZE),
cr);
#endif
break;
}
}
return;
}
void chal_audio_eancpath_set_UIIR_coef(CHAL_HANDLE handle, cUInt32 *UIIR_coef )
{
cUInt32 base = ((ChalAudioCtrlBlk_t*)handle)->audioh_base;
cUInt32 index;
for(index = 0; index < 30; index++)
{
BRCM_WRITE_REG_IDX(base, AUDIOH_EANC_CO_UIIR, index, UIIR_coef[index]);
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_switch_free_channel(CHAL_HANDLE handle, CAPH_SWITCH_CHNL_e channel)
*
* Description: CAPH ASW free channel
*
****************************************************************************/
void chal_caph_switch_free_channel(CHAL_HANDLE handle,
CAPH_SWITCH_CHNL_e channel)
{
chal_caph_switch_cb_t *pchal_cb = (chal_caph_switch_cb_t*)handle;
cUInt8 index;
cUInt8 dst;
cUInt16 reg_idx;
cUInt32 reg_val;
register UInt32 loopCount;
/* Find the channel we are looking for */
for(index = 0; index < CHAL_CAPH_SWITCH_MAX_CHANNELS; index++)
{
if((1UL << index)&channel)
{
/* found the channel we are looking for, make this channel free for next allocation */
pchal_cb->alloc_status[index] = FALSE;
for(dst=0; dst < CHAL_CAPH_SWITCH_MAX_DESTINATIONS; dst++)
{
reg_idx = (index*CHAL_CAPH_SWITCH_CH_REG_SIZE) + (dst*CHAL_CAPH_SWITCH_DST_REG_SIZE);
reg_val = BRCM_READ_REG_IDX( pchal_cb->base, CPH_SSASW_CH01_DST1, reg_idx);
/* Clear destination information */
reg_val &= ~CPH_SSASW_CH01_DST1_CH01_DST1_EN_MASK;
BRCM_WRITE_REG_IDX(pchal_cb->base, CPH_SSASW_CH01_DST1, reg_idx, reg_val);
for (loopCount = 5; loopCount != 0; loopCount--)
reg_val = BRCM_READ_REG_IDX(pchal_cb->base, CPH_SSASW_CH01_DST1, reg_idx);
reg_val &= ~CPH_SSASW_CH01_DST1_CH01_DST1_ADDR_MASK;
BRCM_WRITE_REG_IDX(pchal_cb->base, CPH_SSASW_CH01_DST1, reg_idx,reg_val);
}
break;
}
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_dma_clr_channel_fifo(CHAL_HANDLE handle,
* uint16_t fifo)
*
* Description: clear dma channel internal fifo
*
****************************************************************************/
void chal_caph_dma_clr_channel_fifo(CHAL_HANDLE handle,
uint16_t channel)
{
uint32_t base = ((chal_caph_dma_cb_t*)handle)->base;
uint8_t index;
uint32_t cr;
/* Find the FIFOs we are looking for */
for(index = 0; index < CHAL_CAPH_DMA_MAX_CHANNELS; index++)
{
if((1UL << index)&channel)
{
/* found the Channel we are looking for, Disable the FIFO */
cr = BRCM_READ_REG_IDX( base, CPH_AADMAC_CH1_AADMAC_CR_2, (index*CHAL_CAPH_DMA_CH_REG_SIZE));
/* Send Reset Pulse to the Hardware. First make sure it is 0, set to 1, then clear to 0 */
/* Clear Reset */
cr &= ~CPH_AADMAC_CH1_AADMAC_CR_2_CH1_AADMAC_FIFO_RST_MASK;
BRCM_WRITE_REG_IDX( base, CPH_AADMAC_CH1_AADMAC_CR_2, (index*CHAL_CAPH_DMA_CH_REG_SIZE), cr);
/* Start Reset process on Hardware*/
cr = BRCM_READ_REG_IDX( base, CPH_AADMAC_CH1_AADMAC_CR_2, (index*CHAL_CAPH_DMA_CH_REG_SIZE));
cr |= CPH_AADMAC_CH1_AADMAC_CR_2_CH1_AADMAC_FIFO_RST_MASK;
BRCM_WRITE_REG_IDX( base, CPH_AADMAC_CH1_AADMAC_CR_2, (index*CHAL_CAPH_DMA_CH_REG_SIZE), cr);
/* Clear Reset */
cr = BRCM_READ_REG_IDX( base, CPH_AADMAC_CH1_AADMAC_CR_2, (index*CHAL_CAPH_DMA_CH_REG_SIZE));
cr &= ~CPH_AADMAC_CH1_AADMAC_CR_2_CH1_AADMAC_FIFO_RST_MASK;
BRCM_WRITE_REG_IDX( base, CPH_AADMAC_CH1_AADMAC_CR_2, (index*CHAL_CAPH_DMA_CH_REG_SIZE), cr);
}
}
return;
}
/****************************************************************************
*
* Function Name: cVoid chal_caph_cfifo_set_fifo_thres(CHAL_HANDLE handle,
* CAPH_CFIFO_e fifo,
* cUInt16 thres,
* cUInt16 thres2)
*
* Description: set fifo thresholds
*
****************************************************************************/
cVoid chal_caph_cfifo_set_fifo_thres(CHAL_HANDLE handle,
CAPH_CFIFO_e fifo,
cUInt16 thres, cUInt16 thres2)
{
cUInt32 base = ((chal_caph_cfifo_cb_t *) handle)->base;
cUInt8 index;
cUInt32 cr;
/* Convert them to 32bit sizes */
thres = thres / sizeof(cUInt32);
thres2 = thres2 / sizeof(cUInt32);
/* Find the FIFOs we are looking for */
for (index = 0; index < CHAL_CAPH_CFIFO_MAX_FIFOS; index++) {
if ((1UL << index) & fifo) {
/* found the FIFO, Disable the FIFO */
cr = BRCM_READ_REG_IDX(base, CPH_CFIFO_CPH_CR_1,
(index *
CHAL_CAPH_CFIFO_CR_REG_SIZE));
/* Clear and configure the threshold */
cr &= ~CPH_CFIFO_CPH_CR_1_CH1_THRES_MASK;
thres &=
(CPH_CFIFO_CPH_CR_1_CH1_THRES_MASK >>
CPH_CFIFO_CPH_CR_1_CH1_THRES_SHIFT);
cr |= (thres << CPH_CFIFO_CPH_CR_1_CH1_THRES_SHIFT);
/* Clear and configure the threshold2 */
cr &= ~CPH_CFIFO_CPH_CR_1_CH1_THRES2_MASK;
thres2 &=
(CPH_CFIFO_CPH_CR_1_CH1_THRES2_MASK >>
CPH_CFIFO_CPH_CR_1_CH1_THRES2_SHIFT);
cr |= (thres2 << CPH_CFIFO_CPH_CR_1_CH1_THRES2_SHIFT);
/* Apply the changes to hardware */
BRCM_WRITE_REG_IDX(base, CPH_CFIFO_CPH_CR_1,
(index *
CHAL_CAPH_CFIFO_CR_REG_SIZE), cr);
break;
}
}
/****************************************************************************
*
* Function Name: cVoid chal_caph_dma_set_cfifo(CHAL_HANDLE handle,
* CAPH_DMA_CHANNEL_e channel,
* CAPH_CFIFO_e cfifo_id)
*
* Description: config CAPH DMA channel cfifo channel id
*
****************************************************************************/
cVoid chal_caph_dma_set_cfifo(CHAL_HANDLE handle,
CAPH_DMA_CHANNEL_e channel, CAPH_CFIFO_e cfifo_id)
{
cUInt32 base = ((chal_caph_dma_cb_t *) handle)->base;
cUInt8 index;
cUInt32 cr = 0;
cUInt8 cfifo_ch;
/* Find the channel we are looking for */
for (index = 0; index < CHAL_CAPH_DMA_MAX_CHANNELS; index++) {
if ((1UL << index) & channel) {
cr = BRCM_READ_REG_IDX(base, CPH_AADMAC_CH1_AADMAC_CR_2,
(index *
CHAL_CAPH_DMA_CH_REG_SIZE));
/* configure the CFIFO channel */
cr &=
~CPH_AADMAC_CH1_AADMAC_CR_2_CH1_AADMAC_FIFO_CH_MASK;
/* Find the cfifo channel we are looking for */
for (cfifo_ch = 0;
cfifo_ch < CHAL_CAPH_DMA_MAX_CHANNELS;
cfifo_ch++) {
if ((1UL << cfifo_ch) & cfifo_id) {
cr |=
(cfifo_ch <<
CPH_AADMAC_CH1_AADMAC_CR_2_CH1_AADMAC_FIFO_CH_SHIFT);
break;
}
}
/* Apply the settings in the hardware */
BRCM_WRITE_REG_IDX(base, CPH_AADMAC_CH1_AADMAC_CR_2,
(index * CHAL_CAPH_DMA_CH_REG_SIZE),
cr);
break;
}
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_dma_set_tsize(CHAL_HANDLE handle,
* CAPH_DMA_CHANNEL_e channel,
* uint8_t tsize)
*
* Description: config CAPH DMA channel transfer size
*
****************************************************************************/
void chal_caph_dma_set_tsize(CHAL_HANDLE handle,
CAPH_DMA_CHANNEL_e channel,
uint8_t tsize)
{
uint32_t base = ((chal_caph_dma_cb_t*)handle)->base;
uint8_t index;
uint32_t cr = 0;
/* Find the channel we are looking for */
for(index = 0; index < CHAL_CAPH_DMA_MAX_CHANNELS; index++)
{
if((1UL << index)&channel)
{
cr = BRCM_READ_REG_IDX( base, CPH_AADMAC_CH1_AADMAC_CR_2, (index*CHAL_CAPH_DMA_CH_REG_SIZE));
/* Convert the tsize to the register value,
tSIZE should be in number of 32bit transfers -1 */
if(tsize > sizeof(uint32_t))
{
tsize = (tsize/sizeof(uint32_t)) - 1;
}
else
{
tsize = 0;
}
/* Configure the transfer size per request */
cr &= ~CPH_AADMAC_CH1_AADMAC_CR_2_CH1_AADMAC_TSIZE_PER_REQ_MASK;
cr |= (tsize << CPH_AADMAC_CH1_AADMAC_CR_2_CH1_AADMAC_TSIZE_PER_REQ_SHIFT);
/* Apply the settings in the hardware */
BRCM_WRITE_REG_IDX( base, CPH_AADMAC_CH1_AADMAC_CR_2, (index*CHAL_CAPH_DMA_CH_REG_SIZE), cr);
break;
}
}
return;
}
/****************************************************************************
*
* Function Name: cVoid chal_caph_dma_set_buffer_address(CHAL_HANDLE handle,
* CAPH_DMA_CHANNEL_e channel,
* cUInt32 address)
*
* Description: set CAPH DMA channel buffer address
*
****************************************************************************/
cVoid chal_caph_dma_set_buffer_address(CHAL_HANDLE handle,
CAPH_DMA_CHANNEL_e channel,
cUInt32 address)
{
cUInt32 base = ((chal_caph_dma_cb_t *) handle)->base;
cUInt8 index;
/* Find the channel we are looking for */
for (index = 0; index < CHAL_CAPH_DMA_MAX_CHANNELS; index++) {
if ((1UL << index) & channel) {
/* Set the DMA buffer Address */
address &=
CPH_AADMAC_CH1_AADMAC_CR_1_CH1_AADMAC_BASE_MASK;
BRCM_WRITE_REG_IDX(base, CPH_AADMAC_CH1_AADMAC_CR_1,
(index * CHAL_CAPH_DMA_CH_REG_SIZE),
address);
break;
}
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_dma_disable(CHAL_HANDLE handle,
* uint16_t channel)
*
* Description: disable CAPH DMA channel
*
****************************************************************************/
void chal_caph_dma_disable(CHAL_HANDLE handle,
uint16_t channel)
{
uint32_t base = ((chal_caph_dma_cb_t*)handle)->base;
uint8_t index;
uint32_t reg_val;
/* Find the channel we are looking for */
for(index = 0; index < CHAL_CAPH_DMA_MAX_CHANNELS; index++)
{
if((1UL << index)&channel)
{
/* found the channel we are looking for, disable the channel */
reg_val = BRCM_READ_REG_IDX( base, CPH_AADMAC_CH1_AADMAC_CR_2, (index*CHAL_CAPH_DMA_CH_REG_SIZE));
reg_val &= ~CPH_AADMAC_CH1_AADMAC_CR_2_CH1_AADMAC_EN_MASK;
BRCM_WRITE_REG_IDX(base, CPH_AADMAC_CH1_AADMAC_CR_2, (index*CHAL_CAPH_DMA_CH_REG_SIZE), reg_val);
}
}
return;
}
/****************************************************************************
*
* Function Name: cVoid chal_caph_dma_set_ddrfifo_status(CHAL_HANDLE handle,
* CAPH_DMA_CHANNEL_e channel,
* CAPH_DMA_CHNL_FIFO_STATUS_e status)
*
* Description: set CAPH DMA ddr fifo status
*
****************************************************************************/
static cVoid chal_caph_dma_rheaB0_set_ddrfifo_status(CHAL_HANDLE handle,
CAPH_DMA_CHANNEL_e channel,
CAPH_DMA_CHNL_FIFO_STATUS_e
status)
{
cUInt32 base = ((chal_caph_dma_cb_t *) handle)->base;
cUInt8 index;
cUInt32 cr = 0;
if (cpu_is_rhea_B0()) {
/*-- Rhea B0-- */
for (index = 0; index < CHAL_CAPH_DMA_MAX_CHANNELS; index++) {
if ((1UL << index) & channel) {
/* found the channel, Set the DDR fifo status */
cr = BRCM_READ_REG_IDX(base, CPH_AADMAC_CH1_AADMAC_SR_1,
(index *
CHAL_CAPH_DMA_CH_REG_SIZE));
if (status == CAPH_READY_NONE) {
cr &=
(~CPH_AADMAC_CH1_AADMAC_SR_1_CH1_SW_READY_LOW_MASK);
cr &=
(~CPH_AADMAC_CH1_AADMAC_SR_1_CH1_SW_READY_HIGH_MASK);
BRCM_WRITE_REG_IDX(base,
CPH_AADMAC_CH1_AADMAC_SR_1,
(index *
CHAL_CAPH_DMA_CH_REG_SIZE),
cr);
} else {
#if 0
/* this secion of code has a bug:
*/
if (status & CAPH_READY_LOW) {
cr = CAPH_READY_LOW <<
CPH_AADMAC_CH1_AADMAC_SR_1_CH1_SW_READY_LOW_SHIFT;
BRCM_WRITE_REG_IDX(base,
CPH_AADMAC_CH1_AADMAC_SR_1,
(index *
CHAL_CAPH_DMA_CH_REG_SIZE),
cr);
}
if (status & CAPH_READY_HIGH) {
cr |=
CAPH_READY_HIGH <<
CPH_AADMAC_CH1_AADMAC_SR_1_CH1_SW_READY_LOW_SHIFT;
BRCM_WRITE_REG_IDX(base,
CPH_AADMAC_CH1_AADMAC_SR_1,
(index *
CHAL_CAPH_DMA_CH_REG_SIZE),
cr);
}
#else
cr |=
(status <<
CPH_AADMAC_CH1_AADMAC_SR_1_CH1_SW_READY_LOW_SHIFT);
BRCM_WRITE_REG_IDX(base,
CPH_AADMAC_CH1_AADMAC_SR_1,
(index *
CHAL_CAPH_DMA_CH_REG_SIZE),
cr);
#endif
}
break;
}
}
} else {
/*-- Rhea B1 --*/
/* Find the channel we are looking for */
for (index = 0; index < CHAL_CAPH_DMA_MAX_CHANNELS; index++) {
if ((1UL << index) & channel) {
/* found the channel we are looking for, Set the
DDR fifo status */
cr = BRCM_READ_REG_IDX(base, CPH_AADMAC_CH1_AADMAC_SR_1,
(index *
CHAL_CAPH_DMA_CH_REG_SIZE));
/* mark to preserve HW_RDY bits */
cr |= CPH_AADMAC_CH1_AADMAC_SR_1_CH1_HW_READY_LOW_MASK |
CPH_AADMAC_CH1_AADMAC_SR_1_CH1_HW_READY_HIGH_MASK;
if (status == CAPH_READY_NONE) {
/* set Reset bit */
cr |=
CPH_AADMAC_CH1_AADMAC_SR_1_CH1_AADMAC_FIFO_RST_MASK;
BRCM_WRITE_REG_IDX(base,
CPH_AADMAC_CH1_AADMAC_SR_1,
(index *
CHAL_CAPH_DMA_CH_REG_SIZE),
cr);
/* clear Reset bit */
cr = BRCM_READ_REG_IDX(base,
CPH_AADMAC_CH1_AADMAC_SR_1,
(index*CHAL_CAPH_DMA_CH_REG_SIZE));
cr &=
~CPH_AADMAC_CH1_AADMAC_SR_1_CH1_AADMAC_FIFO_RST_MASK;
cr |=
CPH_AADMAC_CH1_AADMAC_SR_1_CH1_HW_READY_LOW_MASK
| CPH_AADMAC_CH1_AADMAC_SR_1_CH1_HW_READY_HIGH_MASK;
BRCM_WRITE_REG_IDX(base,
CPH_AADMAC_CH1_AADMAC_SR_1,
(index *
CHAL_CAPH_DMA_CH_REG_SIZE),
cr);
return;
}
/* cr already set to CPH_AADMAC_CH1_AADMAC_SR_1_CH1_HW_READY_LOW_MASK |
CPH_AADMAC_CH1_AADMAC_SR_1_CH1_HW_READY_HIGH_MASK */
#if 0 /*no need to separate low and high writes*/
if (status & CAPH_READY_LOW) {
cr |=
CAPH_READY_LOW <<
CPH_AADMAC_CH1_AADMAC_SR_1_CH1_SW_READY_LOW_SHIFT;
BRCM_WRITE_REG_IDX(base,
CPH_AADMAC_CH1_AADMAC_SR_1,
(index *
CHAL_CAPH_DMA_CH_REG_SIZE),
cr);
}
if (status & CAPH_READY_HIGH) {
cr =
CPH_AADMAC_CH1_AADMAC_SR_1_CH1_HW_READY_LOW_MASK |
CPH_AADMAC_CH1_AADMAC_SR_1_CH1_HW_READY_HIGH_MASK;
cr |=
CAPH_READY_HIGH <<
CPH_AADMAC_CH1_AADMAC_SR_1_CH1_SW_READY_LOW_SHIFT;
BRCM_WRITE_REG_IDX(base,
CPH_AADMAC_CH1_AADMAC_SR_1,
(index *
CHAL_CAPH_DMA_CH_REG_SIZE),
cr);
}
#else
cr |= (status <<
CPH_AADMAC_CH1_AADMAC_SR_1_CH1_SW_READY_LOW_SHIFT);
BRCM_WRITE_REG_IDX(base,
CPH_AADMAC_CH1_AADMAC_SR_1,
(index *
CHAL_CAPH_DMA_CH_REG_SIZE),
cr);
#endif
break;
}
}
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_dma_set_buffer(CHAL_HANDLE handle,
* CAPH_DMA_CHANNEL_e channel,
* uint32_t address,
* uint32_t size)
*
* Description: config CAPH DMA channel buffer parameters (address and size)
*
****************************************************************************/
void chal_caph_dma_set_buffer(CHAL_HANDLE handle,
CAPH_DMA_CHANNEL_e channel,
uint32_t address,
uint32_t size)
{
uint32_t base = ((chal_caph_dma_cb_t*)handle)->base;
uint8_t index;
uint32_t cr = 0;
uint32_t maxs = CPH_AADMAC_DMA_MAX_WRAP_SIZE;
uint32_t extds = 0;
if(channel == CAPH_DMA_CH1 || channel == CAPH_DMA_CH2)
{
maxs = CPH_AADMAC_DMA_CH1_2_MAX_WRAP_SIZE;
}
if(size > maxs)
{
size = maxs;
}
/* Set the extended size */
extds = size >> 16;
size &= CPH_AADMAC_CH1_AADMAC_CR_2_CH1_AADMAC_WRAP_MASK;
/* Find the channel we are looking for */
for(index = 0; index < CHAL_CAPH_DMA_MAX_CHANNELS; index++)
{
if((1UL << index)&channel)
{
/* Set the DMA buffer Address */
address &= CPH_AADMAC_CH1_AADMAC_CR_1_CH1_AADMAC_BASE_MASK;
BRCM_WRITE_REG_IDX( base, CPH_AADMAC_CH1_AADMAC_CR_1, (index*CHAL_CAPH_DMA_CH_REG_SIZE), address);
cr = BRCM_READ_REG_IDX( base, CPH_AADMAC_CH1_AADMAC_CR_2, (index*CHAL_CAPH_DMA_CH_REG_SIZE));
/* Configure the size of buffer */
cr &= ~CPH_AADMAC_CH1_AADMAC_CR_2_CH1_AADMAC_WRAP_MASK;
cr |= (size << CPH_AADMAC_CH1_AADMAC_CR_2_CH1_AADMAC_WRAP_SHIFT);
/* Apply the settings in the hardware */
BRCM_WRITE_REG_IDX( base, CPH_AADMAC_CH1_AADMAC_CR_2, (index*CHAL_CAPH_DMA_CH_REG_SIZE), cr);
if(channel == CAPH_DMA_CH1 || channel == CAPH_DMA_CH2)
{
cr = BRCM_READ_REG( base, CPH_AADMAC_CH1_2_EXTENDED_WRAP);
if(channel == CAPH_DMA_CH1)
{
cr &= (~CPH_AADMAC_CH1_2_EXTENDED_WRAP_CH1_AADMAC_WRAP_HIGH_MASK);
cr |= (extds << CPH_AADMAC_CH1_2_EXTENDED_WRAP_CH1_AADMAC_WRAP_HIGH_SHIFT);
}
else
{
cr &= (~CPH_AADMAC_CH1_2_EXTENDED_WRAP_CH2_AADMAC_WRAP_HIGH_MASK);
cr |= (extds << CPH_AADMAC_CH1_2_EXTENDED_WRAP_CH2_AADMAC_WRAP_HIGH_SHIFT);
}
/* Apply the settings in the hardware */
BRCM_WRITE_REG( base, CPH_AADMAC_CH1_2_EXTENDED_WRAP, cr);
}
break;
}
}
return;
}
