static int imx_uart_first_open(int major, int minor, void *arg)
{
rtems_libio_open_close_args_t *args = arg;
imx_uart_data[minor].tty = args->iop->data1;
#if defined(USE_INTERRUPTS)
BSP_install_rtems_irq_handler(&imx_uart_tx_isr_data[minor]);
BSP_install_rtems_irq_handler(&imx_uart_rx_isr_data[minor]);
imx_uart_data[minor].regs->cr1 |= MC9328MXL_UART_CR1_RRDYEN;
#endif
return 0;
}
int timer_instdis(int t, int inst, unsigned period)
{
rtems_irq_connect_data xx;
xx.name = BSP_MISC_IRQ_LOWEST_OFFSET + t;
xx.hdl = timer_isr;
xx.handle = (rtems_irq_hdl_param)t;
xx.on = 0;
xx.off = 0;
xx.isOn = 0;
if ( !inst ) {
openpic_maptimer(t, 0);
openpic_inittimer(t, 0, 0);
}
if ( ! ( inst ? BSP_install_rtems_irq_handler(&xx) : BSP_remove_rtems_irq_handler(&xx) ) ) {
openpic_maptimer(t, 0);
openpic_inittimer(t, 0, 0);
fprintf(stderr,"unable to %s timer ISR #%i\n", inst ? "install" : "remove", t);
return -1;
}
if ( inst ) {
openpic_maptimer( t, 1 );
openpic_inittimer( t, 8 + t, OPENPIC_VEC_SOURCE - BSP_PCI_IRQ_LOWEST_OFFSET + xx.name );
openpic_settimer( t, period, 1 );
}
return 0;
}
/*-------------------------------------------------------------------------+
| Console device driver INITIALIZE entry point.
+--------------------------------------------------------------------------+
| Initilizes the I/O console (keyboard + VGA display) driver.
+--------------------------------------------------------------------------*/
rtems_device_driver
console_initialize(rtems_device_major_number major,
rtems_device_minor_number minor,
void *arg)
{
rtems_status_code status;
/*
* Set up TERMIOS
*/
rtems_termios_initialize ();
/*
* Do device-specific initialization
*/
/* 115200-8-N-1, without hardware flow control */
BSP_uart_init(BSPConsolePort, 115200, CHR_8_BITS, 0, 0, 0);
/* Set interrupt handler */
if(BSPConsolePort == BSP_UART_COM1)
{
console_isr_data.name = BSP_UART_COM1_IRQ;
console_isr_data.hdl = BSP_uart_termios_isr_com1;
}
else
{
assert(BSPConsolePort == BSP_UART_COM2);
console_isr_data.name = BSP_UART_COM2_IRQ;
console_isr_data.hdl = BSP_uart_termios_isr_com2;
}
status = BSP_install_rtems_irq_handler(&console_isr_data);
if (!status){
printk("Error installing serial console interrupt handler!\n");
rtems_fatal_error_occurred(status);
}
/*
* Register the device
*/
status = rtems_io_register_name ("/dev/console", major, 0);
if (status != RTEMS_SUCCESSFUL)
{
printk("Error registering console device!\n");
rtems_fatal_error_occurred (status);
}
if(BSPConsolePort == BSP_UART_COM1)
{
printk("Initialized console on port COM1 115200-8-N-1\n\n");
}
else
{
printk("Initialized console on port COM2 115200-8-N-1\n\n");
}
return RTEMS_SUCCESSFUL;
} /* console_initialize */
void Install_clock(void (*clock_isr)(void *))
{
/*
* initialize the interval here
* First tick is set to right amount of time in the future
* Future ticks will be incremented over last value set
* in order to provide consistent clicks in the face of
* interrupt overhead
*/
rtems_irq_connect_data clockIrqConnData;
Clock_driver_ticks = 0;
clockIrqConnData.on = ClockOn;
clockIrqConnData.off = ClockOff;
clockIrqConnData.isOn = ClockIsOn;
clockIrqConnData.name = BSP_PIT;
clockIrqConnData.hdl = clock_isr;
if ( ! BSP_install_rtems_irq_handler (&clockIrqConnData)) {
printk("Unable to connect Clock Irq handler\n");
rtems_fatal_error_occurred(1);
}
atexit(Clock_exit);
}
void xilTemacStop(struct ifnet *ifp)
{
struct XilTemac* xilTemac = ifp->if_softc;
uint32_t base = xilTemac->iAddr;
/* Disable ipif interrupts */
OUT32(base + XTE_DGIE_OFFSET, 0);
/* Disable the receiver */
uint32_t rxc1 = IN32(base + XTE_ERXC1_OFFSET);
rxc1 &= ~XTE_ERXC1_RXEN_MASK;
OUT32(base + XTE_ERXC1_OFFSET, rxc1);
/* If receiver was receiving a packet when we disabled it, it will be
* rejected, clear appropriate status bit */
uint32_t ipisr = IN32(base + XTE_IPISR_OFFSET);
if( ipisr & XTE_IPXR_RECV_REJECT_MASK ) {
OUT32(base + XTE_IPISR_OFFSET, XTE_IPXR_RECV_REJECT_MASK);
}
#if PPC_HAS_CLASSIC_EXCEPTIONS
if( xilTemac->iOldHandler )
{
opb_intc_set_vector( xilTemac->iOldHandler, xilTemac->iIsrVector, NULL );
xilTemac->iOldHandler = 0;
}
#else
if( xilTemac->iOldHandler.name != 0)
{
BSP_install_rtems_irq_handler (&xilTemac->iOldHandler);
}
#endif
ifp->if_flags &= ~IFF_RUNNING;
}
void
ReInstall_clock(void (*new_clock_isr)(void *))
{
uint32_t isrlevel = 0;
rtems_irq_connect_data clockIrqConnData;
rtems_interrupt_disable(isrlevel);
clockIrqConnData.name = BSP_PIT;
if ( ! BSP_get_current_rtems_irq_handler(&clockIrqConnData)) {
printk("Unable to stop system clock\n");
rtems_fatal_error_occurred(1);
}
BSP_remove_rtems_irq_handler (&clockIrqConnData);
clockIrqConnData.on = ClockOn;
clockIrqConnData.off = ClockOff;
clockIrqConnData.isOn = ClockIsOn;
clockIrqConnData.name = BSP_PIT;
clockIrqConnData.hdl = new_clock_isr;
if (!BSP_install_rtems_irq_handler (&clockIrqConnData)) {
printk("Unable to connect Clock Irq handler\n");
rtems_fatal_error_occurred(1);
}
rtems_interrupt_enable(isrlevel);
}
bool vgacons_probe(
int minor
)
{
int status;
static bool firstTime = true;
if ((*(unsigned char*) NB_MAX_ROW_ADDR == 0) &&
(*(unsigned short*)NB_MAX_COL_ADDR == 0)) {
return false;
}
/*
* If there is a video card, let's assume there is also a keyboard.
* The means that we need the ISR installed in case someone wants to
* use the Keyboard or PS2 Mouse. With Microwindows, the console
* can be COM1 and you can still use the mouse/VGA for graphics.
*/
if ( firstTime ) {
status = BSP_install_rtems_irq_handler(&keyboard_isr_data);
if (!status) {
printk("Error installing keyboard interrupt handler!\n");
rtems_fatal_error_occurred(status);
}
}
firstTime = false;
return true;
}
/*
* ns16550_initialize_interrupts
*
* This routine initializes the port to operate in interrupt driver mode.
*/
NS16550_STATIC void ns16550_initialize_interrupts( int minor)
{
#if defined(BSP_FEATURE_IRQ_EXTENSION) || defined(BSP_FEATURE_IRQ_LEGACY)
console_tbl *c = Console_Port_Tbl [minor];
#endif
console_data *d = &Console_Port_Data [minor];
d->bActive = false;
#ifdef BSP_FEATURE_IRQ_EXTENSION
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
sc = rtems_interrupt_handler_install(
c->ulIntVector,
"NS16550",
RTEMS_INTERRUPT_SHARED,
ns16550_isr,
(void *) minor
);
if (sc != RTEMS_SUCCESSFUL) {
/* FIXME */
printk( "%s: Error: Install interrupt handler\n", __func__);
rtems_fatal_error_occurred( 0xdeadbeef);
}
}
#elif defined(BSP_FEATURE_IRQ_LEGACY)
{
int rv = 0;
#ifdef BSP_FEATURE_IRQ_LEGACY_SHARED_HANDLER_SUPPORT
rtems_irq_connect_data cd = {
c->ulIntVector,
ns16550_isr,
(void *) minor,
NULL,
NULL,
NULL,
NULL
};
rv = BSP_install_rtems_shared_irq_handler( &cd);
#else
rtems_irq_connect_data cd = {
c->ulIntVector,
ns16550_isr,
(void *) minor,
NULL,
NULL,
NULL
};
rv = BSP_install_rtems_irq_handler( &cd);
#endif
if (rv == 0) {
/* FIXME */
printk( "%s: Error: Install interrupt handler\n", __func__);
rtems_fatal_error_occurred( 0xdeadbeef);
}
}
#endif
}
/*
* MPC5x00 slt device driver initialize
*/
rtems_device_driver slt_initialize
(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *pargp
)
{
/* force minor according to definitions in bsp.h */
if(USE_SLICETIMER_0)
{
Install_slt(0);
if(!BSP_install_rtems_irq_handler(&slt0_IrqData))
{
printk("Unable to connect PSC Irq handler\n");
rtems_fatal_error_occurred(1);
}
}
if(USE_SLICETIMER_1)
{
Install_slt(1);
if(!BSP_install_rtems_irq_handler(&slt1_IrqData))
{
printk("Unable to connect PSC Irq handler\n");
rtems_fatal_error_occurred(1);
}
}
return RTEMS_SUCCESSFUL;
}
void at91rm9200_emac_init(void *arg)
{
at91rm9200_emac_softc_t *sc = arg;
struct ifnet *ifp = &sc->arpcom.ac_if;
/*
*This is for stuff that only gets done once (at91rm9200_emac_init()
* gets called multiple times
*/
if (sc->txDaemonTid == 0) {
/* Set up EMAC hardware */
at91rm9200_emac_init_hw(sc);
/* Start driver tasks */
sc->rxDaemonTid = rtems_bsdnet_newproc("ENrx",
4096,
at91rm9200_emac_rxDaemon,
sc);
sc->txDaemonTid = rtems_bsdnet_newproc("ENtx",
4096,
at91rm9200_emac_txDaemon,
sc);
} /* if txDaemonTid */
/* set our priority in the AIC */
AIC_SMR_REG(AIC_SMR_EMAC) = AIC_SMR_PRIOR(EMAC_INT_PRIORITY);
/* install the interrupt handler */
BSP_install_rtems_irq_handler(&at91rm9200_emac_isr_data);
/* EMAC doesn't support promiscuous, so ignore requests */
if (ifp->if_flags & IFF_PROMISC) {
printk ("Warning - AT91RM9200 Ethernet driver"
" doesn't support Promiscuous Mode!\n");
}
/*
* Tell the world that we're running.
*/
ifp->if_flags |= IFF_RUNNING;
/* Enable TX/RX and clear the statistics counters */
EMAC_REG(EMAC_CTL) = (EMAC_CTL_TE | EMAC_CTL_RE | EMAC_CTL_CSR);
/* clear any pending interrupts */
EMAC_REG(EMAC_TSR) = 0xffffffff;
EMAC_REG(EMAC_RSR) = 0xffffffff;
} /* at91rm9200_emac_init() */
static void InstallIRQHandler(rtems_irq_number id,
rtems_irq_hdl handler,
rtems_irq_enable turnOn,
rtems_irq_disable turnOff)
{
rtems_irq_connect_data params;
params.name = id;
params.hdl = handler;
params.on = turnOn;
params.off = turnOff;
params.isOn = NULL;
params.handle = NULL;
if (! BSP_install_rtems_irq_handler(¶ms))
rtems_panic ("Can't install interrupt handler");
}
/*=========================================================================*\
| Function: |
\*-------------------------------------------------------------------------*/
static void m8xx_spi_install_irq_handler
(
/*-------------------------------------------------------------------------*\
| Purpose: |
| install the interrupt handler |
+---------------------------------------------------------------------------+
| Input Parameters: |
\*-------------------------------------------------------------------------*/
m8xx_spi_softc_t *softc_ptr, /* ptr to control structure */
int install /* TRUE: install, FALSE: remove */
)
/*-------------------------------------------------------------------------*\
| Return Value: |
| <none> |
\*=========================================================================*/
{
rtems_status_code rc = RTEMS_SUCCESSFUL;
/*
* install handler for SPI device
*/
/*
* create semaphore for IRQ synchronization
*/
rc = rtems_semaphore_create(rtems_build_name('s','p','i','s'),
0,
RTEMS_FIFO
| RTEMS_SIMPLE_BINARY_SEMAPHORE,
0,
&softc_ptr->irq_sema_id);
if (rc != RTEMS_SUCCESSFUL) {
rtems_panic("SPI: cannot create semaphore");
}
if (rc == RTEMS_SUCCESSFUL) {
rtems_irq_connect_data irq_conn_data = {
BSP_CPM_IRQ_SPI,
m8xx_spi_irq_handler, /* rtems_irq_hdl */
(rtems_irq_hdl_param)softc_ptr, /* (rtems_irq_hdl_param) */
mpc8xx_spi_irq_on, /* (rtems_irq_enable) */
mpc8xx_spi_irq_off, /* (rtems_irq_disable) */
mpc8xx_spi_irq_isOn /* (rtems_irq_is_enabled) */
};
if (!BSP_install_rtems_irq_handler (&irq_conn_data)) {
rtems_panic("SPI: cannot install IRQ handler");
}
}
}
rtems_device_driver Clock_initialize(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *pargp
)
{
unsigned timer_counter_init_value;
unsigned char clock_lsb, clock_msb;
Clock_driver_ticks = 0;
Clock_isrs =
Clock_initial_isr_value =
rtems_configuration_get_microseconds_per_tick() / 1000; /* ticks per clock_isr */
/*
* configure the counter timer ( should be based on microsecs/tick )
* NB. The divisor(Clock_isrs) resolves the is the same number that appears in confdefs.h
* when setting the microseconds_per_tick value.
*/
ClockOff ( &clockIrqData );
timer_counter_init_value = rtems_configuration_get_microseconds_per_tick() / Clock_isrs;
clock_lsb = (unsigned char)timer_counter_init_value;
clock_msb = timer_counter_init_value >> 8;
outport_byte ( TMRCON , 0x34 );
outport_byte ( TMR0 , clock_lsb ); /* load LSB first */
outport_byte ( TMR0 , clock_msb ); /* then MSB */
if (!BSP_install_rtems_irq_handler (&clockIrqData)) {
printk("Unable to initialize system clock\n");
rtems_fatal_error_occurred(1);
}
/*
* make major/minor avail to others such as shared memory driver
*/
rtems_clock_major = major;
rtems_clock_minor = minor;
return RTEMS_SUCCESSFUL;
}
/*
* Serial Mouse - device driver INITIALIZE entry point.
*/
rtems_device_driver
serial_mouse_initialize(rtems_device_major_number major,
rtems_device_minor_number minor,
void *arg)
{
rtems_status_code status;
/* Check if this port is not been used as console */
if( BSPConsolePort == BSP_UART_PORT )
{
status = -1;
printk("SERIAL MOUSE: port selected as console.( %d )\n", BSP_UART_PORT );
rtems_fatal_error_occurred( status );
}
/*
* Set up TERMIOS
*/
rtems_termios_initialize();
/*
* Do device-specific initialization
*/
/* 9600-8-N-1, without hardware flow control */
BSP_uart_init( BSP_UART_PORT, 1200, CHR_8_BITS, 0, 0, 0 );
status = BSP_install_rtems_irq_handler( &serial_mouse_isr_data );
if( !status )
{
printk("Error installing serial mouse interrupt handler!\n");
rtems_fatal_error_occurred(status);
}
/*
* Register the device
*/
status = rtems_io_register_name ("/dev/mouse", major, 0);
if (status != RTEMS_SUCCESSFUL)
{
printk("Error registering /dev/mouse device!\n");
rtems_fatal_error_occurred (status);
}
printk("Device: /dev/mouse on COM%d -- ok \n", BSP_UART_PORT );
return RTEMS_SUCCESSFUL;
} /* tty_initialize */
int BSP_connect_clock_handler (rtems_irq_hdl hdl)
{
if (!BSP_get_current_rtems_irq_handler(&clockIrqData)) {
printk("Unable to get system clock handler\n");
rtems_fatal_error_occurred(1);
}
if (!BSP_remove_rtems_irq_handler (&clockIrqData)) {
printk("Unable to remove current system clock handler\n");
rtems_fatal_error_occurred(1);
}
/*
* Reinit structure
*/
clockIrqData.name = BSP_PERIODIC_TIMER;
clockIrqData.hdl = (rtems_irq_hdl) hdl;
clockIrqData.on = (rtems_irq_enable)clockOn;
clockIrqData.off = (rtems_irq_enable)clockOff;
clockIrqData.isOn = (rtems_irq_is_enabled)clockIsOn;
return BSP_install_rtems_irq_handler (&clockIrqData);
}
static int open_aux(void)
{
int status;
if (aux_count++) {
return 0;
}
queue->head = queue->tail = 0; /* Flush input queue */
status = BSP_install_rtems_irq_handler( &ps2_isr_data );
if( !status ) {
printk("Error installing ps2-mouse interrupt handler!\n" );
rtems_fatal_error_occurred( status );
}
kbd_write_command_w(KBD_CCMD_MOUSE_ENABLE); /* Enable the auxiliary port on
controller. */
aux_write_ack(AUX_ENABLE_DEV); /* Enable aux device */
kbd_write_cmd(AUX_INTS_ON); /* Enable controller ints */
return 0;
}
void xilTemacStart(struct ifnet *ifp)
{
if( (ifp->if_flags & IFF_RUNNING) == 0 )
{
struct XilTemac* xilTemac = ifp->if_softc;
uint32_t base = xilTemac->iAddr;
/* Reset plb temac */
OUT32(base + XTE_DSR_OFFSET, XTE_DSR_RESET_MASK);
/* Don't have usleep on rtems 4.6
usleep(1);
*/
/* @ fastest ppc clock of 500 MHz = 2ns clk */
uint32_t i = 0;
for( i = 0; i < 1 * 500; i++) {
}
/* Reset hard temac */
OUT32(base + XTE_CR_OFFSET, XTE_CR_HTRST_MASK);
/* Don't have usleep on rtems 4.6
usleep(4);
*/
for( i = 0; i < 4 * 500; i++) {
}
/* Disable the receiver -- no need to disable xmit as we control that ;) */
uint32_t rxc1 = IN32(base + XTE_ERXC1_OFFSET);
rxc1 &= ~XTE_ERXC1_RXEN_MASK;
OUT32(base + XTE_ERXC1_OFFSET, rxc1);
/* If receiver was receiving a packet when we disabled it, it will be
* rejected, clear appropriate status bit */
uint32_t ipisr = IN32(base + XTE_IPISR_OFFSET);
if( ipisr & XTE_IPXR_RECV_REJECT_MASK ) {
OUT32(base + XTE_IPISR_OFFSET, XTE_IPXR_RECV_REJECT_MASK);
}
/* Setup IPIF interrupt enables */
uint32_t dier = XTE_DXR_CORE_MASK | XTE_DXR_DPTO_MASK | XTE_DXR_TERR_MASK;
dier |= XTE_DXR_RECV_FIFO_MASK | XTE_DXR_SEND_FIFO_MASK;
OUT32(base + XTE_DIER_OFFSET, dier);
/* Set the mac address */
xilTemacSetMacAddress( ifp, xilTemac->iArpcom.ac_enaddr);
/* Set the link speed */
uint32_t emcfg = IN32(base + XTE_ECFG_OFFSET);
printk("xiltemacStart, default linkspeed: %08x\n", emcfg);
emcfg = (emcfg & ~XTE_ECFG_LINKSPD_MASK) | XTE_ECFG_LINKSPD_100;
OUT32(base + XTE_ECFG_OFFSET, emcfg);
/* Set phy divisor and enable mdio. For a plb bus freq of 150MHz (the
maximum as of Virtex4 Fx), a divisor of 29 gives a mdio clk freq of
2.5MHz (see Xilinx docs for equation), the maximum in the phy standard.
For slower plb frequencies, slower mkdio clks will result. They may not
be optimal, but they should work. */
uint32_t divisor = 29;
OUT32(base + XTE_EMC_OFFSET, divisor | XTE_EMC_MDIO_MASK);
#if PPC_HAS_CLASSIC_EXCEPTIONS /* old connect code */
/* Connect isr vector */
rtems_status_code sc;
extern rtems_isr xilTemacIsr( rtems_vector_number aVector );
sc = opb_intc_set_vector( xilTemacIsr, xilTemac->iIsrVector, &xilTemac->iOldHandler );
if( sc != RTEMS_SUCCESSFUL )
{
xilTemac->iOldHandler = 0;
printk("%s: Could not set interrupt vector for interface '%s' opb_intc_set_vector ret: %d\n", DRIVER_PREFIX, xilTemac->iUnitName, sc );
assert(0);
}
#else
{
rtems_irq_connect_data IrqConnData;
/*
*get old irq handler
*/
xilTemac->iOldHandler.name = xilTemac->iIsrVector;
if (!BSP_get_current_rtems_irq_handler (&xilTemac->iOldHandler)) {
xilTemac->iOldHandler.name = 0;
printk("%s: Unable to detect previous Irq handler\n",DRIVER_PREFIX);
rtems_fatal_error_occurred(1);
}
IrqConnData.on = xilTemacIsrOn;
IrqConnData.off = xilTemacIsrOff;
IrqConnData.isOn = xilTemacIsrIsOn;
IrqConnData.name = xilTemac->iIsrVector;
IrqConnData.hdl = xilTemacIsr;
IrqConnData.handle = xilTemac;
if (!BSP_install_rtems_irq_handler (&IrqConnData)) {
printk("%s: Unable to connect Irq handler\n",DRIVER_PREFIX);
rtems_fatal_error_occurred(1);
}
}
#endif
/* Enable promiscuous mode -- The temac only supports full duplex, which
means we're plugged into a switch. Thus promiscuous mode simply means
we get all multicast addresses*/
OUT32(base + XTE_EAFM_OFFSET, XTE_EAFM_EPPRM_MASK);
/* Setup and enable receiver */
rxc1 = XTE_ERXC1_RXFCS_MASK | XTE_ERXC1_RXEN_MASK | XTE_ERXC1_RXVLAN_MASK;
OUT32(base + XTE_ERXC1_OFFSET, rxc1);
/* Setup and enable transmitter */
uint32_t txc = XTE_ETXC_TXEN_MASK | XTE_ETXC_TXVLAN_MASK;
OUT32(base + XTE_ETXC_OFFSET, txc);
/* Enable interrupts for temac */
uint32_t ipier = IN32(base + XTE_IPIER_OFFSET);
ipier |= (XTE_IPXR_XMIT_ERROR_MASK);
ipier |= (XTE_IPXR_RECV_ERROR_MASK | XTE_IPXR_RECV_DONE_MASK);
ipier |= (XTE_IPXR_AUTO_NEG_MASK);
OUT32(base + XTE_IPIER_OFFSET, ipier);
printk("%s: xiltemacStart, ipier: %08x\n",DRIVER_PREFIX, ipier);
/* Enable device global interrutps */
OUT32(base + XTE_DGIE_OFFSET, XTE_DGIE_ENABLE_MASK);
ifp->if_flags |= IFF_RUNNING;
}
}
static void
m8xx_fec_initialize_hardware (struct m8xx_fec_enet_struct *sc)
{
int i;
unsigned char *hwaddr;
/*
* Issue reset to FEC
*/
m8xx.fec.ecntrl=0x1;
/*
* Put ethernet transciever in reset
*/
m8xx.pgcra |= 0x80;
/*
* Configure I/O ports
*/
m8xx.pdpar = 0x1fff;
m8xx.pddir = 0x1c58;
/*
* Take ethernet transciever out of reset
*/
m8xx.pgcra &= ~0x80;
/*
* Set SIU interrupt level to LVL2
*
*/
m8xx.fec.ivec = ((((unsigned) BSP_FAST_ETHERNET_CTRL)/2) << 29);
/*
* Set the TX and RX fifo sizes. For now, we'll split it evenly
*/
/* If you uncomment these, the FEC will not work right.
m8xx.fec.r_fstart = ((m8xx.fec.r_bound & 0x3ff) >> 2) & 0x3ff;
m8xx.fec.x_fstart = 0;
*/
/*
* Set our physical address
*/
hwaddr = sc->arpcom.ac_enaddr;
m8xx.fec.addr_low = (hwaddr[0] << 24) | (hwaddr[1] << 16) |
(hwaddr[2] << 8) | (hwaddr[3] << 0);
m8xx.fec.addr_high = (hwaddr[4] << 24) | (hwaddr[5] << 16);
/*
* Clear the hash table
*/
m8xx.fec.hash_table_high = 0;
m8xx.fec.hash_table_low = 0;
/*
* Set up receive buffer size
*/
m8xx.fec.r_buf_size = 0x5f0; /* set to 1520 */
/*
* Allocate mbuf pointers
*/
sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf,
M_MBUF, M_NOWAIT);
sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf,
M_MBUF, M_NOWAIT);
if (!sc->rxMbuf || !sc->txMbuf)
rtems_panic ("No memory for mbuf pointers");
/*
* Set receiver and transmitter buffer descriptor bases
*/
sc->rxBdBase = m8xx_bd_allocate(sc->rxBdCount);
sc->txBdBase = m8xx_bd_allocate(sc->txBdCount);
m8xx.fec.r_des_start = (int)sc->rxBdBase;
m8xx.fec.x_des_start = (int)sc->txBdBase;
/*
* Set up Receive Control Register:
* Not promiscuous mode
* MII mode
* Half duplex
* No loopback
*/
m8xx.fec.r_cntrl = 0x00000006;
/*
* Set up Transmit Control Register:
* Full duplex
* No heartbeat
*/
m8xx.fec.x_cntrl = M8xx_FEC_X_CNTRL_FDEN;
/*
* Set up DMA function code:
* Big-endian
* DMA functino code = 0
*/
m8xx.fec.fun_code = 0x78000000;
/*
* Initialize SDMA configuration register
* SDMA ignores FRZ
* FEC not aggressive
* FEC arbitration ID = 0 => U-bus arbitration = 6
* RISC arbitration ID = 1 => U-bus arbitration = 5
*/
m8xx.sdcr = 1;
/*
* Set up receive buffer descriptors
*/
for (i = 0 ; i < sc->rxBdCount ; i++)
(sc->rxBdBase + i)->status = 0;
/*
* Set up transmit buffer descriptors
*/
for (i = 0 ; i < sc->txBdCount ; i++) {
(sc->txBdBase + i)->status = 0;
sc->txMbuf[i] = NULL;
}
sc->txBdHead = sc->txBdTail = 0;
sc->txBdActiveCount = 0;
/*
* Mask all FEC interrupts and clear events
*/
m8xx.fec.imask = M8xx_FEC_IEVENT_TFINT |
M8xx_FEC_IEVENT_RFINT;
m8xx.fec.ievent = ~0;
/*
* Set up interrupts
*/
if (!BSP_install_rtems_irq_handler (ðernetFECIrqData))
rtems_panic ("Can't attach M860 FEC interrupt handler\n");
}
rtems_device_driver Clock_initialize(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *pargp
)
{
unsigned timer_counter_init_value;
unsigned char clock_lsb, clock_msb;
#ifdef BSP_DEBUG
printk("Initializing clock driver in Clock_initialize().\n");
#endif
#ifdef LOAD_RTC_AT_START
/* Initialize clock from on-board real time clock. This breaks the */
/* test code which assumes which assumes the application will do it. */
{
rtems_time_of_day now;
#ifdef BSP_DEBUG
printk("Loading clock from on-board real-time clock.\n");
#endif
init_rtc();
if (rtc_read(&now) >= 0)
rtems_clock_set(&now);
}
#endif
Clock_driver_ticks = 0;
Clock_isrs =
Clock_initial_isr_value =
rtems_configuration_get_microseconds_per_tick() / 1000; /* ticks per clock_isr */
/*
* configure the counter timer ( should be based on microsecs/tick )
* NB. The divisor(Clock_isrs) resolves the is the same number that appears in confdefs.h
* when setting the microseconds_per_tick value.
*/
ClockOff ( &clockIrqData );
timer_counter_init_value = rtems_configuration_get_microseconds_per_tick() / Clock_isrs;
clock_lsb = (unsigned char)timer_counter_init_value;
clock_msb = timer_counter_init_value >> 8;
outport_byte (TIMER_MODE, TIMER_SEL0|TIMER_16BIT|TIMER_RATEGEN);
outport_byte (TIMER_CNTR0, clock_lsb ); /* load LSB first */
outport_byte (TIMER_CNTR0, clock_msb ); /* then MSB */
if (!BSP_install_rtems_irq_handler (&clockIrqData)) {
printk("Unable to initialize system clock\n");
rtems_fatal_error_occurred(1);
}
/*
* make major/minor avail to others such as shared memory driver
*/
rtems_clock_major = major;
rtems_clock_minor = minor;
return RTEMS_SUCCESSFUL;
}
static void
sccInitialize (int chan)
{
int i;
/*
* allocate buffers
* FIXME: use a cache-line size boundary alloc here
*/
rxBuf[chan] = malloc(sizeof(*rxBuf[chan]) + 2*PPC_CACHE_ALIGNMENT);
if (rxBuf[chan] == NULL) {
BSP_panic("Cannot allocate console rx buffer\n");
}
else {
/*
* round up rxBuf[chan] to start at a cache line size
*/
rxBuf[chan] = (sccRxBuf_t *)
(((uint32_t)rxBuf[chan]) +
(PPC_CACHE_ALIGNMENT
- ((uint32_t)rxBuf[chan]) % PPC_CACHE_ALIGNMENT));
}
/*
* Allocate buffer descriptors
*/
sccCurrRxBd[chan] =
sccFrstRxBd[chan] = m8xx_bd_allocate(SCC_RXBD_CNT);
sccPrepTxBd[chan] =
sccDequTxBd[chan] =
sccFrstTxBd[chan] = m8xx_bd_allocate(SCC_TXBD_CNT);
switch(chan) {
case CONS_CHN_SCC1:
/*
* Configure port A pins to enable TXD1 and RXD1 pins
* FIXME: add setup for modem control lines....
*/
m8xx.papar |= 0x03;
m8xx.padir &= ~0x03;
/*
* Configure port C pins to enable RTS1 pins (static active low)
*/
m8xx.pcpar &= ~0x01;
m8xx.pcso &= ~0x01;
m8xx.pcdir |= 0x01;
m8xx.pcdat &= ~0x01;
break;
case CONS_CHN_SCC2:
/*
* Configure port A pins to enable TXD2 and RXD2 pins
* FIXME: add setup for modem control lines....
*/
m8xx.papar |= 0x0C;
m8xx.padir &= ~0x0C;
/*
* Configure port C pins to enable RTS2 pins (static active low)
*/
m8xx.pcpar &= ~0x02;
m8xx.pcso &= ~0x02;
m8xx.pcdir |= 0x02;
m8xx.pcdat &= ~0x02;
break;
case CONS_CHN_SCC3:
/*
* Configure port A pins to enable TXD3 and RXD3 pins
* FIXME: add setup for modem control lines....
*/
m8xx.papar |= 0x30;
m8xx.padir &= ~0x30;
/*
* Configure port C pins to enable RTS3 (static active low)
*/
m8xx.pcpar &= ~0x04;
m8xx.pcso &= ~0x04;
m8xx.pcdir |= 0x04;
m8xx.pcdat &= ~0x04;
break;
case CONS_CHN_SCC4:
/*
* Configure port A pins to enable TXD4 and RXD4 pins
* FIXME: add setup for modem control lines....
*/
m8xx.papar |= 0xC0;
m8xx.padir &= ~0xC0;
/*
* Configure port C pins to enable RTS4 pins (static active low)
*/
m8xx.pcpar &= ~0x08;
m8xx.pcso &= ~0x08;
m8xx.pcdir |= 0x08;
m8xx.pcdat &= ~0x08;
break;
case CONS_CHN_SMC1:
/*
* Configure port B pins to enable SMTXD1 and SMRXD1 pins
*/
m8xx.pbpar |= 0xC0;
m8xx.pbdir &= ~0xC0;
break;
case CONS_CHN_SMC2:
/*
* Configure port B pins to enable SMTXD2 and SMRXD2 pins
*/
m8xx.pbpar |= 0xC00;
m8xx.pbdir &= ~0xC00;
break;
}
/*
* allocate and connect BRG
*/
sccBRGalloc(chan,9600);
/*
* Set up SCCx parameter RAM common to all protocols
*/
CHN_PARAM_SET(chan,rbase,(char *)sccFrstRxBd[chan] - (char *)&m8xx);
CHN_PARAM_SET(chan,tbase,(char *)sccFrstTxBd[chan] - (char *)&m8xx);
CHN_PARAM_SET(chan,rfcr ,M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0));
CHN_PARAM_SET(chan,tfcr ,M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0));
if (m8xx_scc_mode[chan] != TERMIOS_POLLED)
CHN_PARAM_SET(chan,mrblr,RXBUFSIZE);
else
CHN_PARAM_SET(chan,mrblr,1);
/*
* Set up SCCx parameter RAM UART-specific parameters
*/
CHN_PARAM_SET(chan,un.uart.max_idl ,MAX_IDL_DEFAULT);
CHN_PARAM_SET(chan,un.uart.brkln ,0);
CHN_PARAM_SET(chan,un.uart.brkec ,0);
CHN_PARAM_SET(chan,un.uart.brkcr ,0);
if (m8xx_console_chan_desc[chan].is_scc) {
m8xx_console_chan_desc[chan].parms.sccp->un.uart.character[0]=0x8000; /* no char filter */
m8xx_console_chan_desc[chan].parms.sccp->un.uart.rccm=0x80FF; /* control character mask */
}
/*
* Set up the Receive Buffer Descriptors
*/
for (i = 0;i < SCC_RXBD_CNT;i++) {
sccFrstRxBd[chan][i].status = M8xx_BD_EMPTY | M8xx_BD_INTERRUPT;
if (i == SCC_RXBD_CNT-1) {
sccFrstRxBd[chan][i].status |= M8xx_BD_WRAP;
}
sccFrstRxBd[chan][i].length = 0;
sccFrstRxBd[chan][i].buffer = (*rxBuf[chan])[i];
}
/*
* Setup the Transmit Buffer Descriptor
*/
for (i = 0;i < SCC_TXBD_CNT;i++) {
sccFrstTxBd[chan][i].status = M8xx_BD_INTERRUPT;
if (i == SCC_TXBD_CNT-1) {
sccFrstTxBd[chan][i].status |= M8xx_BD_WRAP;
}
sccFrstTxBd[chan][i].length = 0;
sccFrstTxBd[chan][i].buffer = NULL;
}
/*
* Set up SCC general and protocol-specific mode registers
*/
CHN_EVENT_CLR(chan,~0); /* Clear any pending events */
CHN_MASK_SET(chan,0); /* Mask all interrupt/event sources */
if (m8xx_console_chan_desc[chan].is_scc) {
m8xx_console_chan_desc[chan].regs.sccr->psmr = 0xb000; /* 8N1, CTS flow control */
m8xx_console_chan_desc[chan].regs.sccr->gsmr_h = 0x00000000;
m8xx_console_chan_desc[chan].regs.sccr->gsmr_l = 0x00028004; /* UART mode */
}
else {
m8xx_console_chan_desc[chan].regs.smcr->smcmr = 0x4820;
}
/*
* Send "Init parameters" command
*/
m8xx_cp_execute_cmd(M8xx_CR_OP_INIT_RX_TX
| m8xx_console_chan_desc[chan].cr_chan_code);
/*
* Enable receiver and transmitter
*/
if (m8xx_console_chan_desc[chan].is_scc) {
m8xx_console_chan_desc[chan].regs.sccr->gsmr_l |= 0x00000030;
}
else {
m8xx_console_chan_desc[chan].regs.smcr->smcmr |= 0x0003;
}
if (m8xx_scc_mode[chan] != TERMIOS_POLLED) {
rtems_irq_connect_data irq_conn_data = {
m8xx_console_chan_desc[chan].ivec_src,
sccInterruptHandler, /* rtems_irq_hdl */
(rtems_irq_hdl_param)chan, /* (rtems_irq_hdl_param) */
mpc8xx_console_irq_on, /* (rtems_irq_enable) */
mpc8xx_console_irq_off, /* (rtems_irq_disable) */
mpc8xx_console_irq_isOn /* (rtems_irq_is_enabled) */
};
if (!BSP_install_rtems_irq_handler (&irq_conn_data)) {
rtems_panic("console: cannot install IRQ handler");
}
}
}
void cs8900_attach_interrupt (cs8900_device *cs)
{
g_cs = cs;
BSP_install_rtems_irq_handler(&cs8900_isr_data);
}
void mc9328mxl_enet_init_hw(mc9328mxl_enet_softc_t *sc)
{
uint16_t stat;
uint16_t my = 0;
lan91c11x_write_reg(LAN91C11X_RCR, LAN91C11X_RCR_RST);
lan91c11x_write_reg(LAN91C11X_RCR, 0);
rtems_task_wake_after(1);
/* Reset the PHY */
lan91c11x_write_phy_reg(PHY_CTRL, PHY_CTRL_RST);
while(lan91c11x_read_phy_reg(PHY_CTRL) & PHY_CTRL_RST) {
rtems_task_wake_after(1);
}
stat = lan91c11x_read_phy_reg(PHY_STAT);
if(stat & PHY_STAT_CAPT4) {
my |= PHY_ADV_T4;
}
/* 100Mbs doesn't work, so we won't advertise it */
if(stat & PHY_STAT_CAPTXF) {
my |= PHY_ADV_TXFDX;
}
if(stat & PHY_STAT_CAPTXH) {
my |= PHY_ADV_TXHDX;
}
if(stat & PHY_STAT_CAPTF) {
my |= PHY_ADV_10FDX;
}
if(stat & PHY_STAT_CAPTH) {
my |= PHY_ADV_10HDX;
}
my |= PHY_ADV_CSMA;
lan91c11x_write_phy_reg(PHY_AD, my);
/* Enable Autonegotiation */
#if 0
lan91c11x_write_phy_reg(PHY_CTRL,
(PHY_CTRL_ANEGEN | PHY_CTRL_ANEGRST));
#endif
/* Enable full duplex, let MAC take care
* of padding and CRC.
*/
lan91c11x_write_reg(LAN91C11X_TCR,
(LAN91C11X_TCR_PADEN |
LAN91C11X_TCR_SWFDUP));
/* Disable promisc, don'tstrip CRC */
lan91c11x_write_reg(LAN91C11X_RCR, 0);
/* Enable auto-negotiation, LEDA is link, LEDB is traffic */
lan91c11x_write_reg(LAN91C11X_RPCR,
(LAN91C11X_RPCR_ANEG |
LAN91C11X_RPCR_LS2B));
/* Don't add wait states, enable PHY power */
lan91c11x_write_reg(LAN91C11X_CONFIG,
(LAN91C11X_CONFIG_NOWAIT |
LAN91C11X_CONFIG_PWR));
/* Disable error interrupts, enable auto release */
lan91c11x_write_reg(LAN91C11X_CTRL, LAN91C11X_CTRL_AUTO);
/* Reset MMU */
lan91c11x_write_reg(LAN91C11X_MMUCMD,
LAN91C11X_MMUCMD_RESETMMU );
rtems_task_wake_after(100);
/* Enable Autonegotiation */
lan91c11x_write_phy_reg(PHY_CTRL, 0x3000);
rtems_task_wake_after(100);
/* Enable Interrupts for RX */
lan91c11x_write_reg(LAN91C11X_INT, LAN91C11X_INT_RXMASK);
/* Enable interrupts on GPIO Port A3 */
/* Make pin 3 an input */
MC9328MXL_GPIOA_DDIR &= ~bit(3);
/* Use GPIO function for pin 3 */
MC9328MXL_GPIOA_GIUS |= bit(3);
/* Set for active high, level triggered interupt */
MC9328MXL_GPIOA_ICR1 = ((MC9328MXL_GPIOA_ICR1 & ~(3 << 6)) |
(2 << 6));
/* Enable GPIO port A3 interrupt */
MC9328MXL_GPIOA_IMR |= bit(3);
/* Install the interrupt handler */
BSP_install_rtems_irq_handler(&mc9328mxl_enet_isr_data);
} /* mc9328mxl_enet_init_hw() */
/*
* Initialize the ethernet hardware
*/
static void
m8xx_enet_initialize (struct m8xx_enet_struct *sc)
{
int i;
unsigned char *hwaddr;
/*
* Configure port A
* PA15 is enet RxD. Set PAPAR(15) to 1, PADIR(15) to 0.
* PA14 is enet TxD. Set PAPAR(14) to 1, PADIR(14) to 0, PAODR(14) to 0.
* PA7 is input CLK1. Set PAPAR(7) to 1, PADIR(7) to 0.
* PA6 is input CLK2. Set PAPAR(6) to 1, PADIR(6) to 0.
*/
m8xx.papar |= 0x303;
m8xx.padir &= ~0x303;
m8xx.paodr &= ~0x2;
/*
* Configure port C
* PC11 is CTS1*. Set PCPAR(11) to 0, PCDIR(11) to 0, and PCSO(11) to 1.
* PC10 is CD1*. Set PCPAR(10) to 0, PCDIR(10) to 0, and PCSO(10) to 1.
*/
m8xx.pcpar &= ~0x30;
m8xx.pcdir &= ~0x30;
m8xx.pcso |= 0x30;
/*
* Connect CLK1 and CLK2 to SCC1 in the SICR.
* CLK1 is TxClk, CLK2 is RxClk. No grant mechanism, SCC1 is directly
* connected to the NMSI pins.
* R1CS = 0b101 (CLK2)
* T1CS = 0b100 (CLK1)
*/
m8xx.sicr |= 0x2C;
/*
* Initialize SDMA configuration register
*/
m8xx.sdcr = 1;
/*
* Allocate mbuf pointers
*/
sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf,
M_MBUF, M_NOWAIT);
sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf,
M_MBUF, M_NOWAIT);
if (!sc->rxMbuf || !sc->txMbuf)
rtems_panic ("No memory for mbuf pointers");
/*
* Set receiver and transmitter buffer descriptor bases
*/
sc->rxBdBase = m8xx_bd_allocate(sc->rxBdCount);
sc->txBdBase = m8xx_bd_allocate(sc->txBdCount);
m8xx.scc1p.rbase = (char *)sc->rxBdBase - (char *)&m8xx;
m8xx.scc1p.tbase = (char *)sc->txBdBase - (char *)&m8xx;
/*
* Send "Init parameters" command
*/
m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SCC1);
/*
* Set receive and transmit function codes
*/
m8xx.scc1p.rfcr = M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0);
m8xx.scc1p.tfcr = M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0);
/*
* Set maximum receive buffer length
*/
m8xx.scc1p.mrblr = RBUF_SIZE;
/*
* Set CRC parameters
*/
m8xx.scc1p.un.ethernet.c_pres = 0xFFFFFFFF;
m8xx.scc1p.un.ethernet.c_mask = 0xDEBB20E3;
/*
* Clear diagnostic counters
*/
m8xx.scc1p.un.ethernet.crcec = 0;
m8xx.scc1p.un.ethernet.alec = 0;
m8xx.scc1p.un.ethernet.disfc = 0;
/*
* Set pad value
*/
m8xx.scc1p.un.ethernet.pads = 0x8888;
/*
* Set retry limit
*/
m8xx.scc1p.un.ethernet.ret_lim = 15;
/*
* Set maximum and minimum frame length
*/
m8xx.scc1p.un.ethernet.mflr = 1518;
m8xx.scc1p.un.ethernet.minflr = 64;
m8xx.scc1p.un.ethernet.maxd1 = MAX_MTU_SIZE;
m8xx.scc1p.un.ethernet.maxd2 = MAX_MTU_SIZE;
/*
* Clear group address hash table
*/
m8xx.scc1p.un.ethernet.gaddr1 = 0;
m8xx.scc1p.un.ethernet.gaddr2 = 0;
m8xx.scc1p.un.ethernet.gaddr3 = 0;
m8xx.scc1p.un.ethernet.gaddr4 = 0;
/*
* Set our physical address
*/
hwaddr = sc->arpcom.ac_enaddr;
m8xx.scc1p.un.ethernet.paddr_h = (hwaddr[5] << 8) | hwaddr[4];
m8xx.scc1p.un.ethernet.paddr_m = (hwaddr[3] << 8) | hwaddr[2];
m8xx.scc1p.un.ethernet.paddr_l = (hwaddr[1] << 8) | hwaddr[0];
/*
* Aggressive retry
*/
m8xx.scc1p.un.ethernet.p_per = 0;
/*
* Clear individual address hash table
*/
m8xx.scc1p.un.ethernet.iaddr1 = 0;
m8xx.scc1p.un.ethernet.iaddr2 = 0;
m8xx.scc1p.un.ethernet.iaddr3 = 0;
m8xx.scc1p.un.ethernet.iaddr4 = 0;
/*
* Clear temp address
*/
m8xx.scc1p.un.ethernet.taddr_l = 0;
m8xx.scc1p.un.ethernet.taddr_m = 0;
m8xx.scc1p.un.ethernet.taddr_h = 0;
/*
* Set up receive buffer descriptors
*/
for (i = 0 ; i < sc->rxBdCount ; i++) {
(sc->rxBdBase + i)->status = 0;
}
/*
* Set up transmit buffer descriptors
*/
for (i = 0 ; i < sc->txBdCount ; i++) {
(sc->txBdBase + i)->status = 0;
sc->txMbuf[i] = NULL;
}
sc->txBdHead = sc->txBdTail = 0;
sc->txBdActiveCount = 0;
/*
* Clear any outstanding events
*/
m8xx.scc1.scce = 0xFFFF;
/*
* Set up interrupts
*/
if (!BSP_install_rtems_irq_handler (ðernetSCC1IrqData)) {
rtems_panic ("Can't attach M8xx SCC1 interrupt handler\n");
}
m8xx.scc1.sccm = 0; /* No interrupts unmasked till necessary */
/*
* Set up General SCC Mode Register
* Ethernet configuration
*/
m8xx.scc1.gsmr_h = 0x0;
m8xx.scc1.gsmr_l = 0x1088000c;
/*
* Set up data synchronization register
* Ethernet synchronization pattern
*/
m8xx.scc1.dsr = 0xd555;
/*
* Set up protocol-specific mode register
* No Heartbeat check
* No force collision
* Discard short frames
* Individual address mode
* Ethernet CRC
* Not promisuous
* Ignore/accept broadcast packets as specified
* Normal backoff timer
* No loopback
* No input sample at end of frame
* 64-byte limit for late collision
* Wait 22 bits before looking for start of frame delimiter
* Disable full-duplex operation
*/
m8xx.scc1.psmr = 0x080A | (sc->acceptBroadcast ? 0 : 0x100);
/*
* Enable the TENA (RTS1*) pin
*/
m8xx.pcpar |= 0x1;
m8xx.pcdir &= ~0x1;
/*
* Enable receiver and transmitter
*/
m8xx.scc1.gsmr_l = 0x1088003c;
}
/*
* Initialize the ethernet hardware
*/
static void
wd8003Enet_initialize_hardware (struct wd_softc *sc)
{
int i1, ultra;
char cc1, cc2;
unsigned char temp;
rtems_status_code st;
unsigned int tport;
unsigned char *hwaddr;
tport = sc->port;
/* address from board ROM */
inport_byte(tport+0x04, temp);
outport_byte(tport+0x04, temp & 0x7f);
hwaddr = sc->arpcom.ac_enaddr;
for (i1=cc2=0; i1<8; i1++) {
inport_byte(tport + ADDROM + i1, cc1);
cc2 += cc1;
if (i1 < 6)
hwaddr[i1] = cc1;
}
inport_byte(tport+0x04, temp);
outport_byte(tport+0x04, temp | 0x80); /* alternate registers */
outport_byte(tport+W83CREG, MSK_RESET); /* reset board, set buffer */
outport_byte(tport+W83CREG, 0);
outport_byte(tport+W83CREG, MSK_ENASH + (int)((sc->bpar>>13)&0x3f));
outport_byte(tport+CMDR, MSK_PG0 + MSK_RD2);
cc1 = MSK_BMS + MSK_FT10; /* configure 8 or 16 bits */
inport_byte(tport+0x07, temp) ;
ultra = ((temp & 0xf0) == 0x20 || (temp & 0xf0) == 0x40);
if (ultra)
cc1 = MSK_WTS + MSK_BMS + MSK_FT10;
outport_byte(tport+DCR, cc1);
outport_byte(tport+RBCR0, 0);
outport_byte(tport+RBCR1, 0);
outport_byte(tport+RCR, MSK_MON); /* disable the rxer */
outport_byte(tport+TCR, 0); /* normal operation */
outport_byte(tport+PSTOP, OUTPAGE); /* init PSTOP */
outport_byte(tport+PSTART, 0); /* init PSTART */
outport_byte(tport+BNRY, -1); /* init BNRY */
outport_byte(tport+ISR, -1); /* clear IR's */
outport_byte(tport+IMR, 0x15); /* enable interrupt */
outport_byte(tport+CMDR, MSK_PG1 + MSK_RD2);
for (i1=0; i1<6; i1++) /* initial physical addr */
outport_byte(tport+PAR+i1, hwaddr[i1]);
for (i1=0; i1<MARsize; i1++) /* clear multicast */
outport_byte(tport+MAR+i1, 0);
outport_byte(tport+CURR, 0); /* init current packet */
outport_byte(tport+CMDR, MSK_PG0 + MSK_RD2);
outport_byte(tport+CMDR, MSK_STA + MSK_RD2); /* put 8390 on line */
outport_byte(tport+RCR, MSK_AB); /* MSK_AB accept broadcast */
if (ultra) {
inport_byte(tport+0x0c, temp);
outport_byte(tport+0x0c, temp | 0x80);
outport_byte(tport+0x05, 0x80);
outport_byte(tport+0x06, 0x01);
}
/*
* Set up interrupts
*/
sc->irqInfo.hdl = wd8003Enet_interrupt_handler;
sc->irqInfo.on = nopOn;
sc->irqInfo.off = nopOn;
sc->irqInfo.isOn = wdIsOn;
st = BSP_install_rtems_irq_handler (&sc->irqInfo);
if (!st)
rtems_panic ("Can't attach WD interrupt handler for irq %d\n",
sc->irqInfo.name);
}
void
m8xx_uart_scc_initialize (int minor)
{
unsigned char brg;
volatile m8xxSCCparms_t *sccparms = 0;
volatile m8xxSCCRegisters_t *sccregs = 0;
/*
* Check that minor number is valid
*/
if ( (minor < SCC2_MINOR) || (minor > NUM_PORTS-1) )
return;
/* Get the sicr clock source bit values for 9600 bps */
brg = m8xx_get_brg_clk(9600);
/*
* Allocate buffer descriptors
*/
RxBd[minor] = m8xx_bd_allocate(1);
TxBd[minor] = m8xx_bd_allocate(1);
/*
* Get the address of the parameter RAM for the specified port,
* configure I/O port A,C & D and put SMC in NMSI mode, connect
* the SCC to the appropriate BRG.
*
* SCC2 TxD is shared with port A bit 12
* SCC2 RxD is shared with port A bit 13
* SCC1 TxD is shared with port A bit 14
* SCC1 RxD is shared with port A bit 15
* SCC4 DCD is shared with port C bit 4
* SCC4 CTS is shared with port C bit 5
* SCC3 DCD is shared with port C bit 6
* SCC3 CTS is shared with port C bit 7
* SCC2 DCD is shared with port C bit 8
* SCC2 CTS is shared with port C bit 9
* SCC1 DCD is shared with port C bit 10
* SCC1 CTS is shared with port C bit 11
* SCC2 RTS is shared with port C bit 14
* SCC1 RTS is shared with port C bit 15
* SCC4 RTS is shared with port D bit 6
* SCC3 RTS is shared with port D bit 7
* SCC4 TxD is shared with port D bit 8
* SCC4 RxD is shared with port D bit 9
* SCC3 TxD is shared with port D bit 10
* SCC3 RxD is shared with port D bit 11
*/
switch (minor) {
case SCC2_MINOR:
sccparms = &m8xx.scc2p;
sccregs = &m8xx.scc2;
m8xx.papar |= 0x000C; /* PA12 & PA13 are dedicated peripheral pins */
m8xx.padir &= ~0x000C; /* PA13 & PA12 must not drive the UART lines */
m8xx.paodr &= ~0x000C; /* PA12 & PA13 are not open drain */
m8xx.pcpar |= 0x0002; /* PC14 is SCC2 RTS */
m8xx.pcpar &= ~0x00C0; /* PC8 & PC9 are SCC2 DCD and CTS */
m8xx.pcdir &= ~0x00C2; /* PC8, PC9 & PC14 must not drive the UART lines */
m8xx.pcso |= 0x00C0; /* Enable DCD and CTS inputs */
m8xx.sicr &= 0xFFFF00FF; /* Clear TCS2 & RCS2, GR2=no grant, SC2=NMSI mode */
m8xx.sicr |= (brg<<11) | (brg<<8); /* TCS2 = RCS2 = brg */
break;
#ifdef mpc860
case SCC3_MINOR:
sccparms = &m8xx.scc3p;
sccregs = &m8xx.scc3;
m8xx.pcpar &= ~0x0300; /* PC6 & PC7 are SCC3 DCD and CTS */
m8xx.pcdir &= ~0x0300; /* PC6 & PC7 must not drive the UART lines */
m8xx.pcso |= 0x0300; /* Enable DCD and CTS inputs */
m8xx.pdpar |= 0x0130; /* PD7, PD10 & PD11 are dedicated peripheral pins */
m8xx.sicr &= 0xFF00FFFF; /* Clear TCS3 & RCS3, GR3=no grant, SC3=NMSI mode */
m8xx.sicr |= (brg<<19) | (brg<<16); /* TCS3 = RCS3 = brg */
break;
case SCC4_MINOR:
sccparms = &m8xx.scc4p;
sccregs = &m8xx.scc4;
m8xx.pcpar &= ~0x0C00; /* PC4 & PC5 are SCC4 DCD and CTS */
m8xx.pcdir &= ~0x0C00; /* PC4 & PC5 must not drive the UART lines */
m8xx.pcso |= 0x0C00; /* Enable DCD and CTS inputs */
m8xx.pdpar |= 0x02C0; /* PD6, PD8 & PD9 are dedicated peripheral pins */
m8xx.sicr &= 0x00FFFFFF; /* Clear TCS4 & RCS4, GR4=no grant, SC4=NMSI mode */
m8xx.sicr |= (brg<<27) | (brg<<24); /* TCS4 = RCS4 = brg */
break;
#endif
}
/*
* Set up SDMA
*/
m8xx.sdcr = 0x01; /* as per section 16.10.2.1 MPC821UM/AD */
/*
* Set up the SCC parameter RAM.
*/
sccparms->rbase = (char *)RxBd[minor] - (char *)&m8xx;
sccparms->tbase = (char *)TxBd[minor] - (char *)&m8xx;
sccparms->rfcr = M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0);
sccparms->tfcr = M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0);
if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 )
sccparms->mrblr = RXBUFSIZE; /* Maximum Rx buffer size */
else
sccparms->mrblr = 1; /* Maximum Rx buffer size */
sccparms->un.uart.max_idl = 10; /* Set nb of idle chars to close buffer */
sccparms->un.uart.brkcr = 0; /* Set nb of breaks to send for STOP Tx */
sccparms->un.uart.parec = 0; /* Clear parity error counter */
sccparms->un.uart.frmec = 0; /* Clear framing error counter */
sccparms->un.uart.nosec = 0; /* Clear noise counter */
sccparms->un.uart.brkec = 0; /* Clear break counter */
sccparms->un.uart.uaddr[0] = 0; /* Not in multidrop mode, so clear */
sccparms->un.uart.uaddr[1] = 0; /* Not in multidrop mode, so clear */
sccparms->un.uart.toseq = 0; /* Tx Out-Of-SEQuence--no XON/XOFF now */
sccparms->un.uart.character[0] = 0x8000; /* Entry is invalid */
sccparms->un.uart.character[1] = 0x8000; /* Entry is invalid */
sccparms->un.uart.character[2] = 0x8000; /* Entry is invalid */
sccparms->un.uart.character[3] = 0x8000; /* Entry is invalid */
sccparms->un.uart.character[4] = 0x8000; /* Entry is invalid */
sccparms->un.uart.character[5] = 0x8000; /* Entry is invalid */
sccparms->un.uart.character[6] = 0x8000; /* Entry is invalid */
sccparms->un.uart.character[7] = 0x8000; /* Entry is invalid */
sccparms->un.uart.rccm = 0xc0ff; /* No masking */
/*
* Set up the Receive Buffer Descriptor
*/
RxBd[minor]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP | M8xx_BD_INTERRUPT;
RxBd[minor]->length = 0;
RxBd[minor]->buffer = rxBuf[minor];
/*
* Setup the Transmit Buffer Descriptor
*/
TxBd[minor]->status = M8xx_BD_WRAP;
/*
* Set up SCCx general and protocol-specific mode registers
*/
sccregs->gsmr_h = 0x00000020; /* RFW=low latency operation */
sccregs->gsmr_l = 0x00028004; /* TDCR=RDCR=16x clock mode, MODE=uart*/
sccregs->scce = ~0; /* Clear any pending event */
sccregs->sccm = 0; /* Mask all interrupt/event sources */
sccregs->psmr = 0x3000; /* Normal operation & mode, 1 stop bit,
8 data bits, no parity */
sccregs->dsr = 0x7E7E; /* No fractional stop bits */
sccregs->gsmr_l = 0x00028034; /* ENT=enable Tx, ENR=enable Rx */
/*
* Initialize the Rx and Tx with the new parameters.
*/
switch (minor) {
case SCC2_MINOR:
m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SCC2);
break;
#ifdef mpc860
case SCC3_MINOR:
m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SCC3);
break;
case SCC4_MINOR:
m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SCC4);
break;
#endif
}
if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 ) {
consoleIrqData.on = m8xx_scc_enable;
consoleIrqData.off = m8xx_scc_disable;
consoleIrqData.isOn = m8xx_scc_isOn;
switch (minor) {
case SCC2_MINOR:
consoleIrqData.name = BSP_CPM_IRQ_SCC2;
consoleIrqData.hdl = m8xx_scc2_interrupt_handler;
break;
#ifdef mpc860
case SCC3_MINOR:
consoleIrqData.name = BSP_CPM_IRQ_SCC3;
consoleIrqData.hdl = m8xx_scc3_interrupt_handler;
break;
case SCC4_MINOR:
consoleIrqData.name = BSP_CPM_IRQ_SCC4;
consoleIrqData.hdl = m8xx_scc4_interrupt_handler;
break;
#endif /* mpc860 */
}
if (!BSP_install_rtems_irq_handler (&consoleIrqData)) {
printk("Unable to connect SCC Irq handler\n");
rtems_fatal_error_occurred(1);
}
}
}
void
m8xx_uart_smc_initialize (int minor)
{
unsigned char brg;
volatile m8xxSMCparms_t *smcparms = 0;
volatile m8xxSMCRegisters_t *smcregs = 0;
/*
* Check that minor number is valid
*/
if ( (minor < SMC1_MINOR) || (minor > SMC2_MINOR) )
return;
m8xx.sdcr = 0x01; /* as per section 16.10.2.1 MPC821UM/AD */
/* Get the simode clock source bit values for 9600 bps */
brg = m8xx_get_brg_clk(9600);
/*
* Allocate buffer descriptors
*/
RxBd[minor] = m8xx_bd_allocate (1);
TxBd[minor] = m8xx_bd_allocate (1);
/*
* Get the address of the parameter RAM for the specified port,
* configure I/O port B and put SMC in NMSI mode, connect the
* SMC to the appropriate BRG.
*
* SMC2 RxD is shared with port B bit 20
* SMC2 TxD is shared with port B bit 21
* SMC1 RxD is shared with port B bit 24
* SMC1 TxD is shared with port B bit 25
*/
switch (minor) {
case SMC1_MINOR:
smcparms = &m8xx.smc1p;
smcregs = &m8xx.smc1;
m8xx.pbpar |= 0x000000C0; /* PB24 & PB25 are dedicated peripheral pins */
m8xx.pbdir &= ~0x000000C0; /* PB24 & PB25 must not drive UART lines */
m8xx.pbodr &= ~0x000000C0; /* PB24 & PB25 are not open drain */
m8xx.simode &= 0xFFFF0FFF; /* Clear SMC1CS & SMC1 for NMSI mode */
m8xx.simode |= brg << 12; /* SMC1CS = brg */
break;
case SMC2_MINOR:
smcparms = &m8xx.smc2p;
smcregs = &m8xx.smc2;
m8xx.pbpar |= 0x00000C00; /* PB20 & PB21 are dedicated peripheral pins */
m8xx.pbdir &= ~0x00000C00; /* PB20 & PB21 must not drive the UART lines */
m8xx.pbodr &= ~0x00000C00; /* PB20 & PB21 are not open drain */
m8xx.simode &= 0x0FFFFFFF; /* Clear SMC2CS & SMC2 for NMSI mode */
m8xx.simode |= brg << 28; /* SMC2CS = brg */
break;
}
/*
* Set up SMC1 parameter RAM common to all protocols
*/
smcparms->rbase = (char *)RxBd[minor] - (char *)&m8xx;
smcparms->tbase = (char *)TxBd[minor] - (char *)&m8xx;
smcparms->rfcr = M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0);
smcparms->tfcr = M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0);
if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 )
smcparms->mrblr = RXBUFSIZE; /* Maximum Rx buffer size */
else
smcparms->mrblr = 1; /* Maximum Rx buffer size */
/*
* Set up SMC1 parameter RAM UART-specific parameters
*/
smcparms->un.uart.max_idl = 10; /* Set nb of idle chars to close buffer */
smcparms->un.uart.brkcr = 0; /* Set nb of breaks to send for STOP Tx */
smcparms->un.uart.brkec = 0; /* Clear break counter */
/*
* Set up the Receive Buffer Descriptor
*/
RxBd[minor]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP | M8xx_BD_INTERRUPT;
RxBd[minor]->length = 0;
RxBd[minor]->buffer = rxBuf[minor];
/*
* Setup the Transmit Buffer Descriptor
*/
TxBd[minor]->status = M8xx_BD_WRAP;
/*
* Set up SMCx general and protocol-specific mode registers
*/
smcregs->smce = ~0; /* Clear any pending events */
smcregs->smcm = 0; /* Enable SMC Rx & Tx interrupts */
smcregs->smcmr = M8xx_SMCMR_CLEN(9) | M8xx_SMCMR_SM_UART;
/*
* Send "Init parameters" command
*/
switch (minor) {
case SMC1_MINOR:
m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SMC1);
break;
case SMC2_MINOR:
m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SMC2);
break;
}
/*
* Enable receiver and transmitter
*/
smcregs->smcmr |= M8xx_SMCMR_TEN | M8xx_SMCMR_REN;
if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 ) {
consoleIrqData.on = m8xx_smc_enable;
consoleIrqData.off = m8xx_smc_disable;
consoleIrqData.isOn = m8xx_smc_isOn;
switch (minor) {
case SMC1_MINOR:
consoleIrqData.name = BSP_CPM_IRQ_SMC1;
consoleIrqData.hdl = m8xx_smc1_interrupt_handler;
break;
case SMC2_MINOR:
consoleIrqData.name = BSP_CPM_IRQ_SMC2_OR_PIP;
consoleIrqData.hdl = m8xx_smc2_interrupt_handler;
break;
}
if (!BSP_install_rtems_irq_handler (&consoleIrqData)) {
printk("Unable to connect SMC Irq handler\n");
rtems_fatal_error_occurred(1);
}
}
}
/*
* Initialize the SCC hardware
* Configure I/O ports for SCC3
* Internal Tx clock, External Rx clock
*/
static void
m8260_scc_initialize_hardware (struct m8260_hdlc_struct *sc)
{
int i;
int brg;
rtems_status_code status;
/* RxD PB14 */
m8260.pparb |= 0x00020000;
m8260.psorb &= ~0x00020000;
m8260.pdirb &= ~0x00020000;
/* RxC (CLK5) PC27 */
m8260.pparc |= 0x00000010;
m8260.psorc &= ~0x00000010;
m8260.pdirc &= ~0x00000010;
/* TxD PD24 and TxC PD10 (BRG4) */
m8260.ppard |= 0x00200080;
m8260.psord |= 0x00200000;
m8260.psord &= ~0x00000080;
m8260.pdird |= 0x00200080;
/* External Rx Clock from CLK5 */
if( m8xx_get_clk( M8xx_CLK_5 ) == -1 )
printk( "Error allocating CLK5 for network device.\n" );
else
m8260.cmxscr |= 0x00002000;
/* Internal Tx Clock from BRG4 */
if( (brg = m8xx_get_brg(M8xx_BRG_4, 8000000 )) == -1 )
printk( "Error allocating BRG for network device\n" );
else
m8260.cmxscr |= ((unsigned)brg << 8);
/*
* Allocate mbuf pointers
*/
sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf,
M_MBUF, M_NOWAIT);
sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf,
M_MBUF, M_NOWAIT);
if (!sc->rxMbuf || !sc->txMbuf)
rtems_panic ("No memory for mbuf pointers");
/*
* Set receiver and transmitter buffer descriptor bases
*/
sc->rxBdBase = m8xx_bd_allocate (sc->rxBdCount);
sc->txBdBase = m8xx_bd_allocate (sc->txBdCount);
m8260.scc3p.rbase = (char *)sc->rxBdBase - (char *)&m8260;
m8260.scc3p.tbase = (char *)sc->txBdBase - (char *)&m8260;
/*
* Send "Init parameters" command
*/
m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SCC3 );
/*
* Set receive and transmit function codes
*/
m8260.scc3p.rfcr = M8260_RFCR_MOT | M8260_RFCR_60X_BUS;
m8260.scc3p.tfcr = M8260_TFCR_MOT | M8260_TFCR_60X_BUS;
/*
* Set maximum receive buffer length
*/
m8260.scc3p.mrblr = RBUF_SIZE;
m8260.scc3p.un.hdlc.c_mask = 0xF0B8;
m8260.scc3p.un.hdlc.c_pres = 0xFFFF;
m8260.scc3p.un.hdlc.disfc = 0;
m8260.scc3p.un.hdlc.crcec = 0;
m8260.scc3p.un.hdlc.abtsc = 0;
m8260.scc3p.un.hdlc.nmarc = 0;
m8260.scc3p.un.hdlc.retrc = 0;
m8260.scc3p.un.hdlc.rfthr = 1;
m8260.scc3p.un.hdlc.mflr = RBUF_SIZE;
m8260.scc3p.un.hdlc.hmask = 0x0000; /* promiscuous */
m8260.scc3p.un.hdlc.haddr1 = 0xFFFF; /* Broadcast address */
m8260.scc3p.un.hdlc.haddr2 = 0xFFFF; /* Station address */
m8260.scc3p.un.hdlc.haddr3 = 0xFFFF; /* Dummy */
m8260.scc3p.un.hdlc.haddr4 = 0xFFFF; /* Dummy */
/*
* Send "Init parameters" command
*/
/*
m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SCC3 );
*/
/*
* Set up receive buffer descriptors
*/
for (i = 0 ; i < sc->rxBdCount ; i++) {
(sc->rxBdBase + i)->status = 0;
}
/*
* Set up transmit buffer descriptors
*/
for (i = 0 ; i < sc->txBdCount ; i++) {
(sc->txBdBase + i)->status = 0;
sc->txMbuf[i] = NULL;
}
sc->txBdHead = sc->txBdTail = 0;
sc->txBdActiveCount = 0;
m8260.scc3.sccm = 0; /* No interrupts unmasked till necessary */
/*
* Clear any outstanding events
*/
m8260.scc3.scce = 0xFFFF;
/*
* Set up interrupts
*/
status = BSP_install_rtems_irq_handler (&hdlcSCC3IrqData);
/*
printk( "status = %d, Success = %d\n", status, RTEMS_SUCCESSFUL );
*/
if (status != 1 /*RTEMS_SUCCESSFUL*/ ) {
rtems_panic ("Can't attach M8260 SCC3 interrupt handler: %s\n",
rtems_status_text (status));
}
m8260.scc3.sccm = 0; /* No interrupts unmasked till necessary */
m8260.scc3.gsmr_h = 0;
m8260.scc3.gsmr_l = 0x10000000;
m8260.scc3.dsr = 0x7E7E; /* flag character */
m8260.scc3.psmr = 0x2000; /* 2 flags between Tx'd frames */
/* printk("scc3 init\n" ); */
m8260.scc3.gsmr_l |= 0x00000030; /* Set ENR and ENT to enable Rx and Tx */
}
/*
* initialization of channel info.
*/
rtems_status_code mscan_channel_initialize(rtems_device_major_number major,
rtems_device_minor_number minor)
{
rtems_status_code status;
struct mscan_channel_info *chan = &chan_info[minor];
/* set registers according to MSCAN channel information */
switch (minor) {
case MSCAN_A:
chan->rx_qname = rtems_build_name('C', 'N', 'A', 'Q');
chan->tx_rb_sname = rtems_build_name('C', 'N', 'A', 'S');
/* register RTEMS device names for MSCAN A */
if ((status =
rtems_io_register_name(MSCAN_A_DEV_NAME, major,
MSCAN_A)) != RTEMS_SUCCESSFUL)
return status;
/* register RTEMS device names for MSCAN 0 */
if ((status =
rtems_io_register_name(MSCAN_0_DEV_NAME, major,
MSCAN_A)) != RTEMS_SUCCESSFUL)
return status;
/* allocate the space for MSCAN A tx ring buffer */
if (((chan->tx_ring_buf.buf_ptr) =
malloc(sizeof (struct can_message) * (NO_OF_MSCAN_TX_BUFF + 1))) !=
NULL) {
chan->tx_ring_buf.head_ptr = chan->tx_ring_buf.tail_ptr =
chan->tx_ring_buf.buf_ptr;
} else {
return RTEMS_UNSATISFIED;
}
break;
case MSCAN_B:
chan->rx_qname = rtems_build_name('C', 'N', 'B', 'Q');
chan->tx_rb_sname = rtems_build_name('C', 'N', 'B', 'S');
/* register RTEMS device names for MSCAN B */
if ((status =
rtems_io_register_name(MSCAN_B_DEV_NAME, major,
MSCAN_B)) != RTEMS_SUCCESSFUL)
return status;
/* register RTEMS device names for MSCAN 1 */
if ((status =
rtems_io_register_name(MSCAN_1_DEV_NAME, major,
MSCAN_B)) != RTEMS_SUCCESSFUL)
return status;
/* allocate the space for MSCAN B tx ring buffer */
if (((chan->tx_ring_buf.buf_ptr) =
malloc(sizeof (struct can_message) * (NO_OF_MSCAN_TX_BUFF + 1))) !=
NULL) {
chan->tx_ring_buf.head_ptr = chan->tx_ring_buf.tail_ptr =
chan->tx_ring_buf.buf_ptr;
} else {
return RTEMS_UNSATISFIED;
}
break;
default:
return RTEMS_UNSATISFIED;
break;
}
/* create RTEMS rx message queue */
status =
rtems_message_queue_create(chan->rx_qname, (uint32_t) NO_OF_MSCAN_RX_BUFF,
(uint32_t)
MSCAN_MESSAGE_SIZE(sizeof (struct can_message)),
(rtems_attribute) RTEMS_LOCAL | RTEMS_FIFO,
(rtems_id *) & (chan->rx_qid));
/* create counting RTEMS tx ring buffer semaphore */
status =
rtems_semaphore_create(chan->tx_rb_sname, (uint32_t) (NO_OF_MSCAN_TX_BUFF),
RTEMS_COUNTING_SEMAPHORE | RTEMS_NO_INHERIT_PRIORITY
| RTEMS_NO_PRIORITY_CEILING | RTEMS_LOCAL,
(rtems_task_priority) 0,
(rtems_id *) & (chan->tx_rb_sid));
/* Set up interrupts */
if (!BSP_install_rtems_irq_handler(&(mpc5200_mscan_irq_data[minor])))
rtems_panic("Can't attach MPC5x00 MSCAN interrupt handler %d\n", minor);
/* basic setup for channel info. struct. */
chan->regs = (mscan *) &(mpc5200.mscan[minor]);
chan->int_rx_err = 0;
chan->id_extended = FALSE;
chan->mode = MSCAN_INITIALIZED_MODE;
chan->tx_buf_no = NO_OF_MSCAN_TX_BUFF;
return status;
}
int
NET_EMBEMB(rtems_,NETDRIVER_PREFIX,_attach)
(struct rtems_bsdnet_ifconfig *config, int attaching)
{
int error = 0;
device_t dev = net_dev_get(config);
struct NET_SOFTC *sc;
struct ifnet *ifp;
#ifndef HAVE_LIBBSPEXT
rtems_irq_connect_data irq_data = {
0,
the_net_isr,
#if ISMINVERSION(4,6,99)
0,
#endif
noop,
noop,
noop1 };
#endif
if ( !dev )
return 1;
if ( !dev->d_softc.NET_SOFTC_BHANDLE_FIELD ) {
#if defined(NETDRIVER_PCI)
device_printf(dev,NETDRIVER" unit not configured; executing setup...");
/* setup should really be performed prior to attaching.
* Wipe the device; setup and re-obtain the device...
*/
memset(dev,0,sizeof(*dev));
error = NET_EMBEMB(rtems_,NETDRIVER_PREFIX,_pci_setup)(-1);
/* re-obtain the device */
dev = net_dev_get(config);
if ( !dev ) {
printk("Unable to re-assign device structure???\n");
return 1;
}
if (error <= 0) {
device_printf(dev,NETDRIVER" FAILED; unable to attach interface, sorry\n");
return 1;
}
device_printf(dev,"success\n");
#else
device_printf(dev,NETDRIVER" unit not configured; use 'rtems_"NETDRIVER"_setup()'\n");
return 1;
#endif
}
if ( !net_driver_ticks_per_sec )
rtems_clock_get( RTEMS_CLOCK_GET_TICKS_PER_SECOND, &net_driver_ticks_per_sec );
sc = device_get_softc( dev );
ifp = &sc->arpcom.ac_if;
#ifdef DEBUG_MODULAR
if (!METHODSPTR) {
device_printf(dev,NETDRIVER": method pointer not set\n");
return -1;
}
#endif
if ( attaching ) {
if ( ifp->if_init ) {
device_printf(dev,NETDRIVER" Driver already attached.\n");
return -1;
}
if ( config->hardware_address ) {
/* use configured MAC address */
memcpy(sc->arpcom.ac_enaddr, config->hardware_address, ETHER_ADDR_LEN);
} else {
#ifdef NET_READ_MAC_ADDR
NET_READ_MAC_ADDR(sc);
#endif
}
if ( METHODSPTR->n_attach(dev) ) {
device_printf(dev,NETDRIVER"_attach() failed\n");
return -1;
}
} else {
if ( !ifp->if_init ) {
device_printf(dev,NETDRIVER" Driver not attached.\n");
return -1;
}
if ( METHODSPTR->n_detach ) {
if ( METHODSPTR->n_detach(dev) ) {
device_printf(dev,NETDRIVER"_detach() failed\n");
return -1;
}
} else {
device_printf(dev,NETDRIVER"_detach() not implemented\n");
return -1;
}
}
if ( !sc->tid )
sc->tid = rtems_bsdnet_newproc(NETDRIVER"d", 4096, net_daemon, sc);
if (attaching) {
#ifdef DEBUG
printf("Installing IRQ # %i\n",sc->irq_no);
#endif
#ifdef HAVE_LIBBSPEXT
if ( bspExtInstallSharedISR(sc->irq_no, the_net_isr, sc, 0) )
#else
/* BSP dependent :-( */
irq_data.name = sc->irq_no;
#if ISMINVERSION(4,6,99)
irq_data.handle = (rtems_irq_hdl_param)sc;
#else
thesc = sc;
#endif
if ( ! BSP_install_rtems_irq_handler( &irq_data ) )
#endif
{
fprintf(stderr,NETDRIVER": unable to install ISR\n");
error = -1;
}
} else {
if ( sc->irq_no ) {
#ifdef DEBUG
printf("Removing IRQ # %i\n",sc->irq_no);
#endif
#ifdef HAVE_LIBBSPEXT
if (bspExtRemoveSharedISR(sc->irq_no, the_net_isr, sc))
#else
/* BSP dependent :-( */
irq_data.name = sc->irq_no;
#if ISMINVERSION(4,6,99)
irq_data.handle = (rtems_irq_hdl_param)sc;
#endif
if ( ! BSP_remove_rtems_irq_handler( &irq_data ) )
#endif
{
fprintf(stderr,NETDRIVER": unable to uninstall ISR\n");
error = -1;
}
}
}
return error;
}
