/***************************************************************************//**
* @brief
* Enable/disable the watchdog timer.
*
* @note
* This function modifies the WDOG CTRL register which requires
* synchronization into the low frequency domain. If this register is modified
* before a previous update to the same register has completed, this function
* will stall until the previous synchronization has completed.
*
* @param[in] wdog
* Pointer to WDOG peripheral register block.
*
* @param[in] enable
* true to enable watchdog, false to disable. Watchdog cannot be disabled if
* watchdog has been locked.
******************************************************************************/
void WDOGn_Enable(WDOG_TypeDef *wdog, bool enable)
{
/* SYNCBUSY may stall when locked. */
if (wdog->CTRL & WDOG_CTRL_LOCK)
{
return;
}
if (!enable)
{
/* If the user intends to disable and the WDOG is enabled */
if (BUS_RegBitRead(&wdog->CTRL, _WDOG_CTRL_EN_SHIFT))
{
/* Wait for any pending previous write operation to have been completed in */
/* low frequency domain */
while (wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL)
;
BUS_RegBitWrite(&wdog->CTRL, _WDOG_CTRL_EN_SHIFT, 0);
}
}
else
{
BUS_RegBitWrite(&wdog->CTRL, _WDOG_CTRL_EN_SHIFT, 1);
}
}
/***************************************************************************//**
* @brief
* Restore BURTC to reset state
* @note
* Before accessing the BURTC, BURSTEN in RMU->CTRL must be cleared.
* LOCK will not be reset to default value, as this will disable access
* to core BURTC registers.
******************************************************************************/
void BURTC_Reset(void)
{
bool buResetState;
/* Read reset state, set reset and restore state */
buResetState = BUS_RegBitRead(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT);
BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, 1);
BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, buResetState);
}
