/**
Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
writes the result back to the bit field in the 32-bit port.
Reads the 32-bit PCI configuration register specified by Address, performs a
bitwise OR between the read result and the value specified by
OrData, and writes the result to the 32-bit PCI configuration register
specified by Address. The value written to the PCI configuration register is
returned. This function must guarantee that all PCI read and write operations
are serialized. Extra left bits in OrData are stripped.
If Address > 0x0FFFFFFF, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
If StartBit is greater than 31, then ASSERT().
If EndBit is greater than 31, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
@param Address The PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..31.
@param OrData The value to OR with the PCI configuration register.
@return The value written back to the PCI configuration register.
**/
UINT32
EFIAPI
PciBitFieldOr32 (
IN UINTN Address,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT32 OrData
)
{
return PciWrite32 (
Address,
BitFieldOr32 (PciRead32 (Address), StartBit, EndBit, OrData)
);
}
/**
Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
writes the result back to the bit field in the 32-bit port.
Reads the 32-bit PCI configuration register specified by Address, performs a
bitwise OR between the read result and the value specified by
OrData, and writes the result to the 32-bit PCI configuration register
specified by Address. The value written to the PCI configuration register is
returned. This function must guarantee that all PCI read and write operations
are serialized. Extra left bits in OrData are stripped.
If any reserved bits in Address are set, then ASSERT().
If StartBit is greater than 31, then ASSERT().
If EndBit is greater than 31, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..31.
@param OrData The value to OR with the PCI configuration register.
@return The value written back to the PCI configuration register.
**/
UINT32
EFIAPI
PciSegmentBitFieldOr32 (
IN UINT64 Address,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT32 OrData
)
{
return PciSegmentWrite32 (
Address,
BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData)
);
}
/**
Reads a bit field from a 32-bit value, performs a bitwise AND followed by a
bitwise OR, and returns the result.
Performs a bitwise AND between the bit field specified by StartBit and EndBit
in Operand and the value specified by AndData, followed by a bitwise
inclusive OR with value specified by OrData. All other bits in Operand are
preserved. The new 32-bit value is returned.
If 32-bit operations are not supported, then ASSERT().
If StartBit is greater than 31, then ASSERT().
If EndBit is greater than 31, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..31.
@param AndData The value to AND with the read value from the value.
@param OrData The value to OR with the result of the AND operation.
@return The new 32-bit value.
**/
UINT32
EFIAPI
BitFieldAndThenOr32 (
IN UINT32 Operand,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT32 AndData,
IN UINT32 OrData
)
{
ASSERT (EndBit < sizeof (Operand) * 8);
ASSERT (StartBit <= EndBit);
return BitFieldOr32 (
BitFieldAnd32 (Operand, StartBit, EndBit, AndData),
StartBit,
EndBit,
OrData
);
}
